115 lines
4.5 KiB
C++
115 lines
4.5 KiB
C++
// SPDX-FileCopyrightText: 2024 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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#include "hls_jfjoch.h"
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void load_from_hbm(STREAM_768 &data_in,
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STREAM_768 &data_out,
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hls::stream<axis_completion > &s_axis_completion,
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hls::stream<axis_completion > &m_axis_completion,
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hls::stream<ap_uint<16> > &m_axis_free_handles,
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hls::stream<ap_axiu<256,1,1,1> > &hbm_in_0,
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hls::stream<ap_axiu<256,1,1,1> > &hbm_in_1,
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hls::stream<ap_axiu<256,1,1,1> > &hbm_in_2,
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hls::stream<axis_datamover_ctrl> &datamover_0_cmd,
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hls::stream<axis_datamover_ctrl> &datamover_1_cmd,
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hls::stream<axis_datamover_ctrl> &datamover_2_cmd,
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volatile ap_uint<1> &idle,
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volatile uint32_t &ignore_counter,
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ap_uint<32> hbm_size_bytes) {
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#pragma HLS INTERFACE ap_ctrl_none port=return
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#pragma HLS INTERFACE register both axis port=data_in
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#pragma HLS INTERFACE register both axis port=data_out
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#pragma HLS INTERFACE register both axis port=m_axis_completion
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#pragma HLS INTERFACE register both axis port=s_axis_completion
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#pragma HLS INTERFACE register both axis port=m_axis_free_handles
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#pragma HLS INTERFACE register both axis port=hbm_in_0
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#pragma HLS INTERFACE register both axis port=hbm_in_1
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#pragma HLS INTERFACE register both axis port=hbm_in_2
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#pragma HLS INTERFACE register both axis port=datamover_0_cmd
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#pragma HLS INTERFACE register both axis port=datamover_1_cmd
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#pragma HLS INTERFACE register both axis port=datamover_2_cmd
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#pragma HLS INTERFACE register ap_none port=idle
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#pragma HLS INTERFACE register ap_vld port=ignore_counter
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#pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes
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static uint32_t ignore_counter_internal = 0;
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ignore_counter = ignore_counter_internal;
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idle = 1;
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for (ap_uint<16> i = 0; i < hbm_size_bytes * 4 / (RAW_MODULE_SIZE * sizeof(uint16_t)); i++)
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m_axis_free_handles << i;
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packet_768_t packet;
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{
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#pragma HLS PROTOCOL fixed
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data_in >> packet;
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ap_wait();
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data_out << packet;
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ap_wait();
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idle = 0;
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ignore_counter_internal = 0;
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ignore_counter = ignore_counter_internal;
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ap_wait();
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}
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ap_uint<32> offset_hbm_0 = 22 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_1 = 24 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_2 = 26 * hbm_size_bytes / 32;
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axis_completion cmpl;
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s_axis_completion >> cmpl;
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while (!cmpl.last) {
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if (!cmpl.ignore) {
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m_axis_completion << cmpl;
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size_t offset = ((cmpl.handle / 2) * RAW_MODULE_SIZE * sizeof(uint16_t)) / 64;
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if (cmpl.handle % 2 == 1)
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offset += hbm_size_bytes / 32;
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setup_datamover(datamover_0_cmd, (offset_hbm_0 + offset) * 32, RAW_MODULE_SIZE * sizeof(uint16_t) / 2);
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setup_datamover(datamover_1_cmd, (offset_hbm_1 + offset) * 32, RAW_MODULE_SIZE * sizeof(uint16_t) / 2);
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setup_datamover(datamover_2_cmd, (offset_hbm_2 + offset) * 32, RAW_MODULE_SIZE * sizeof(uint16_t) / 2);
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for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {
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#pragma HLS PIPELINE II=1
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ap_axiu<256, 1, 1, 1> packet_in_0;
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ap_axiu<256, 1, 1, 1> packet_in_1;
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ap_axiu<256, 1, 1, 1> packet_in_2;
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hbm_in_0 >> packet_in_0;
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hbm_in_1 >> packet_in_1;
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hbm_in_2 >> packet_in_2;
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packet_768_t packet_out;
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packet_out.data(255, 0) = packet_in_0.data;
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packet_out.data(511, 256) = packet_in_1.data;
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packet_out.data(767, 512) = packet_in_2.data;
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packet_out.last = (i == RAW_MODULE_SIZE * sizeof(uint16_t) / 64 - 1);
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packet_out.id = 0;
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packet_out.dest = 0;
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packet_out.keep = UINT64_MAX;
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packet_out.strb = UINT64_MAX;
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packet_out.user = 0;
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data_out << packet_out;
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}
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} else {
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if (ignore_counter_internal < UINT32_MAX)
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ignore_counter_internal += 1;
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ignore_counter = ignore_counter_internal;
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}
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m_axis_free_handles << cmpl.handle;
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s_axis_completion >> cmpl;
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}
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m_axis_completion << cmpl;
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m_axis_free_handles << UINT16_MAX;
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data_in >> packet;
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data_out << packet;
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idle = 1;
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}
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