279 lines
10 KiB
C++
279 lines
10 KiB
C++
// SPDX-FileCopyrightText: 2024 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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#include "hls_jfjoch.h"
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#define o(field) offsetof(ModuleStatistics, field)
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#define sf(msg, field, s) msg(o(field)*8 + s - 1, o(field)*8)
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inline ap_uint<1024> fill_module_info(axis_completion &cmpl, ap_uint<PIXEL_COUNT_WIDTH> &pixel_count_result) {
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ap_uint<1024> msg = 0;
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sf(msg, frame_number, 64) = cmpl.frame_number;
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sf(msg, timestamp, 64) = cmpl.timestamp;
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sf(msg, pulse_id, 64) = cmpl.bunchid;
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sf(msg, detector_type, 32) = cmpl.detector_type;
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sf(msg, exptime, 32) = cmpl.exptime;
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sf(msg, debug, 32) = cmpl.debug;
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sf(msg, pedestal, 32) = cmpl.pedestal;
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sf(msg, packet_count, 32) = cmpl.packet_count;
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sf(msg, module_number, 32) = cmpl.module;
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sf(msg, err_pixels, 32) = pixel_count_result(31, 0);
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sf(msg, saturated_pixels, 32) = pixel_count_result(63, 32);
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sf(msg, max_value, 32) = pixel_count_result(95, 64);
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sf(msg, min_value, 32) = pixel_count_result(127,96);
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sf(msg, pixel_sum, 64) = pixel_count_result(191,128);
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sf(msg, masked_pixels, 32) = pixel_count_result(223, 192);
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return msg;
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}
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inline void write_completion(hls::stream<ap_uint<32> > &m_axis_completion,
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const ap_uint<16> &handle,
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const ap_uint<16> &data_collection_id) {
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#pragma HLS INLINE
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m_axis_completion << (data_collection_id, handle);
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}
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void read_request(hls::stream<ap_uint<32> > &s_axis_work_request, ap_uint<16> &handle) {
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#pragma HLS INLINE
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ap_uint<32> tmp1;
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s_axis_work_request >> tmp1;
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handle = tmp1(15, 0);
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}
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void host_writer(STREAM_512 &data_in,
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hls::stream<ap_uint<512>> &adu_histo_in,
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hls::stream<ap_uint<512>> &integration_in,
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hls::stream<ap_uint<512>> &spot_finder_in,
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hls::stream<ap_uint<512>> &roi_count_in,
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hls::stream<ap_uint<PIXEL_COUNT_WIDTH>> &pixel_calc_in,
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hls::stream<axis_completion > &s_axis_completion,
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hls::stream<ap_axiu<512,1,1,1> > &host_memory_out,
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hls::stream<axis_datamover_ctrl> &datamover_out_cmd,
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hls::stream<ap_uint<32> > &s_axis_work_request,
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hls::stream<ap_uint<32> > &m_axis_completion,
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const uint64_t *dma_address_table,
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volatile uint64_t &packets_processed,
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volatile ap_uint<1> &idle,
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volatile ap_uint<1> &in_cancel,
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volatile ap_uint<3> &state) {
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#pragma HLS INTERFACE ap_ctrl_none port=return
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#pragma HLS INTERFACE register both axis port=data_in
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#pragma HLS INTERFACE register both axis port=adu_histo_in
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#pragma HLS INTERFACE register both axis port=integration_in
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#pragma HLS INTERFACE register both axis port=spot_finder_in
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#pragma HLS INTERFACE register both axis port=roi_count_in
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#pragma HLS INTERFACE register both axis port=pixel_calc_in
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#pragma HLS INTERFACE register both axis port=s_axis_completion
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#pragma HLS INTERFACE register both axis port=host_memory_out
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#pragma HLS INTERFACE register both axis port=datamover_out_cmd
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#pragma HLS INTERFACE register both axis port=m_axis_completion
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#pragma HLS INTERFACE register both axis port=s_axis_work_request
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#pragma HLS INTERFACE register ap_vld port=packets_processed
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#pragma HLS INTERFACE register ap_none port=idle
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#pragma HLS INTERFACE register ap_none port=in_cancel
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#pragma HLS INTERFACE register ap_none port=state
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#pragma HLS INTERFACE mode=m_axi port=dma_address_table bundle=dma_address_table depth=65536 offset=off \
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max_read_burst_length=2 max_write_burst_length=2 latency=10 num_write_outstanding=1 num_read_outstanding=1
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idle = 1;
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state = 0;
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ap_uint<16> req_handle;
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ap_uint<16> req_handle_send = HANDLE_START;
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ap_uint<64> req_host_offset;
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while (data_in.empty()) {
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if (!s_axis_work_request.empty()) {
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#pragma HLS PIPELINE II=1
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read_request(s_axis_work_request, req_handle);
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write_completion(m_axis_completion, req_handle, DATA_COLLECTION_ID_PURGE);
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}
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}
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packet_512_t packet;
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{
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#pragma HLS PROTOCOL fixed
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data_in >> packet;
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ap_wait();
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}
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ap_uint<32> data_collection_mode = ACT_REG_MODE(packet.data);
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ap_uint<32> data_collection_id = data_collection_mode(31, 16);
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ap_uint<1> mode_32bit = (data_collection_mode & MODE_32BIT_OUTPUT) ? 1 : 0;
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ap_uint<1> mode_8bit = (data_collection_mode & MODE_8BIT_OUTPUT) ? 1 : 0;
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uint64_t internal_packets_processed = 0;
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packets_processed = internal_packets_processed;
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write_completion(m_axis_completion, HANDLE_START, data_collection_id);
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idle = 0;
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size_t pixel_depth;
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if (mode_32bit)
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pixel_depth = 4;
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else if (mode_8bit)
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pixel_depth = 1;
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else
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pixel_depth = 2;
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axis_completion cmpl;
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s_axis_completion >> cmpl;
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state = 1;
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while (!cmpl.last) {
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ap_uint<1> send_images = 1;
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while (s_axis_work_request.empty() && !in_cancel.read()) {
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#pragma HLS PIPELINE II=1
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ap_wait();
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}
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if (s_axis_work_request.empty()) {
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send_images = 0;
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state = 2;
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} else
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state = 3;
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// Either send_images == 0 (so collection can proceed without writing to host mem)
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// or s_axis_work_request is not empty (so collection can proceed with writing to host mem)
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if (send_images) {
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read_request(s_axis_work_request, req_handle);
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req_host_offset = dma_address_table[req_handle];
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send_images = (req_host_offset != 0);
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}
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packet_512_t packet_out;
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packet_out.strb = UINT64_MAX;
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packet_out.keep = UINT64_MAX;
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packet_out.dest = 0;
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packet_out.user = 0;
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packet_out.id = 0;
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packet_out.last = 0;
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if (send_images) {
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setup_datamover(datamover_out_cmd, req_host_offset, RAW_MODULE_SIZE * pixel_depth);
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setup_datamover(datamover_out_cmd, req_host_offset + offsetof(DeviceOutput, spot_finding_result),
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(RAW_MODULE_SIZE / 8 + 64));
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setup_datamover(datamover_out_cmd, req_host_offset + offsetof(DeviceOutput, integration_result),
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(FPGA_INTEGRATION_BIN_COUNT / 8) * 64);
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setup_datamover(datamover_out_cmd, req_host_offset + offsetof(DeviceOutput, adu_histogram),
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ADU_HISTO_BIN_COUNT / 16 * 64);
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setup_datamover(datamover_out_cmd, req_host_offset + offsetof(DeviceOutput, roi_counts),
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FPGA_ROI_COUNT * 64);
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setup_datamover(datamover_out_cmd, req_host_offset + offsetof(DeviceOutput, module_statistics),
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3 * 64);
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}
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for (int i = 0; i < RAW_MODULE_SIZE * pixel_depth / 64; i++) {
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#pragma HLS PIPELINE II=1
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data_in >> packet;
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packet_out.data = packet.data;
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if (i == RAW_MODULE_SIZE * pixel_depth / 64 - 1)
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packet_out.last = 1;
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else
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packet_out.last = 0;
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if (send_images)
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host_memory_out << packet_out;
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}
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packet_out.last = 0;
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// 256 transfers x 512-bit
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for (int i = 0; i < RAW_MODULE_SIZE / (8 * 64) + 1; i++) {
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#pragma HLS PIPELINE II=1
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spot_finder_in >> packet_out.data;
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packet_out.last = (i == RAW_MODULE_SIZE / (8 * 64));
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if (send_images)
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host_memory_out << packet_out;
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}
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// 128 transfers x 512-bit
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for (int i = 0; i < FPGA_INTEGRATION_BIN_COUNT / 8; i++) {
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#pragma HLS PIPELINE II=1
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integration_in >> packet_out.data;
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packet_out.last = (i == FPGA_INTEGRATION_BIN_COUNT / 8 - 1);
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if (send_images)
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host_memory_out << packet_out;
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}
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// 128 transfers x 512-bit
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for (int i = 0; i < ADU_HISTO_BIN_COUNT / 16; i++) {
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#pragma HLS PIPELINE II=1
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ap_uint<512> tmp;
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adu_histo_in >> packet_out.data;
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packet_out.last = (i == ADU_HISTO_BIN_COUNT / 16 - 1);
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if (send_images)
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host_memory_out << packet_out;
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}
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// 8 transfers x 512-bit
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for (int i = 0; i < FPGA_ROI_COUNT; i++) {
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#pragma HLS PIPELINE II=1
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ap_uint<512> tmp;
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roi_count_in >> packet_out.data;
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packet_out.last = (i == FPGA_ROI_COUNT - 1);
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if (send_images)
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host_memory_out << packet_out;
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}
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if (send_images)
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state = 5;
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else
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state = 4;
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ap_uint<PIXEL_COUNT_WIDTH> pixel_count_p;
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pixel_calc_in >> pixel_count_p;
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ap_uint<1024> tmp = fill_module_info(cmpl, pixel_count_p);
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if (send_images) {
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packet_out.data = tmp(511,0);
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packet_out.last = 0;
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host_memory_out << packet_out;
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packet_out.data = tmp(1023,512);
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packet_out.last = 0;
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host_memory_out << packet_out;
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}
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packet_out.data = cmpl.packet_mask;
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packet_out.last = 1;
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if (send_images)
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host_memory_out << packet_out;
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if (send_images) {
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if (req_handle_send != HANDLE_START)
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write_completion(m_axis_completion, req_handle_send, data_collection_id);
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req_handle_send = req_handle;
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internal_packets_processed += cmpl.packet_count;
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packets_processed = internal_packets_processed;
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}
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state = 6;
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s_axis_completion >> cmpl;
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state = 7;
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}
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data_in >> packet;
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#ifdef JFJOCH_HLS_NOSYNTH
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while (!host_memory_out.empty())
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std::this_thread::sleep_for(std::chrono::milliseconds(1));
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#else
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{
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// wait for 5 ms (ensure that PCIe buffer is clean)
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#pragma HLS PROTOCOL
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for (int i = 0; i < 5 * 200 * 1000; i++)
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ap_wait();
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}
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#endif
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if (req_handle_send != HANDLE_START)
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write_completion(m_axis_completion, req_handle_send, data_collection_id);
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write_completion(m_axis_completion, HANDLE_END, data_collection_id);
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idle = 1;
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}
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