leonarski_fandClaude Opus 5
1239c49731
Setting a bandwidth flipped three unrelated switches at once: it changed the profile's radial capture term, it moved the width measurement from the signal disk to the whole fit grid, and it silently overrode the background clip and trim, so --background-clip under --bandwidth was ignored - the two runs were bit-identical. The width measurement was the damaging one. The fit grid is an azimuthally averaged stack, so its second moment is sigma_r^2 + sigma_t^2 and the radial smear of a bandwidth leaked into the tangential model - a tangential width of 3.04 px against a 1.06 px truth, inflating the effective background pixel count where the weak signal is. The result was a step rather than a slope: on genuinely monochromatic data, declaring a 0.2% bandwidth cost ISa 28.4 -> 22.2. Measure the two widths separately, accumulated in each spot's own radial/tangential frame over the signal disk, from the signed profile cells - away from the peak a learned cell is background noise centred on zero, so the signed sum is unbiased, while clamping it at zero turns that noise into a pedestal the r^2 weight reads as width. The radial term is then the measured excess or the analytic floor, whichever is larger. With the two widths separated there is nothing left for the broadband switch to select, so it is gone - which is the proof the three were independent. The background clip and trim now come from the settings in every case; the tuned 3-sigma broadband default moves to the rugnux front end, which is the only place that knows whether the user gave a value. Monochromatic data: declaring a 0.2% bandwidth now costs ISa 28.4 -> 27.9 rather than 22.2, and forcing the old 3-sigma clip in the new build reproduces the good result, so none of the step came from the clip. On large-bandwidth data CC1/2 improves in 8 of 10 shells. Across 12 monochromatic crystals the space groups are unchanged and CC1/2 moves by at most 0.2 points. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
66 lines
3.4 KiB
C++
66 lines
3.4 KiB
C++
// SPDX-FileCopyrightText: 2026 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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// SPDX-License-Identifier: GPL-3.0-only
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#pragma once
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#include <cstdint>
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#include <memory>
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#include <vector>
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#include "BraggIntegrationEngine.h"
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#include "../indexing/CUDAMemHelpers.h"
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// CUDA engine: reproduces BraggIntegrationEngineCPU up to floating-point precision. Each stage is a
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// kernel with one CUDA block per reflection cooperating over the small window via shared-memory
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// reductions (the natural mapping for thousands of independent, tiny per-spot integrations).
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//
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// Pipeline (profile modes): reset -> mark_mask -> boxsum -> learn_profile -> build_profiles -> fit
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// (the resolution shell is computed inline, so there is no separate shell pass). BoxSum mode stops
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// after boxsum (that pass is the BraggIntegrate2D box integrator and the seed of the profile fit).
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// The preprocessed image already lives on the device (ImagePreprocessorBufferGPU::getGPUBuffer());
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// only the per-frame predicted centres are uploaded.
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class BraggIntegrationEngineGPU : public BraggIntegrationEngine {
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std::shared_ptr<CudaStream> stream;
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int threads;
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size_t fit_shared_bytes;
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size_t capacity = 0; // per-reflection device/host arrays hold at least this many reflections
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// --- per-reflection device arrays (grown by EnsureCapacity) ---
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CudaDevicePtr<float> d_px_x, d_px_y, d_d;
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CudaDevicePtr<int> d_cx, d_cy;
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CudaDevicePtr<float> d_I, d_sigma, d_bkg, d_bkg_var, d_var_bkg, d_obs_x, d_obs_y;
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CudaDevicePtr<float> d_isum; // box-sum raw sum, for the radial correction
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CudaDevicePtr<int> d_ninner, d_rbin;
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CudaDevicePtr<uint8_t> d_ok, d_strong, d_has_obs;
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// --- radial background curvature correction (see BraggIntegrationEngine) ---
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int n_rad = 0; // radial bins, 0 when the correction is off
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CudaDevicePtr<float> d_rad_sum, d_k_diff;
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CudaDevicePtr<int> d_rad_cnt;
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// --- fixed-size device arrays ---
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// The learning/fit math is single precision: FP64 is heavily throttled on consumer GPUs and the
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// extraction is Poisson-noise limited, so float reproduces the double CPU path to ~1e-4.
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CudaDevicePtr<uint8_t> d_mask; // per-pixel r2-disk reflection mask
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CudaDevicePtr<float> d_shell_grid, d_global_grid; // learned profile accumulators (N_SHELL*GG, GG)
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CudaDevicePtr<float> d_shell_P, d_global_P; // normalised profiles (empirical mode)
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CudaDevicePtr<float> d_mom; // learned 2nd moments, 3 per shell + global
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CudaDevicePtr<float> d_sigma2_r, d_sigma2_t; // radial/tangential widths, N_SHELL + global
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CudaDevicePtr<int> d_shell_n, d_global_n;
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CudaDevicePtr<unsigned long long> d_invd2; // [min,max] inv-d^2 as monotonic bit patterns
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// --- host staging (copied back once per frame) ---
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std::vector<float> h_px_x, h_px_y, h_d;
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std::vector<float> h_I, h_sigma, h_bkg, h_var_bkg, h_obs_x, h_obs_y;
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std::vector<uint8_t> h_ok, h_has_obs;
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void EnsureCapacity(size_t n);
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public:
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BraggIntegrationEngineGPU(const DiffractionExperiment &experiment, std::shared_ptr<CudaStream> stream);
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std::vector<Reflection> Run(const ImagePreprocessorBuffer &image,
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const std::vector<Reflection> &predicted, size_t npredicted,
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int64_t image_number) override;
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};
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