121 lines
3.7 KiB
C
121 lines
3.7 KiB
C
// Copyright (2019-2022) Paul Scherrer Institute
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// SPDX-License-Identifier: GPL-3.0-or-later
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#ifndef DEFINITIONS_H
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#define DEFINITIONS_H
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#define WVL_1A_IN_KEV 12.39854f
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#define DELAY_FRAMES_STOP_AND_QUIT 5
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#define RAW_MODULE_LINES (512L)
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#define RAW_MODULE_COLS (1024L)
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#define RAW_MODULE_SIZE (RAW_MODULE_LINES * RAW_MODULE_COLS)
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#define CONVERTED_MODULE_LINES (514L)
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#define CONVERTED_MODULE_COLS (1030L)
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#define CONVERTED_MODULE_SIZE (CONVERTED_MODULE_LINES * CONVERTED_MODULE_COLS)
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#define JUNGFRAU_PACKET_SIZE_BYTES (8192)
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#define FPGA_BUFFER_LOCATION_SIZE (RAW_MODULE_SIZE * sizeof(short))
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#define MIN_COUNT_TIME_IN_US 10
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#define MIN_FRAME_TIME_HALF_SPEED_IN_US 1000
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#define MIN_FRAME_TIME_FULL_SPEED_IN_US 470
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#define MAX_FRAME_TIME 2000
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#define MAX_SUMMATION 1000
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#define READOUT_TIME_IN_US 20
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#define GRPC_MAX_MESSAGE_SIZE (1000L*1000L*1000L)
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#define MIN_ENERGY 0.1
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#define MAX_ENERGY 25.0
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#define PEDESTAL_WINDOW_SIZE 128
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#define PEDESTAL_WRONG 16384
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#define FRAME_TIME_PEDE_G1G2_IN_US (10*1000)
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#define SENSOR_THICKNESS_IN_UM 320.0
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#define PIXEL_SIZE_IN_UM 75.0
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#define PIXEL_SIZE_IN_MM (PIXEL_SIZE_IN_UM/1000.0)
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#define SENSOR_MATERIAL "Si"
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#define GAIN_G0_MULTIPLIER 32
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#define GAIN_G1_MULTIPLIER (-1)
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#define GAIN_G2_MULTIPLIER (-1)
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#define DEFAULT_G0_FACTOR (41.0)
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#define DEFAULT_G1_FACTOR (-1.439)
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#define DEFAULT_G2_FACTOR (-0.1145)
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// For FPGA
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/* This number is unique and is declared in ~snap/ActionTypes.md */
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#define ACTION_TYPE 0x52324158
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#define RELEASE_LEVEL 0x0033
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#define MODE_CONV 0x0001L
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#define MODE_INTERNAL_PACKET_GEN 0x0002L
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#define TASK_NO_DATA_STREAM UINT16_MAX
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#define PIXEL_OUT_SATURATION (INT16_MAX)
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#define PIXEL_OUT_LOST (INT16_MIN)
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#define PIXEL_OUT_0xFFFF (INT16_MIN)
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#define PIXEL_OUT_G1_SATURATION (INT16_MIN)
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#define PIXEL_OUT_GAINBIT_2 (INT16_MIN)
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#define LOAD_CALIBRATION_BRAM_SIZE 1024
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// FPGA register map
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#define ADDR_CTRL_REGISTER 0x0000
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#define ADDR_GIT_SHA1 0x000C
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#define ADDR_ACTION_TYPE 0x0010
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#define ADDR_RELEASE_LEVEL 0x0014
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#define ADDR_HBM_TEMP 0x0018
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#define ADDR_HBM_MAX_TEMP 0x001C
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#define ADDR_MAX_MODULES_FPGA 0x0020
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#define ADDR_MODS_INT_PKT_GEN 0x0024
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#define ADDR_STALLS_HOST_LO 0x0028
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#define ADDR_STALLS_HOST_HI 0x002C
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#define ADDR_STALLS_HBM_LO 0x0030
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#define ADDR_STALLS_HBM_HI 0x0034
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#define ADDR_FIFO_STATUS 0x0038
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#define ADDR_PACKETS_PROC_LO 0x0040
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#define ADDR_PACKETS_PROC_HI 0x0044
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#define ADDR_PACKETS_ETH_LO 0x0048
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#define ADDR_PACKETS_ETH_HI 0x004C
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#define ADDR_PACKETS_ICMP_LO 0x0050
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#define ADDR_PACKETS_ICMP_HI 0x0054
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#define ADDR_PACKETS_UDP_LO 0x0058
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#define ADDR_PACKETS_UDP_HI 0x005C
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#define ADDR_PACKETS_SLS_LO 0x0060
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#define ADDR_PACKETS_SLS_HI 0x0064
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#define ADDR_PACKETS_ERR_LEN 0x0068
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#define ADDR_PACKETS_ERR_ETH 0x006C
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#define ADDR_MAC_ADDR_LO 0x0080
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#define ADDR_MAC_ADDR_HI 0x0084
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#define ADDR_IPV4_ADDR 0x0088
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#define ADDR_NMODULES 0x008C
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#define ADDR_DATA_COL_MODE 0x0090
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#define ADDR_ONE_OVER_ENERGY 0x0094
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#define ADDR_NFRAMES 0x0098
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#define ADDR_NSTORAGE_CELLS 0x009C
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#define ADDR_MAILBOX_WRDATA 0x00
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#define ADDR_MAILBOX_RDDATA 0x08
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#define ADDR_MAILBOX_STATUS 0x10
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#define ADDR_MAILBOX_SIT 0x18
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#define ADDR_MAILBOX_RIT 0x1C
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#define MAILBOX_EMPTY (1 << 0)
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#define MAILBOX_FULL (1 << 1)
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#define MAILBOX_STA (1 << 2)
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#define MAILBOX_RTA (1 << 3)
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#define CTRL_REGISTER_IDLE (1<<1u)
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#endif //DEFINITIONS_H
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