leonarski_fandClaude Opus 4.8
4cda46c6b0
Replace the free functions BraggIntegrate2D/ProfileIntegrate2D with the BraggIntegrationEngine (CPU/GPU) as the live integrator. - IndexAndRefine no longer holds the integrator: ProcessImage takes a per-worker BraggIntegrateFn callback (ProcessImage is called concurrently by the shared IndexAndRefine, so the stateful engine must not be a member). - WithoutFPGA/jfjoch_process: owns a GPU engine when a GPU is present, else CPU, and passes the GPU-resident preprocessed buffer so integration runs on-device. - AfterFPGA: forces CPU and integrates straight off the assembled CompressedImage via a templated per-pixel sampler - only the reflection-disk pixels are read, no whole-image copy (the FPGA host runs up to 36 GB/s). Sampler maps type min/max to INT32_MIN/INT32_MAX on read; special/saturation only, no +/-1 band. - Remove BraggIntegrate2D/ProfileIntegrate2D and their test; keep IntegratorMode. Prediction: buffer up to 20000 candidates but return the 10000 closest to the Ewald sphere (deterministic partial_sort on |dist_ewald|, hkl tiebreak) instead of the GPU atomic-fill order. Serialized output stays <=10000, so the frame transport headroom and its CBOR guard are unchanged. integration_model exposed via OpenAPI (bragg_integration_settings schema, /config/bragg_integration PUT/GET, added to jfjoch_settings and jfjoch_statistics) and the frontend (BraggIntegrationSettings dropdown). Regenerated C++/TS clients and redoc. Validated old-vs-new on all 18 /data/rotation_test crystals: indexing rate and space group bit-identical; ISa/CC identical on 16/18 (one improved, EcwtAL500 ISa 0.0->6.7); new CompressedImage-vs-buffer and GPU-vs-CPU parity tests pass. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
60 lines
2.4 KiB
C++
60 lines
2.4 KiB
C++
// SPDX-FileCopyrightText: 2024 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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// SPDX-License-Identifier: GPL-3.0-only
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#pragma once
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#include "../common/DiffractionExperiment.h"
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#include "bragg_prediction/BraggPrediction.h"
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#include "bragg_integration/BraggIntegrationEngineCPU.h"
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#include "indexing/IndexerThreadPool.h"
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#include "spot_finding/StrongPixelSet.h"
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#include "azint/AzIntEngineCPU.h"
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#include "IndexAndRefine.h"
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class MXAnalysisAfterFPGA {
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mutable std::mutex read_from_cpu_mutex;
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const DiffractionExperiment &experiment;
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const AzimuthalIntegrationMapping &integration;
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IndexAndRefine &indexer;
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std::unique_ptr<BraggPrediction> prediction;
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std::unique_ptr<AzIntEngineCPU> cpu_azint;
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// The FPGA host has no usable GPU bandwidth for integration, so Bragg integration here is always on
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// the CPU, reading the assembled detector image straight (only the reflection disks - no copy).
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std::unique_ptr<BraggIntegrationEngineCPU> bragg_engine;
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bool find_spots = false;
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std::vector<DiffractionSpot> spots;
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constexpr static const float spot_distance_threshold_pxl = 2.0f;
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std::vector<float> arr_mean;
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std::vector<float> arr_sttdev;
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std::vector<uint32_t> arr_valid_count;
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std::vector<uint32_t> arr_strong_pixel;
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enum class State {Idle, Disabled, Enabled} state = State::Idle;
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std::chrono::duration<double, std::micro> spot_finding_time_total{0.0};
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bool spot_finding_timing_active = false;
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public:
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MXAnalysisAfterFPGA(const DiffractionExperiment& experiment,
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const AzimuthalIntegrationMapping &integration,
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IndexAndRefine &indexer);
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void ReadFromFPGA(const DeviceOutput* output,
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const SpotFindingSettings& settings,
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size_t module_number);
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void ReadFromCPU(DeviceOutput *output,
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const SpotFindingSettings &settings,
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size_t module_number);
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// Computes the azimuthal integration profile on the CPU from the assembled image.
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// Only active when the settings force the CPU backend; otherwise a no-op (the FPGA
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// fills the profile). image points to the uncompressed image of GetByteDepthImage() pixels.
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void RunAzimuthalIntegration(const void *image, AzimuthalIntegrationProfile &profile);
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void Process(DataMessage &message, const SpotFindingSettings& settings);
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};
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