Two changes to the stills integration background, both stills-only (rotation keeps its path bit for bit): 1. The r2..r3 background ring's outer radius is measured per run. The pre-scan lays apertures on a grid over its frames, away from every found spot, and for each candidate r3 (r2+2 .. 14) takes the mean square difference between the r1 disk mean and the clipped ring mean. With nothing in the aperture that is exactly the background error the ring makes (noise + bias); the run keeps the minimum. On a photon-counting pixel detector the noise wins and the shipped r3=14 is kept; on a binned CCD the background structure wins and the narrowest ring is taken. r1 stays 6: a smaller disk (4,6,14) costs 0.0013 dimple R_free on a JUNGFRAU set, so it does not pass the photon-counting gate. --adaptive-integration-radius now defaults on for stills too (=off restores the fixed 6/8/14). The pre-scan bandwidth estimate is not applied to stills. 2. The radial background-curvature correction on stills takes its curve from the adaptive spot finder's peak-excluded per-ring background (whole frame) instead of the predicted reflections' own ring pixels, and auto applies it to every stills image (no ice-score gate: a solvent/carrier hump curves the background as much as ice). New engine call RadialBackgroundFromRings; CPU, GPU and Metal read the handed-over curve. The GPU box sum now sizes the radial bin index separately from accumulating, so a handed-over curve is read at the right radius. Measured (dimple R_free, deposited free set, battery arguments, all frames unless noted): pal86 (Rayonix 4x4, 156 um): 0.354 -> 0.218 (ring 10; at 4,6,10 0.213) lcls222 (Rayonix 4x4, 177 um): 0.205 -> 0.196 (ring 10) sacla236 (MPCCD): 0.2588 -> 0.2558 (ring 11) alvra213_int16 (JUNGFRAU): 0.1986 -> 0.1986 (ring 14, unchanged) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_015CeEGgpKdfkCTJb3YNMJcu
103 lines
6.0 KiB
C++
103 lines
6.0 KiB
C++
// SPDX-FileCopyrightText: 2026 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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// SPDX-License-Identifier: GPL-3.0-only
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#pragma once
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#include <cstdint>
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#include <memory>
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#include <vector>
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#include "BraggIntegrationEngine.h"
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#include "../indexing/CUDAMemHelpers.h"
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#include "../../common/PixelMask.h"
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// CUDA engine: reproduces BraggIntegrationEngineCPU up to floating-point precision. Each stage is a
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// kernel with one CUDA block per reflection cooperating over the small window via shared-memory
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// reductions (the natural mapping for thousands of independent, tiny per-spot integrations).
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//
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// Pipeline (profile modes): reset -> mark_mask -> boxsum -> learn_profile -> build_profiles -> fit
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// (the resolution shell is computed inline, so there is no separate shell pass). BoxSum mode stops
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// after boxsum (that pass is the BraggIntegrate2D box integrator and the seed of the profile fit).
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// The preprocessed image already lives on the device (ImagePreprocessorBufferGPU::getGPUBuffer());
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// only the per-frame predicted centres are uploaded.
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class BraggIntegrationEngineGPU : public BraggIntegrationEngine {
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std::shared_ptr<CudaStream> stream;
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int threads;
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size_t fit_shared_bytes;
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int rad_w = 0; // radial-background window of boxsum, in bins of one pixel
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size_t boxsum_shared_bytes = 0;
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size_t capacity = 0; // per-reflection device/host arrays hold at least this many reflections
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// Whether d_mask / d_owner may still carry the marks of an earlier image. Run() clears what it
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// marked before it returns when that is cheaper than clearing the frame, and this is then false in
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// the steady state; it is true before the first call, after one that threw part-way through, and
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// whenever the marks covered enough of the frame that clearing all of it was the cheaper choice.
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bool dirty = true;
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size_t mask_box_px = 0; // pixels one reflection's mark_mask box covers, at the widest aperture
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// --- per-reflection device arrays (grown by EnsureCapacity) ---
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CudaDevicePtr<float> d_px_x, d_px_y, d_d;
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CudaDevicePtr<BraggPanel> d_panel; // the panel of each reflection (BraggStencil.h)
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CudaDevicePtr<uint8_t> d_mark; // the reflection marks its signal region in d_mask
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CudaDevicePtr<int> d_cx, d_cy;
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CudaDevicePtr<float> d_I, d_sigma, d_bkg, d_bkg_var, d_var_bkg, d_obs_x, d_obs_y;
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CudaDevicePtr<float> d_isum; // box-sum raw sum, for the radial correction
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CudaDevicePtr<int> d_ninner, d_rbin, d_kbin;
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// The run's pixel mask, one byte per pixel (PixelMask::GetBinaryMask), shared with the
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// preprocessor's copy. See BraggIntegrationEngineCPU::static_mask.
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std::shared_ptr<CudaDevicePtr<uint8_t>> d_static_mask;
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CudaDevicePtr<uint8_t> d_ok, d_strong, d_has_obs, d_overloaded;
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// --- radial background curvature correction (see BraggIntegrationEngine) ---
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int n_rad = 0; // radial bins, 0 when the correction is off
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CudaDevicePtr<unsigned long long> d_rad_sum; // integer pixel sums, see boxsum
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CudaDevicePtr<float> d_k_diff;
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CudaDevicePtr<int> d_rad_cnt;
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CudaDevicePtr<float> d_rad_curve; // the curve handed over (RadialBackgroundFromRings)
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// --- fixed-size device arrays ---
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// The learning/fit math is single precision: FP64 is heavily throttled on consumer GPUs and the
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// extraction is Poisson-noise limited, so float reproduces the double CPU path to ~1e-4.
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CudaDevicePtr<uint8_t> d_mask; // per-pixel inner-stencil reflection mask
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// Per-pixel (distance, reflection) key naming the nearest predicted centre; allocated only when
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// an overlap treatment is on, so the default path costs no extra device memory.
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CudaDevicePtr<uint32_t> d_owner;
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// Fixed-point (see PROFILE_FIXED): a float atomicAdd here made the profile depend on the order
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// the blocks arrived in, and with it every intensity fitted through it.
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CudaDevicePtr<unsigned long long> d_shell_grid, d_global_grid; // learned profile accumulators (N_SHELL*GG, GG)
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CudaDevicePtr<float> d_shell_P, d_global_P; // normalised profiles (empirical mode)
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CudaDevicePtr<unsigned long long> d_mom; // learned 2nd moments, 3 per shell + global
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CudaDevicePtr<float> d_sigma2_r, d_sigma2_t; // radial/tangential widths, N_SHELL + global
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CudaDevicePtr<int> d_shell_n, d_global_n;
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CudaDevicePtr<unsigned long long> d_invd2; // [min,max] inv-d^2 as monotonic bit patterns
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// BraggIntegrationCounts, accumulated on the device so an image costs no transfer; brought back
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// only when Counts() is asked for.
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CudaDevicePtr<unsigned long long> d_counts;
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// --- host staging (copied back once per frame) ---
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// Pinned, like every other engine's staging: a copy out of pageable memory does not return until the
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// driver has staged it through a bounce buffer, so eight of them in a row are eight serialised
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// round-trips rather than eight queued transfers.
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CudaHostPtr<float> h_px_x, h_px_y, h_d;
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CudaHostPtr<BraggPanel> h_panel;
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CudaHostPtr<uint8_t> h_mark;
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CudaHostPtr<float> h_I, h_sigma, h_bkg, h_var_bkg, h_obs_x, h_obs_y;
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CudaHostPtr<uint8_t> h_ok, h_has_obs, h_overloaded;
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void EnsureCapacity(size_t n);
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public:
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BraggIntegrationEngineGPU(const DiffractionExperiment &experiment, std::shared_ptr<CudaStream> stream,
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const PixelMask &mask);
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// Waits for the stream: its pooled buffers are freed next (see CudaDevicePtr).
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~BraggIntegrationEngineGPU() override { if (stream) cudaStreamSynchronize(*stream); }
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std::vector<Reflection> Run(const ImagePreprocessorBuffer &image,
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const std::vector<Reflection> &predicted, size_t npredicted,
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int64_t image_number) override;
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// Brings the two device counters back before answering. Synchronises the stream, so ask once a
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// pass rather than once an image.
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[[nodiscard]] BraggIntegrationCounts Counts() const override;
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};
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