94 lines
3.7 KiB
C++
94 lines
3.7 KiB
C++
// SPDX-FileCopyrightText: 2024 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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#include "hls_jfjoch.h"
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void frame_summation_reorder_compl(STREAM_768 &data_in,
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STREAM_768 &data_out,
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hls::stream<axis_completion > &s_axis_completion,
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hls::stream<axis_completion > &m_axis_completion) {
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#pragma HLS INTERFACE ap_ctrl_none port=return
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#pragma HLS INTERFACE axis register both port=data_in
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#pragma HLS INTERFACE axis register both port=data_out
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#pragma HLS INTERFACE axis register both port=s_axis_completion
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#pragma HLS INTERFACE axis register both port=m_axis_completion
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axis_completion completions[MAX_FPGA_SUMMATION * MAX_MODULES_FPGA];
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ap_uint<MAX_FPGA_SUMMATION> completion_mask[MAX_MODULES_FPGA];
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ap_uint<9> completion_count[MAX_MODULES_FPGA]; // must represent 256
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ap_uint<64> curr_frame_number_prefix[MAX_MODULES_FPGA];
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for (int i = 0; i < MAX_MODULES_FPGA; i++) {
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completion_mask[i] = 0;
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completion_count[i] = 0;
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curr_frame_number_prefix[i] = 0;
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}
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packet_768_t packet_in;
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{
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#pragma HLS PROTOCOL fixed
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data_in >> packet_in;
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ap_wait();
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data_out << packet_in;
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ap_wait();
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}
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ap_uint<8> sum = ACT_REG_NSUMMATION(packet_in.data); // 0..255
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axis_completion c;
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s_axis_completion >> c;
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if (sum == 0) {
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while (!c.last) {
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m_axis_completion << c;
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ap_uint<7> module = c.module;
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if (c.frame_number <= curr_frame_number_prefix[module])
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c.ignore = 1;
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curr_frame_number_prefix[module] = c.frame_number;
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s_axis_completion >> c;
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}
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} else {
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while (!c.last) {
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ap_uint<64> frame_number_prefix = c.frame_number / (sum + 1);
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ap_uint<8> frame_number_loc = c.frame_number % (sum + 1); // 0..255
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ap_uint<7> module = c.module;
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if (frame_number_prefix > curr_frame_number_prefix[module]) {
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for (int i = 0; i <= sum; i++) {
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#pragma HLS PIPELINE II=1
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axis_completion cmpl = completions[module * MAX_FPGA_SUMMATION + i];
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if (completion_count[module] != sum + 1)
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cmpl.ignore = 1;
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if (completion_mask[module][i])
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m_axis_completion << cmpl;
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}
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completions[module * MAX_FPGA_SUMMATION + frame_number_loc] = c;
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completion_mask[module] = 1 << frame_number_loc;
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completion_count[module] = 1;
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curr_frame_number_prefix[module] = frame_number_prefix;
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} else if (frame_number_prefix == curr_frame_number_prefix[module]) {
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completions[module * MAX_FPGA_SUMMATION + frame_number_loc] = c;
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completion_mask[module][frame_number_loc] = 1;
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completion_count[module] += 1;
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curr_frame_number_prefix[module] = frame_number_prefix;
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} else {
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c.ignore = 1;
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m_axis_completion << c;
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}
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s_axis_completion >> c;
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}
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for (int module = 0; module < MAX_MODULES_FPGA; module++) {
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for (int i = 0; i <= sum; i++) {
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#pragma HLS PIPELINE II=1
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axis_completion cmpl = completions[module * MAX_FPGA_SUMMATION + i];
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if (completion_count[module] != sum + 1)
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cmpl.ignore = 1;
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if (completion_mask[module][i])
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m_axis_completion << cmpl;
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}
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}
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}
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m_axis_completion << c;
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data_in >> packet_in;
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data_out << packet_in;
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}
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