106 lines
5.5 KiB
Tcl
106 lines
5.5 KiB
Tcl
# SPDX-FileCopyrightText: 2024 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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# Hierarchical cell: packet_proc
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proc create_hier_cell_packet_proc { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_packet_proc() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create cell and set as current instance
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set hier_obj [create_bd_cell -type hier $nameHier]
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current_bd_instance $hier_obj
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# Create interface pins
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 eth_in
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 eth_out
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_cfg
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 udp_out
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# Create pins
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create_bd_pin -dir I aresetn
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create_bd_pin -dir I eth_clk
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create_bd_pin -dir I eth_reset
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create_bd_pin -dir I refclk200
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create_bd_pin -dir I stat_rx_status
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# Create instance: axis_clock_converter_rx, and set properties
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set axis_clock_converter_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_rx ]
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# Create instance: axis_clock_converter_tx, and set properties
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set axis_clock_converter_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_tx ]
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# Create instance: axis_dwidth_converter_rx, and set properties
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set axis_dwidth_converter_rx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_converter_rx ]
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set_property -dict [ list \
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CONFIG.M_TDATA_NUM_BYTES {64} \
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] $axis_dwidth_converter_rx
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# Create instance: axis_dwidth_converter_tx, and set properties
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set axis_dwidth_converter_tx [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 axis_dwidth_converter_tx ]
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set_property -dict [ list \
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CONFIG.M_TDATA_NUM_BYTES {8} \
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] $axis_dwidth_converter_tx
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# Create instance: network_stack
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create_hier_cell_network_stack $hier_obj network_stack
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# Create instance: util_vector_logic_0, and set properties
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set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
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set_property -dict [ list \
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CONFIG.C_OPERATION {not} \
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CONFIG.C_SIZE {1} \
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CONFIG.LOGO_FILE {data/sym_notgate.png} \
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] $util_vector_logic_0
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set_property -dict [list CONFIG.DIRECT {1}] [get_bd_cells network_stack/network_config_0]
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# Create interface connections
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connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins udp_out] [get_bd_intf_pins network_stack/udp_out]
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connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins eth_out] [get_bd_intf_pins axis_clock_converter_tx/M_AXIS]
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connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins eth_in] [get_bd_intf_pins axis_clock_converter_rx/S_AXIS]
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connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins s_axi_cfg] [get_bd_intf_pins network_stack/s_axi_cfg]
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connect_bd_intf_net -intf_net axis_clock_converter_rx_M_AXIS [get_bd_intf_pins axis_clock_converter_rx/M_AXIS] [get_bd_intf_pins axis_dwidth_converter_rx/S_AXIS]
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connect_bd_intf_net -intf_net axis_dwidth_converter_tx_M_AXIS [get_bd_intf_pins axis_clock_converter_tx/S_AXIS] [get_bd_intf_pins axis_dwidth_converter_tx/M_AXIS]
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connect_bd_intf_net -intf_net eth_in_1 [get_bd_intf_pins axis_dwidth_converter_rx/M_AXIS] [get_bd_intf_pins network_stack/eth_in]
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connect_bd_intf_net -intf_net network_stack_eth_out [get_bd_intf_pins axis_dwidth_converter_tx/S_AXIS] [get_bd_intf_pins network_stack/eth_out]
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# Create port connections
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connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins axis_clock_converter_rx/m_axis_aresetn] [get_bd_pins axis_clock_converter_tx/s_axis_aresetn] [get_bd_pins axis_dwidth_converter_rx/aresetn] [get_bd_pins axis_dwidth_converter_tx/aresetn] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins network_stack/resetn]
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connect_bd_net -net eth_clk_1 [get_bd_pins eth_clk] [get_bd_pins axis_clock_converter_rx/s_axis_aclk] [get_bd_pins axis_clock_converter_tx/m_axis_aclk]
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connect_bd_net -net eth_reset_1 [get_bd_pins eth_reset] [get_bd_pins util_vector_logic_0/Op1]
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connect_bd_net -net eth_resetn_1 [get_bd_pins axis_clock_converter_rx/s_axis_aresetn] [get_bd_pins axis_clock_converter_tx/m_axis_aresetn] [get_bd_pins util_vector_logic_0/Res]
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connect_bd_net -net refclk200_1 [get_bd_pins refclk200] [get_bd_pins axis_clock_converter_rx/m_axis_aclk] [get_bd_pins axis_clock_converter_tx/s_axis_aclk] [get_bd_pins axis_dwidth_converter_rx/aclk] [get_bd_pins axis_dwidth_converter_tx/aclk] [get_bd_pins network_stack/axiclk]
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connect_bd_net -net network_stack_stat_rx_status_1 [get_bd_pins stat_rx_status] [get_bd_pins network_stack/stat_rx_status]
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# Restore current instance
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current_bd_instance $oldCurInst
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} |