leonarski_f
d315506633
* Enhancements for EIGER * Writer is more flexible and capable of handling DECTRIS data
264 lines
12 KiB
C++
264 lines
12 KiB
C++
// Copyright (2019-2023) Paul Scherrer Institute
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#include "hls_jfjoch.h"
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#define PEDESTAL_G0_PRECISION 24 // 14-bit + 1-bit (fractional) + 7-bit (for 128 pixel window)
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typedef ap_ufixed<PEDESTAL_G0_PRECISION,14, AP_RND_CONV> pedestal_g0_t;
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typedef ap_uint<PEDESTAL_G0_PRECISION * 32> packed_pedestal_g0_t;
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void pack(packed_pedestal_g0_t& out, pedestal_g0_t in[32]) {
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#pragma HLS INLINE
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for (int i = 0; i < 32; i ++) {
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for (int j = 0; j < PEDESTAL_G0_PRECISION; j ++) out[i * PEDESTAL_G0_PRECISION + j] = in[i][j];
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}
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}
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inline void unpack(packed_pedestal_g0_t in, pedestal_g0_t out[32]) {
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#pragma HLS INLINE
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for (int i = 0; i < 32; i ++) {
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for (int j = 0; j < PEDESTAL_G0_PRECISION; j ++) out[i][j] = in[i * PEDESTAL_G0_PRECISION + j];
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}
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}
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ap_uint<512> pack_and_reduce(const packed_pedestal_g0_t &in) {
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#pragma HLS INLINE
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ap_uint<512> out;
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pedestal_g0_t tmp_full[32];
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unpack(in, tmp_full);
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for (int i = 0; i < 32; i++) {
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ap_uint<16> tmp1 = tmp_full[i] + pedestal_g0_t(0.5); // returns only integer part
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if (tmp_full[i] > 16383)
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tmp1 = 16384;
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for (int j = 0; j < 16; j++)
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out[i*16+j] = tmp1[j];
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}
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return out;
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}
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packed_pedestal_g0_t update_pedestal(ap_uint<512> data_in,
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const packed_pedestal_g0_t packed_pedestal_in,
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ap_uint<1> accumulate, ap_uint<8> mode) {
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#pragma HLS INLINE
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// Load current pedestal
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pedestal_g0_t pedestal[32];
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unpack(packed_pedestal_in, pedestal);
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for (int j = 0; j < 32; j++) {
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ap_uint<2> gain = data_in(16 * j + 15,16 * j + 14);
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ap_uint<14> adu = data_in(16 * j + 13,16 * j);
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// Correct pedestal based on gain
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if ((((gain == 0x0) && ((mode & MODE_PEDESTAL_G0) != 0)) ||
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((gain == 0x1) && ((mode & MODE_PEDESTAL_G1) != 0)) ||
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((gain == 0x3) && ((mode & MODE_PEDESTAL_G2) != 0)))
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&& (pedestal[j] < pedestal_g0_t(16383.25))) {
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if (accumulate)
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pedestal[j] += pedestal_g0_t(adu) / PEDESTAL_WINDOW_SIZE;
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else
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pedestal[j] += ap_fixed<PEDESTAL_G0_PRECISION + 2, 16, AP_RND_CONV>(adu - pedestal[j]) / PEDESTAL_WINDOW_SIZE;
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} else
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pedestal[j] = pedestal_g0_t(16383.5);
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}
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packed_pedestal_g0_t packed_pedestal_out;
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// Save pedestal
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pack(packed_pedestal_out, pedestal);
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return packed_pedestal_out;
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}
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void pedestal(STREAM_512 &data_in, STREAM_512 &data_out,
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hls::stream<axis_completion > &s_axis_completion,
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hls::stream<axis_completion > &m_axis_completion,
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ap_uint<256> *d_hbm_p0,
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ap_uint<256> *d_hbm_p0_w,
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ap_uint<256> *d_hbm_p1,
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ap_uint<256> *d_hbm_p1_w,
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ap_uint<256> *d_hbm_p2,
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ap_uint<256> *d_hbm_p2_w,
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ap_uint<256> *d_hbm_p3,
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ap_uint<256> *d_hbm_p3_w,
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ap_uint<256> *d_hbm_p4,
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ap_uint<256> *d_hbm_p4_w,
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ap_uint<256> *d_hbm_p5,
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ap_uint<256> *d_hbm_p5_w,
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ap_uint<32> hbm_size_bytes) {
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#pragma HLS INTERFACE ap_ctrl_none port=return
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#pragma HLS INTERFACE axis register both port=data_in
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#pragma HLS INTERFACE axis register both port=data_out
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#pragma HLS INTERFACE axis register both port=s_axis_completion
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#pragma HLS INTERFACE axis register both port=m_axis_completion
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#pragma HLS INTERFACE register ap_none port=hbm_size_bytes
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#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \
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max_read_burst_length=16 max_write_burst_length=2 latency=130 num_write_outstanding=2 num_read_outstanding=16
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#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
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max_read_burst_length=16 max_write_burst_length=2 latency=130 num_write_outstanding=2 num_read_outstanding=16
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#pragma HLS INTERFACE m_axi port=d_hbm_p2 bundle=d_hbm_p2 depth=512 offset=off \
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max_read_burst_length=16 max_write_burst_length=2 latency=130 num_write_outstanding=2 num_read_outstanding=16
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#pragma HLS INTERFACE m_axi port=d_hbm_p3 bundle=d_hbm_p3 depth=512 offset=off \
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max_read_burst_length=16 max_write_burst_length=2 latency=130 num_write_outstanding=2 num_read_outstanding=16
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#pragma HLS INTERFACE m_axi port=d_hbm_p4 bundle=d_hbm_p4 depth=512 offset=off \
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max_read_burst_length=16 max_write_burst_length=2 latency=130 num_write_outstanding=2 num_read_outstanding=16
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#pragma HLS INTERFACE m_axi port=d_hbm_p5 bundle=d_hbm_p5 depth=512 offset=off \
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max_read_burst_length=16 max_write_burst_length=2 latency=130 num_write_outstanding=2 num_read_outstanding=16
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#pragma HLS INTERFACE m_axi port=d_hbm_p0_w bundle=d_hbm_p0_w depth=512 offset=off \
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max_read_burst_length=2 max_write_burst_length=16 latency=130 num_write_outstanding=8 num_read_outstanding=2
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#pragma HLS INTERFACE m_axi port=d_hbm_p1_w bundle=d_hbm_p1_w depth=512 offset=off \
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max_read_burst_length=2 max_write_burst_length=16 latency=130 num_write_outstanding=8 num_read_outstanding=2
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#pragma HLS INTERFACE m_axi port=d_hbm_p2_w bundle=d_hbm_p2_w depth=512 offset=off \
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max_read_burst_length=2 max_write_burst_length=16 latency=130 num_write_outstanding=8 num_read_outstanding=2
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#pragma HLS INTERFACE m_axi port=d_hbm_p3_w bundle=d_hbm_p3_w depth=512 offset=off \
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max_read_burst_length=2 max_write_burst_length=16 latency=130 num_write_outstanding=8 num_read_outstanding=2
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#pragma HLS INTERFACE m_axi port=d_hbm_p4_w bundle=d_hbm_p4_w depth=512 offset=off \
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max_read_burst_length=2 max_write_burst_length=16 latency=130 num_write_outstanding=8 num_read_outstanding=2
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#pragma HLS INTERFACE m_axi port=d_hbm_p5_w bundle=d_hbm_p5_w depth=512 offset=off \
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max_read_burst_length=2 max_write_burst_length=16 latency=130 num_write_outstanding=8 num_read_outstanding=2
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uint64_t frame_count[MAX_MODULES_FPGA*16];
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for (int i = 0; i < MAX_MODULES_FPGA*16; i++)
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frame_count[i] = 0;
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packet_512_t packet;
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{
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#pragma HLS PROTOCOL fixed
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data_in >> packet;
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ap_wait();
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data_out << packet;
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ap_wait();
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}
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ap_uint<8> conversion_mode = ACT_REG_MODE(packet.data);
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ap_uint<8> nmodules = ACT_REG_NMODULES(packet.data) + 1;
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ap_uint<5> nstoragecells = ACT_REG_NSTORAGE_CELLS(packet.data);
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ap_uint<1> pedestal_mode = ((conversion_mode & MODE_PEDESTAL_G0) != 0)
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|| ((conversion_mode & MODE_PEDESTAL_G1) != 0)
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|| ((conversion_mode & MODE_PEDESTAL_G2) != 0);
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ap_uint<32> offset_hbm_0 = 24 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_1 = 25 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_2 = 26 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_3 = 27 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_4 = 28 * hbm_size_bytes / 32;
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ap_uint<32> offset_hbm_5 = 29 * hbm_size_bytes / 32;
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if (pedestal_mode) {
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clean_hbm:
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for (int i = 0; i < nmodules * nstoragecells * RAW_MODULE_SIZE * sizeof(uint16_t) / 128; i++) {
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#pragma HLS PIPELINE II=1
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d_hbm_p0_w[offset_hbm_0 + i] = 0;
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d_hbm_p1_w[offset_hbm_1 + i] = 0;
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d_hbm_p2_w[offset_hbm_2 + i] = 0;
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d_hbm_p3_w[offset_hbm_3 + i] = 0;
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d_hbm_p4_w[offset_hbm_4 + i] = 0;
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d_hbm_p5_w[offset_hbm_5 + i] = 0;
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}
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}
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axis_completion cmpl;
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s_axis_completion >> cmpl;
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while (!cmpl.last) {
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m_axis_completion << cmpl;
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if ((cmpl.packet_count == 256) && pedestal_mode) {
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ap_int<5> storage_cell = ((nstoragecells > 1) ? ap_int<5>((cmpl.frame_number % nstoragecells)) : ap_int<5>(0));
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ap_uint<1> accumulate = (frame_count[nmodules * storage_cell + cmpl.module] < PEDESTAL_WINDOW_SIZE);
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frame_count[nmodules * storage_cell + cmpl.module]++;
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size_t offset_local = (storage_cell * nmodules + cmpl.module) * (RAW_MODULE_SIZE * sizeof(uint16_t) / 128);
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process_data:
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for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 128; i++) {
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#pragma HLS PIPELINE II=2
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data_in >> packet;
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data_out << packet;
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packed_pedestal_g0_t packed_pedestal_in_0, packed_pedestal_out_0;
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packed_pedestal_in_0(255, 0) = d_hbm_p0[offset_hbm_0 + offset_local + i];
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packed_pedestal_in_0(511, 256) = d_hbm_p1[offset_hbm_1 + offset_local + i];
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packed_pedestal_in_0(767, 512) = d_hbm_p2[offset_hbm_2 + offset_local + i];
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packed_pedestal_out_0 = update_pedestal(packet.data, packed_pedestal_in_0, accumulate, conversion_mode);
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d_hbm_p0_w[offset_hbm_0 + offset_local + i] = packed_pedestal_out_0(255, 0);
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d_hbm_p1_w[offset_hbm_1 + offset_local + i] = packed_pedestal_out_0(511, 256);
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d_hbm_p2_w[offset_hbm_2 + offset_local + i] = packed_pedestal_out_0(767, 512);
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data_in >> packet;
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data_out << packet;
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packed_pedestal_in_0(255, 0) = d_hbm_p3[offset_hbm_3 + offset_local + i];
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packed_pedestal_in_0(511, 256) = d_hbm_p4[offset_hbm_4 + offset_local + i];
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packed_pedestal_in_0(767, 512) = d_hbm_p5[offset_hbm_5 + offset_local + i];
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packed_pedestal_out_0 = update_pedestal(packet.data, packed_pedestal_in_0, accumulate, conversion_mode);
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d_hbm_p3_w[offset_hbm_3 + offset_local + i] = packed_pedestal_out_0(255, 0);
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d_hbm_p4_w[offset_hbm_4 + offset_local + i] = packed_pedestal_out_0(511, 256);
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d_hbm_p5_w[offset_hbm_5 + offset_local + i] = packed_pedestal_out_0(767, 512);
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}
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} else {
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for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {
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#pragma HLS PIPELINE II=1
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data_in >> packet;
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data_out << packet;
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}
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}
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s_axis_completion >> cmpl;
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}
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if (pedestal_mode) {
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for (int s = 0; s < nstoragecells; s++) {
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for (int m = 0; m < nmodules; m++) {
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if (frame_count[s * nmodules + m] > 0) {
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axis_completion cmpl_pedestal;
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cmpl_pedestal.last = 0;
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cmpl_pedestal.frame_number = s;
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cmpl_pedestal.module = m;
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cmpl_pedestal.packet_mask(63, 0) = UINT64_MAX;
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cmpl_pedestal.packet_mask(127, 64) = UINT64_MAX;
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cmpl_pedestal.packet_mask(191, 128) = UINT64_MAX;
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cmpl_pedestal.packet_mask(255, 192) = UINT64_MAX;
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cmpl_pedestal.packet_count = frame_count[s * nmodules + m];
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cmpl_pedestal.pedestal = 1;
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m_axis_completion << cmpl_pedestal;
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save_frames:
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for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 128; i++) {
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#pragma HLS PIPELINE II=2
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packet_512_t packet_out;
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packed_pedestal_g0_t packed_pedestal_in_0;
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size_t offset_local = (s * nmodules + m) * (RAW_MODULE_SIZE * sizeof(uint16_t) / 128) + i;
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packed_pedestal_in_0(255, 0) = d_hbm_p0[offset_hbm_0 + offset_local];
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packed_pedestal_in_0(511, 256) = d_hbm_p1[offset_hbm_1 + offset_local];
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packed_pedestal_in_0(767, 512) = d_hbm_p2[offset_hbm_2 + offset_local];
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packet_out.data = pack_and_reduce(packed_pedestal_in_0);
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packet_out.user = 0;
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packet_out.last = 0;
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data_out << packet_out;
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packed_pedestal_in_0(255, 0) = d_hbm_p3[offset_hbm_3 + offset_local];
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packed_pedestal_in_0(511, 256) = d_hbm_p4[offset_hbm_4 + offset_local];
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packed_pedestal_in_0(767, 512) = d_hbm_p5[offset_hbm_5 + offset_local];
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packet_out.data = pack_and_reduce(packed_pedestal_in_0);
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packet_out.user = 0;
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packet_out.last = (i == RAW_MODULE_SIZE * sizeof(uint16_t) / 128 - 1);
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data_out << packet_out;
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}
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}
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}
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}
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}
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m_axis_completion << cmpl;
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data_in >> packet;
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data_out << packet;
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}
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