345 lines
13 KiB
C++
345 lines
13 KiB
C++
// Copyright (2019-2023) Paul Scherrer Institute
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#include "FPGAAcquisitionDevice.h"
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#include <random>
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#include <bitset>
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#include "../common/to_fixed.h"
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void FPGAAcquisitionDevice::StartSendingWorkRequests() {
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stop_work_requests = false;
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send_work_request_future = std::async(std::launch::async, &FPGAAcquisitionDevice::SendWorkRequestThread, this);
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}
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void FPGAAcquisitionDevice::Finalize() {
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read_work_completion_future.get();
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stop_work_requests = true;
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send_work_request_future.get();
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FPGA_EndAction();
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while (!HW_IsIdle())
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std::this_thread::sleep_for(std::chrono::milliseconds(1));
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SetDataSource(default_data_source);
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}
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void FPGAAcquisitionDevice::ReadWorkCompletionThread() {
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uint32_t values;
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Completion c{};
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bool quit_loop = false;
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do {
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while (!HW_ReadMailbox(&values))
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std::this_thread::sleep_for(std::chrono::microseconds(10));
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c = parse_hw_completion(values);
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if (c.data_collection_id == data_collection_id) {
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work_completion_queue.PutBlocking(c);
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if (c.type == Completion::Type::End)
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quit_loop = true;
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} else if (logger) {
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if (c.type == Completion::Type::Start)
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logger->Warning("Stream {} Start completion with wrong data collection ID", data_stream);
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else
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logger->Warning("Stream {} Image completion with wrong data collection ID frame {} module {}",
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data_stream, c.frame_number, c.module_number);
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}
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} while (!quit_loop);
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}
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void FPGAAcquisitionDevice::SendWorkRequestThread() {
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while (!stop_work_requests) {
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WorkRequest wr{};
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if (work_request_queue.Get(wr)) {
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if ( !HW_SendWorkRequest(wr.handle)) {
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work_request_queue.Put(wr);
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std::this_thread::sleep_for(std::chrono::microseconds(10));
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}
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} else {
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std::this_thread::sleep_for(std::chrono::microseconds(10));
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}
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}
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}
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void FPGAAcquisitionDevice::InitializeIntegrationMap(const DiffractionExperiment &experiment,
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const std::vector<uint16_t> &v) {
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std::vector<float> weights(experiment.GetModulesNum() * RAW_MODULE_SIZE, 1.0);
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InitializeIntegrationMap(experiment, v, weights);
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}
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void FPGAAcquisitionDevice::InitializeIntegrationMap(const DiffractionExperiment &experiment,
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const std::vector<uint16_t> &v,
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const std::vector<float> &weights) {
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auto offset = experiment.GetFirstModuleOfDataStream(data_stream);
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if (v.size() != experiment.GetModulesNum() * RAW_MODULE_SIZE)
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Mismatch regarding integration map array");
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if (weights.size() != experiment.GetModulesNum() * RAW_MODULE_SIZE)
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Mismatch regarding weights array");
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size_t modules = experiment.GetModulesNum(data_stream);
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if (modules > 2 * buffer_device.size())
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Not enough host/FPGA buffers to load all integration map values");
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for (int m = 0; m < modules; m++)
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memcpy(buffer_device[m], v.data() + (offset + m) * RAW_MODULE_SIZE, RAW_MODULE_SIZE * sizeof(uint16_t));
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for (int m = 0; m < modules; m++) {
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for (int i = 0; i < RAW_MODULE_SIZE; i++) {
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buffer_device[modules + m][i] = to_fixed(weights[(offset + m) * RAW_MODULE_SIZE + i], 15);
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}
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}
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HW_LoadIntegrationMap(modules);
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}
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void FPGAAcquisitionDevice::SetInternalGeneratorFrameForAllModules(const std::vector<uint16_t> &v) {
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if (v.size() != RAW_MODULE_SIZE) {
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Error in size of custom internal generator frame");
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}
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for (int m = 0; m < max_modules; m++) {
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memcpy(internal_pkt_gen_frame.data() + m * RAW_MODULE_SIZE,
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v.data(), RAW_MODULE_SIZE * sizeof(uint16_t));
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}
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if (max_modules > buffer_device.size())
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Not enough host/FPGA buffers to load all integration map values");
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for (int m = 0; m < max_modules; m++)
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memcpy(buffer_device[m], internal_pkt_gen_frame.data() + m * RAW_MODULE_SIZE, RAW_MODULE_SIZE * sizeof(uint16_t));
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HW_LoadInternalGeneratorFrame(max_modules);
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}
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void FPGAAcquisitionDevice::SetInternalGeneratorFrame(const std::vector<uint16_t> &v) {
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if (v.empty() || (v.size() % RAW_MODULE_SIZE != 0)) {
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Error in size of custom internal generator frame");
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}
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size_t nmodules = v.size() / RAW_MODULE_SIZE;
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if (nmodules > max_modules) {
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Max number of modules exceeded");
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}
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memcpy(internal_pkt_gen_frame.data(), v.data(), nmodules * RAW_MODULE_SIZE * sizeof(uint16_t));
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if (nmodules > buffer_device.size())
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Not enough host/FPGA buffers to load all integration map values");
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for (int m = 0; m < nmodules; m++)
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memcpy(buffer_device[m], internal_pkt_gen_frame.data() + m * RAW_MODULE_SIZE, RAW_MODULE_SIZE * sizeof(uint16_t));
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HW_LoadInternalGeneratorFrame(nmodules);
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}
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void FPGAAcquisitionDevice::InitializeCalibration(const DiffractionExperiment &experiment, const JFCalibration &calib) {
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auto offset = experiment.GetFirstModuleOfDataStream(data_stream);
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if (calib.GetModulesNum() != experiment.GetModulesNum())
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Mismatch regarding module count in calibration and experiment description");
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if (calib.GetStorageCellNum() != experiment.GetStorageCellNumber())
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Mismatch regarding storage cell count in calibration and experiment description");
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size_t modules = experiment.GetModulesNum(data_stream);
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size_t storage_cells = experiment.GetStorageCellNumber();
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if (modules * (3 + 3 * storage_cells) > buffer_device.size())
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throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
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"Not enough host/FPGA buffers to load all calibration constants");
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for (int m = 0; m < modules; m++) {
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calib.GainCalibration(m).ExportG0(buffer_device[m]);
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calib.GainCalibration(m).ExportG1(buffer_device[m + modules]);
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calib.GainCalibration(m).ExportG2(buffer_device[m + modules * 2]);
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}
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for (int s = 0; s < storage_cells; s++) {
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auto mask = calib.CalculateMask(experiment, s);
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for (int m = 0; m < modules; m++) {
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auto pedestal_g0 = calib.Pedestal(offset + m, 0, s).GetPedestal();
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auto pedestal_g1 = calib.Pedestal(offset + m, 1, s).GetPedestal();
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auto pedestal_g2 = calib.Pedestal(offset + m, 2, s).GetPedestal();
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for (int i = 0; i < RAW_MODULE_SIZE; i++) {
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if (experiment.GetApplyPixelMaskInFPGA() && (mask[(offset + m) * RAW_MODULE_SIZE + i] != 0)) {
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buffer_device[(3 + 0 * storage_cells + s) * modules + m][i] = 16384;
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buffer_device[(3 + 1 * storage_cells + s) * modules + m][i] = 16384;
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buffer_device[(3 + 2 * storage_cells + s) * modules + m][i] = 16384;
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} else {
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buffer_device[(3 + 0 * storage_cells + s) * modules + m][i] = pedestal_g0[i];
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buffer_device[(3 + 1 * storage_cells + s) * modules + m][i] = pedestal_g1[i];
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buffer_device[(3 + 2 * storage_cells + s) * modules + m][i] = pedestal_g2[i];
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}
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}
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}
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}
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HW_LoadCalibration(modules, storage_cells);
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}
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union float_uint32 {
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float f;
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uint32_t u;
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};
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inline uint32_t float2uint(float f) {
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float_uint32 fu;
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fu.f = f;
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return fu.u;
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}
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void FPGAAcquisitionDevice::FillActionRegister(const DiffractionExperiment& x, DataCollectionConfig &job) {
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std::random_device rd;
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std::uniform_int_distribution<uint16_t> dist;
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data_collection_id = dist(rd);
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job.nmodules = x.GetModulesNum(data_stream) - 1;
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job.nframes = x.GetFrameNum();
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job.one_over_energy = float2uint(1 / x.GetPhotonEnergy_keV());
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job.nstorage_cells = x.GetStorageCellNumber() - 1;
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job.mode = data_collection_id << 16;
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job.nsummation = x.GetSummation() - 1;
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expected_descriptors_per_module = 5;
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switch (x.GetDetectorMode()) {
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case DetectorMode::Conversion:
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job.mode |= MODE_CONV;
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break;
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case DetectorMode::Raw:
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break;
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case DetectorMode::PedestalG0:
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job.mode |= MODE_PEDESTAL_G0;
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break;
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case DetectorMode::PedestalG1:
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job.mode |= MODE_PEDESTAL_G1;
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break;
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case DetectorMode::PedestalG2:
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job.mode |= MODE_PEDESTAL_G2;
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break;
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}
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if (!x.IsPixelSigned())
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job.mode |= MODE_UNSIGNED;
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if (x.GetPixelDepth() == 4)
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job.mode |= MODE_32BIT;
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}
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void FPGAAcquisitionDevice::Start(const DiffractionExperiment &experiment, uint32_t flag) {
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if (!HW_IsIdle())
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throw(JFJochException(JFJochExceptionCategory::AcquisitionDeviceError,
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"Hardware action running prior to start of data acquisition"));
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if (experiment.IsUsingInternalPacketGen())
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SetDataSource(AcquisitionDeviceSource::FRAME_GENERATOR);
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else
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SetDataSource(default_data_source);
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DataCollectionConfig cfg_in{}, cfg_out{};
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FillActionRegister(experiment, cfg_in);
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cfg_in.mode |= flag;
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HW_WriteActionRegister(&cfg_in);
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HW_ReadActionRegister(&cfg_out);
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if (cfg_out.mode != cfg_in.mode)
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throw JFJochException(JFJochExceptionCategory::AcquisitionDeviceError,
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"Mismatch between expected and actual values of configuration registers (mode)");
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if (cfg_out.nframes != cfg_in.nframes)
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throw JFJochException(JFJochExceptionCategory::AcquisitionDeviceError,
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"Mismatch between expected and actual values of configuration registers (Frames per trigger)");
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if (cfg_out.nmodules != cfg_in.nmodules)
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throw JFJochException(JFJochExceptionCategory::AcquisitionDeviceError,
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"Mismatch between expected and actual values of configuration registers (#modules)");
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FPGA_StartAction(experiment);
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read_work_completion_future = std::async(std::launch::async, &FPGAAcquisitionDevice::ReadWorkCompletionThread, this);
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}
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std::vector<uint16_t> FPGAAcquisitionDevice::GetInternalGeneratorFrame() const {
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return internal_pkt_gen_frame;
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}
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void FPGAAcquisitionDevice::SetInternalGeneratorFrame() {
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std::vector<uint16_t> tmp(RAW_MODULE_SIZE);
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for (int i = 0; i < RAW_MODULE_SIZE; i++)
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tmp[i] = i % 65536;
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SetInternalGeneratorFrameForAllModules(tmp);
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}
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FPGAAcquisitionDevice::FPGAAcquisitionDevice(uint16_t data_stream)
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: AcquisitionDevice(data_stream),
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internal_pkt_gen_frame(RAW_MODULE_SIZE * MAX_MODULES_FPGA) {
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}
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void FPGAAcquisitionDevice::SetSpotFinderParameters(int16_t count_threshold, double snr_threshold) {
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if (snr_threshold < 0) {
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if (logger)
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logger->Warning("Trying to set SNR threshold below zero: {}", snr_threshold );
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snr_threshold = 0;
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} else if (snr_threshold > 64) {
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if (logger)
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logger->Warning("Trying to set SNR threshold too high: {}", snr_threshold );
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snr_threshold = 64;
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}
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SpotFinderParameters params{.count_threshold = count_threshold, .snr_threshold = to_fixed(snr_threshold, 2)};
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HW_SetSpotFinderParameters(params);
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}
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AcquisitionDeviceSource FPGAAcquisitionDevice::GetDataSource() {
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switch (HW_GetDataSource()) {
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case STREAM_MERGE_SRC_100G:
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return AcquisitionDeviceSource::MAC_100G;
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case STREAM_MERGE_SRC_4x10G:
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return AcquisitionDeviceSource::MAC_4x10G;
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case STREAM_MERGE_SRC_FRAME_GEN:
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return AcquisitionDeviceSource::FRAME_GENERATOR;
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default:
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return AcquisitionDeviceSource::NONE;
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}
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}
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void FPGAAcquisitionDevice::SetDefaultDataSource(AcquisitionDeviceSource id) {
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default_data_source = id;
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SetDataSource(id);
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}
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void FPGAAcquisitionDevice::SetDataSource(AcquisitionDeviceSource id) {
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switch (id) {
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case AcquisitionDeviceSource::MAC_100G:
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HW_SetDataSource(STREAM_MERGE_SRC_100G);
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break;
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case AcquisitionDeviceSource::MAC_4x10G:
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HW_SetDataSource(STREAM_MERGE_SRC_4x10G);
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break;
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case AcquisitionDeviceSource::FRAME_GENERATOR:
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HW_SetDataSource(STREAM_MERGE_SRC_FRAME_GEN);
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break;
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case AcquisitionDeviceSource::NONE:
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HW_SetDataSource(STREAM_MERGE_SRC_NONE);
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break;
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}
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}
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uint32_t FPGAAcquisitionDevice::GetExpectedDescriptorsPerModule() const {
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return expected_descriptors_per_module;
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}
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