113 lines
4.2 KiB
Tcl
113 lines
4.2 KiB
Tcl
## Copyright (2019-2022) Paul Scherrer Institute
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## SPDX-License-Identifier: CERN-OHL-S-2.0
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##
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open_project $::env(VIV_PROJECT_PATH)
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set flow $::env(FLOW)
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set part [get_property PART [current_project]]
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if {$part eq {xcvu35p-fsvh2104-2-e}} {
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set fpga_flash_size 128
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set fpga_name "VU35P"
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set interface "SPIx8"
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} elseif {$part eq {xcu55c-fsvh2892-2L-e}} {
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set fpga_flash_size 128
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set fpga_name "U55C"
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set interface "SPIx4"
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} elseif {$part eq {xcu50-fsvh2104-2-e}} {
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set fpga_flash_size 128
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set fpga_name "U50"
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set interface "SPIx8"
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} else {
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set fpga_flash_size 64
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set fpga_name "VU33P"
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set interface "SPIx8"
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}
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set bitstream_name jfjoch_${flow}_${fpga_name}_rel@RELEASE_LEVEL@_@GIT_SHA1@
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puts "Part $part Flash size ${fpga_flash_size} Flow ${flow} Image name ${bitstream_name}"
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set log_file synth.log
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puts "Synthesis..."
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synth_design -directive PerformanceOptimized -flatten_hierarchy rebuilt -bufg 12 -fanout_limit 400 -fsm_extraction one_hot -resource_sharing off -no_lc -shreg_min_size 5 -cascade_dsp auto -control_set_opt_threshold auto -gated_clock_conversion off > synth.log
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puts "Opt design..."
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opt_design -directive Explore > opt_design.log
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xilinx::designutils::report_failfast
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write_checkpoint -force jungfraujoch_synth.dcp
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puts "Place design..."
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place_design -directive Explore > place_design.log
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set WNSPLACE [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup] ]
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puts "Place WNS (before optimization): $WNSPLACE ps"
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puts "Phys opt design..."
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set NLOOPS 3
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set WNS [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup] ]
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for {set i 0} {$i < $NLOOPS} {incr i} {
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if {$WNS < 0.000} {
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phys_opt_design -directive AggressiveExplore >> phys_opt_design.log
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phys_opt_design -directive AggressiveFanoutOpt >> phys_opt_design.log
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phys_opt_design -directive AlternateReplication >> phys_opt_design.log
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set WNS [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup] ]
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puts "Iter $i WNS: $WNS ps"
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}
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}
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set WNSPLACE [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup] ]
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puts " ***** Place WNS: $WNSPLACE ps *****"
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write_checkpoint -force jungfraujoch_place.dcp
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if {$WNSPLACE > -1.000} {
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puts "Route design..."
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route_design -directive Explore -tns_cleanup -ultrathreads > route_design.log
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set WNSROUTE [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup] ]
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puts "Route WNS (before optimization): $WNSROUTE ps"
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write_checkpoint -force jungfraujoch_route.dcp
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report_utilization -no_primitives
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if {$WNSROUTE < 0.0} {
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puts "Phys opt design after routing (1st round) ..."
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phys_opt_design -directive AggressiveExplore > phys_opt_design_post_route.log
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set WNSROUTE [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup] ]
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puts "Route WNS (1st round optimization): $WNSROUTE ps"
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}
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if {$WNSROUTE < 0.0} {
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puts "Phys opt design after routing (2nd round) ..."
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phys_opt_design -directive AggressiveExplore >> phys_opt_design_post_route.log
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set WNSROUTE [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup] ]
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puts "Route WNS (2nd round optimization): $WNSROUTE ps"
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}
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write_checkpoint -force jungfraujoch_route_opt.dcp
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puts ""
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puts " ***** Final WNS: $WNSROUTE ps *****"
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puts ""
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if {$WNSROUTE >= -0.050} {
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write_bitstream -force -file ${bitstream_name} >> bitstream.log
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if {$part eq {xcu55c-fsvh2892-2L-e}} {
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write_cfgmem -force -size 128 -format mcs -interface SPIx4 -loadbit "up 0x01002000 ${bitstream_name}.bit" ${bitstream_name} >> cfgmem.log
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puts " ***** Bitstream ${bitstream_name}.mcs written! *****"
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} else {
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write_cfgmem -force -size ${fpga_flash_size} -format bin -interface ${interface} -loadbit "up 0x0 ${bitstream_name}.bit" ${bitstream_name} >> cfgmem.log
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puts " ***** Bitstream ${bitstream_name}.bin written! *****"
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}
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puts ""
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} else {
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puts " ***** Cannot write bitstream due to negative WNS *****"
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puts ""
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close_project
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exit 1
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}
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} else {
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puts " ***** WNS place < -1 ns, no chance of success *****"
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close_project
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exit 1
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}
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