leonarski_fandClaude Opus 4.8
51451f167b
Add AzimuthalIntegrationSettings::ForceCPUinFPGAWorkflow so the FPGA data-acquisition path can compute azimuthal integration on the CPU instead of the FPGA. This removes the FPGA bin-count limit (FPGA_INTEGRATION_BIN_COUNT) and adds per-bin standard deviation. - MXAnalysisAfterFPGA runs AzIntEngineCPU on the assembled image; the FPGA integration-map load and per-module read-back are skipped when forced. - JFJochReceiverFPGA rejects bin counts above the FPGA limit at acquisition start (unless CPU is forced) with an actionable error. - Wire force_cpu through the broker (both directions) and the frontend. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
53 lines
2.0 KiB
C++
53 lines
2.0 KiB
C++
// SPDX-FileCopyrightText: 2024 Filip Leonarski, Paul Scherrer Institute <filip.leonarski@psi.ch>
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// SPDX-License-Identifier: GPL-3.0-only
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#pragma once
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#include <optional>
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#include <cstdint>
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class AzimuthalIntegrationSettings {
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bool solid_angle_correction = true;
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bool polarization_correction = true;
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float high_q_recipA = 5.0;
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float low_q_recipA = 0.1;
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float bkg_estimate_high_q_recipA = 2.0f * M_PI / 3.0;
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float bkg_estimate_low_q_recipA = 2.0f * M_PI / 5.0;
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float q_spacing = 0.05;
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int32_t azim_bins = 1;
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// Compute azimuthal integration on the CPU instead of the FPGA during the FPGA
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// acquisition workflow. Lifts the FPGA bin-count limit and adds standard-deviation output.
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bool force_cpu_in_fpga_workflow = false;
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int32_t q_bins= 0;
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int32_t total_bins = 0;
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void UpdateBinCount();
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public:
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AzimuthalIntegrationSettings();
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AzimuthalIntegrationSettings& SolidAngleCorrection(bool input);
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AzimuthalIntegrationSettings& PolarizationCorrection(bool input);
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AzimuthalIntegrationSettings& QRange_recipA(float low, float high);
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AzimuthalIntegrationSettings& QSpacing_recipA(float input);
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AzimuthalIntegrationSettings& BkgEstimateQRange_recipA(float low, float high);
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AzimuthalIntegrationSettings& AzimuthalBinCount(int32_t input);
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AzimuthalIntegrationSettings& ForceCPUinFPGAWorkflow(bool input);
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[[nodiscard]] bool IsSolidAngleCorrection() const;
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[[nodiscard]] bool IsPolarizationCorrection() const;
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[[nodiscard]] float GetHighQ_recipA() const;
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[[nodiscard]] float GetLowQ_recipA() const;
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[[nodiscard]] float GetQSpacing_recipA() const;
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[[nodiscard]] int32_t GetBinCount() const;
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[[nodiscard]] int32_t GetQBinCount() const;
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[[nodiscard]] int32_t GetAzimuthalBinCount() const;
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[[nodiscard]] bool IsForceCPUinFPGAWorkflow() const;
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[[nodiscard]] float GetBkgEstimateLowQ_recipA() const;
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[[nodiscard]] float GetBkgEstimateHighQ_recipA() const;
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[[nodiscard]] uint16_t QToBin(float q) const;
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[[nodiscard]] uint16_t GetBin(float q, float phi_deg) const;
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};
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