// Copyright (2019-2024) Paul Scherrer Institute #include #include "../fpga/hls/hls_jfjoch.h" TEST_CASE("FPGA_EigerReorderTest") { STREAM_512 data_in; STREAM_512 data_out; hls::stream compl_in; hls::stream compl_out; std::vector input_frame(RAW_MODULE_SIZE), output_frame(RAW_MODULE_SIZE); auto input_frame_512 = (ap_uint<512> *) input_frame.data(); auto output_frame_512 = (ap_uint<512> *) output_frame.data(); for (int i = 0; i < RAW_MODULE_SIZE; i++) input_frame[i] = i % 16380; // just make sure this is not multiple of power of 2 data_in << packet_512_t{.data = 0, .user = 0}; for (int i = 0; i < 16384; i++) data_in << packet_512_t{.data = input_frame_512[i], .user = 0}; data_in << packet_512_t{.data = 0, .user = 1}; compl_in << axis_completion{.detector_type = SLS_DETECTOR_TYPE_EIGER, .last = 0}; compl_in << axis_completion{.last = 1}; eiger_reorder(data_in, data_out, compl_in, compl_out); REQUIRE(compl_in.size() == 0); REQUIRE(compl_out.size() == 2); REQUIRE(data_in.size() == 0); REQUIRE(data_out.size() == 16384 + 2); packet_512_t packet; data_out >> packet; for (int i = 0; i < 16384; i++) { data_out >> packet; output_frame_512[i] = packet.data; } data_out >> packet; CHECK(input_frame[0] == output_frame[1024*3]); CHECK(input_frame[511] == output_frame[1024*3 + 511]); CHECK(input_frame[512+174] == output_frame[1024*2+174]); CHECK(input_frame[1024+300] == output_frame[1024+300]); CHECK(input_frame[2048] == output_frame[1024*3 + 512]); CHECK(input_frame[2048+511] == output_frame[1024*3 + 512 + 511]); CHECK(input_frame[2048+1024+134] == output_frame[512+1024+134]); CHECK(input_frame[4095] == output_frame[1023]); CHECK(input_frame[4096*63 + 2048+1024+134] == output_frame[4096*63+512+1024+134]); CHECK(input_frame[4096*25 + 2048+1024+134] == output_frame[4096*25+512+1024+134]); CHECK(input_frame[4096*80 + 134] == output_frame[4096*80 + 134]); CHECK(input_frame[4096*80 + 2048 + 196] == output_frame[4096*80 + 512 + 196]); CHECK(input_frame[4096*127 + 2048 + 1024 + 191] == output_frame[4096*127+ 512 +02* 1024 + 191]); }