FPGA data flow

The following steps are performed on FPGA (in the order of operation):

  1. UDP header decoding

  2. SLS detector header decoding

  3. State machine that controls data acquisition (start/stop/cancel)

  4. High-bandwidth memory cache to buffer network packets and reorder them to form full modules

  5. ADU histogram for JUNGFRAU

  6. Mask pixels from missing packets with special value

  7. Reorder lines for EIGER to form a proper module

  8. Mask pixels based on provided pixel mask

  9. JUNGFRAU conversion with gain and pedestal corrections

  10. Threshold: pixel values below a set minimum are zeroed, values above a set maximum saturated

  11. Frame summation (up to 256 frames)

  12. Integration according to predefined map (e.g., 1D azimuthal integration)

  13. Spot finding

  14. ROI calculation

  15. Image lossy compression using N*sqrt(pixel) values

  16. Send images, analysis results and metadata to host memory via PCI Express

Each step has a dedicated core, written in high-level synthesis. Exact operation of cores for data analysis is explained in dedicated document.