## Copyright (2019-2023) Paul Scherrer Institute

# Hierarchical cell: image_processing
proc create_hier_cell_image_processing { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_image_processing() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 data_in

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 data_out

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 integration_result_out

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p0

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p1

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p2

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p3

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p4

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p5

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p6

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p7

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p8

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p9

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p10

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p11

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p16

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p17

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p18

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p19

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p22

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p23

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p24

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p25

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p26

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p27

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_completion

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 result_out

  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_completion

  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 spot_finder_out


  # Create pins
  create_bd_pin -dir I -type rst ap_rst_n
  create_bd_pin -dir I -type clk axi_clk
  create_bd_pin -dir I -type rst axi_rst_n
  create_bd_pin -dir I -from 31 -to 0 -type data hbm_size_bytes
  create_bd_pin -dir I -from 15 -to 0 -type data in_count_threshold
  create_bd_pin -dir I -from 7 -to 0 -type data in_snr_threshold
  create_bd_pin -dir O proc_fifo_empty
  create_bd_pin -dir O proc_fifo_full

  # Create instance: adu_histo_0, and set properties
  set adu_histo_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:adu_histo:1.0 adu_histo_0 ]

  # Create instance: axis_32_to_512_0, and set properties
  set axis_32_to_512_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:axis_32_to_512:1.0 axis_32_to_512_0 ]

  # Create instance: axis_64_to_512_0, and set properties
  set axis_64_to_512_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:axis_64_to_512:1.0 axis_64_to_512_0 ]

  # Create instance: axis_compl_fifo_0, and set properties
  set axis_compl_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_compl_fifo_0 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {16} \
   CONFIG.HAS_AEMPTY {0} \
   CONFIG.HAS_AFULL {0} \
 ] $axis_compl_fifo_0

  # Create instance: axis_compl_fifo_1, and set properties
  set axis_compl_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_compl_fifo_1 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {16} \
   CONFIG.HAS_AEMPTY {0} \
   CONFIG.HAS_AFULL {0} \
 ] $axis_compl_fifo_1

  # Create instance: axis_compl_fifo_2, and set properties
  set axis_compl_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_compl_fifo_2 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {16} \
 ] $axis_compl_fifo_2

  # Create instance: axis_compl_fifo_3, and set properties
  set axis_compl_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_compl_fifo_3 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {16} \
 ] $axis_compl_fifo_3

  # Create instance: axis_compl_fifo_4, and set properties
  set axis_compl_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_compl_fifo_4 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {16} \
 ] $axis_compl_fifo_4

  # Create instance: axis_data_fifo_0, and set properties
  set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {256} \
 ] $axis_data_fifo_0

  # Create instance: axis_data_fifo_1, and set properties
  set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {256} \
 ] $axis_data_fifo_1

  # Create instance: axis_data_fifo_2, and set properties
  set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {256} \
 ] $axis_data_fifo_2

  # Create instance: axis_data_fifo_3, and set properties
  set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {256} \
 ] $axis_data_fifo_3

  # Create instance: axis_data_fifo_4, and set properties
  set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {256} \
 ] $axis_data_fifo_4

  # Create instance: axis_data_fifo_5, and set properties
  set axis_data_fifo_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_5 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {256} \
 ] $axis_data_fifo_5

  # Create instance: axis_data_fifo_6, and set properties
  set axis_data_fifo_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_6 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {256} \
   CONFIG.HAS_AEMPTY {1} \
   CONFIG.HAS_AFULL {1} \
 ] $axis_data_fifo_6

  # Create instance: axis_data_fifo_7, and set properties
  set axis_data_fifo_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_7 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {256} \
 ] $axis_data_fifo_7

  # Create instance: axis_integration_result_fifo_0, and set properties
  set axis_integration_result_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_integration_result_fifo_0 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {256} \
 ] $axis_integration_result_fifo_0

  # Create instance: axis_integration_result_fifo_1, and set properties
  set axis_integration_result_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_integration_result_fifo_1 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {512} \
 ] $axis_integration_result_fifo_1

  # Create instance: axis_register_slice_data_1, and set properties
  set axis_register_slice_data_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_data_1 ]
  set_property -dict [ list \
   CONFIG.REG_CONFIG {16} \
 ] $axis_register_slice_data_1

  # Create instance: axis_register_slice_data_2, and set properties
  set axis_register_slice_data_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_data_2 ]
  set_property -dict [ list \
   CONFIG.REG_CONFIG {16} \
 ] $axis_register_slice_data_2

  # Create instance: axis_register_slice_data_3, and set properties
  set axis_register_slice_data_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_data_3 ]
  set_property -dict [ list \
   CONFIG.REG_CONFIG {16} \
 ] $axis_register_slice_data_3

  # Create instance: axis_spot_finder_fifo_0, and set properties
  set axis_spot_finder_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_spot_finder_fifo_0 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {32} \
 ] $axis_spot_finder_fifo_0

  # Create instance: axis_spot_finder_fifo_1, and set properties
  set axis_spot_finder_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_spot_finder_fifo_1 ]
  set_property -dict [ list \
   CONFIG.FIFO_DEPTH {2048} \
   CONFIG.FIFO_MEMORY_TYPE {ultra} \
 ] $axis_spot_finder_fifo_1

  # Create instance: frame_summation_0, and set properties
  set frame_summation_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:frame_summation:1.0 frame_summation_0 ]

  # Create instance: integration_0, and set properties
  set integration_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:integration:1.0 integration_0 ]

  # Create instance: jf_conversion_0, and set properties
  set jf_conversion_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:jf_conversion:1.0 jf_conversion_0 ]

  # Create instance: mask_missing_0, and set properties
  set mask_missing_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:mask_missing:1.0 mask_missing_0 ]

  # Create instance: one, and set properties
  set one [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one ]

  # Create instance: pedestal_0, and set properties
  set pedestal_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:pedestal:1.0 pedestal_0 ]

  # Create instance: smartconnect_0, and set properties
  set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]

  # Create instance: smartconnect_1, and set properties
  set smartconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_1 ]

  # Create instance: smartconnect_2, and set properties
  set smartconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_2 ]

  # Create instance: smartconnect_3, and set properties
  set smartconnect_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_3 ]

  # Create instance: smartconnect_4, and set properties
  set smartconnect_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_4 ]

  # Create instance: smartconnect_5, and set properties
  set smartconnect_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_5 ]

  # Create instance: spot_finder_0, and set properties
  set spot_finder_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:spot_finder:1.0 spot_finder_0 ]

  # Create instance: stream_24bit_conv_0, and set properties
  set stream_24bit_conv_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:stream_24bit_conv:1.0 stream_24bit_conv_0 ]

  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins spot_finder_out] [get_bd_intf_pins axis_spot_finder_fifo_1/M_AXIS]
  connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins m_axi_d_hbm_p0] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p0]
  connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins integration_result_out] [get_bd_intf_pins axis_integration_result_fifo_1/M_AXIS]
  connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins m_axi_d_hbm_p16] [get_bd_intf_pins integration_0/m_axi_d_hbm_p0]
  connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins m_axi_d_hbm_p17] [get_bd_intf_pins integration_0/m_axi_d_hbm_p1]
  connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins m_axi_d_hbm_p18] [get_bd_intf_pins integration_0/m_axi_d_hbm_p2]
  connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins m_axi_d_hbm_p19] [get_bd_intf_pins integration_0/m_axi_d_hbm_p3]
  connect_bd_intf_net -intf_net Conn12 [get_bd_intf_pins m_axi_d_hbm_p3] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p3]
  connect_bd_intf_net -intf_net Conn13 [get_bd_intf_pins m_axi_d_hbm_p4] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p4]
  connect_bd_intf_net -intf_net Conn15 [get_bd_intf_pins m_axi_d_hbm_p5] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p5]
  connect_bd_intf_net -intf_net Conn19 [get_bd_intf_pins result_out] [get_bd_intf_pins adu_histo_0/result_out]
  connect_bd_intf_net -intf_net Conn21 [get_bd_intf_pins m_axi_d_hbm_p6] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p6]
  connect_bd_intf_net -intf_net Conn23 [get_bd_intf_pins m_axi_d_hbm_p7] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p7]
  connect_bd_intf_net -intf_net Conn26 [get_bd_intf_pins m_axi_d_hbm_p8] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p8]
  connect_bd_intf_net -intf_net Conn27 [get_bd_intf_pins m_axi_d_hbm_p9] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p9]
  connect_bd_intf_net -intf_net Conn28 [get_bd_intf_pins m_axi_d_hbm_p10] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p10]
  connect_bd_intf_net -intf_net Conn29 [get_bd_intf_pins m_axi_d_hbm_p11] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p11]
  connect_bd_intf_net -intf_net Conn30 [get_bd_intf_pins m_axi_d_hbm_p2] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p2]
  connect_bd_intf_net -intf_net Conn31 [get_bd_intf_pins m_axi_d_hbm_p1] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p1]
  connect_bd_intf_net -intf_net adu_histo_0_data_out [get_bd_intf_pins adu_histo_0/data_out] [get_bd_intf_pins axis_data_fifo_2/S_AXIS]
  connect_bd_intf_net -intf_net adu_histo_0_m_axis_completion [get_bd_intf_pins adu_histo_0/m_axis_completion] [get_bd_intf_pins axis_compl_fifo_1/S_AXIS]
  connect_bd_intf_net -intf_net axis_32_to_512_0_data_out [get_bd_intf_pins axis_32_to_512_0/data_out] [get_bd_intf_pins axis_spot_finder_fifo_1/S_AXIS]
  connect_bd_intf_net -intf_net axis_64_to_512_0_data_out [get_bd_intf_pins axis_64_to_512_0/data_out] [get_bd_intf_pins axis_integration_result_fifo_1/S_AXIS]
  connect_bd_intf_net -intf_net axis_compl_fifo_0_M_AXIS [get_bd_intf_pins adu_histo_0/s_axis_completion] [get_bd_intf_pins axis_compl_fifo_0/M_AXIS]
  connect_bd_intf_net -intf_net axis_compl_fifo_1_M_AXIS [get_bd_intf_pins axis_compl_fifo_2/M_AXIS] [get_bd_intf_pins jf_conversion_0/s_axis_completion]
  connect_bd_intf_net -intf_net axis_compl_fifo_2_M_AXIS [get_bd_intf_pins axis_compl_fifo_1/M_AXIS] [get_bd_intf_pins mask_missing_0/s_axis_completion]
  connect_bd_intf_net -intf_net axis_compl_fifo_4_M_AXIS [get_bd_intf_pins axis_compl_fifo_3/M_AXIS] [get_bd_intf_pins frame_summation_0/s_axis_completion]
  connect_bd_intf_net -intf_net axis_compl_fifo_5_M_AXIS [get_bd_intf_pins axis_compl_fifo_4/M_AXIS] [get_bd_intf_pins integration_0/s_axis_completion]
  connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins pedestal_0/data_in]
  connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins adu_histo_0/data_in] [get_bd_intf_pins axis_data_fifo_1/M_AXIS]
  connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS1 [get_bd_intf_pins axis_data_fifo_3/M_AXIS] [get_bd_intf_pins jf_conversion_0/data_in]
  connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins axis_data_fifo_2/M_AXIS] [get_bd_intf_pins mask_missing_0/data_in]
  connect_bd_intf_net -intf_net axis_data_fifo_5_M_AXIS1 [get_bd_intf_pins axis_data_fifo_6/M_AXIS] [get_bd_intf_pins spot_finder_0/data_in]
  connect_bd_intf_net -intf_net axis_data_fifo_6_M_AXIS [get_bd_intf_pins axis_data_fifo_4/M_AXIS] [get_bd_intf_pins axis_register_slice_data_1/S_AXIS]
  connect_bd_intf_net -intf_net axis_data_fifo_6_M_AXIS1 [get_bd_intf_pins axis_data_fifo_7/M_AXIS] [get_bd_intf_pins stream_24bit_conv_0/data_in]
  connect_bd_intf_net -intf_net axis_data_fifo_7_M_AXIS [get_bd_intf_pins axis_data_fifo_5/M_AXIS] [get_bd_intf_pins integration_0/data_in]
  connect_bd_intf_net -intf_net axis_integration_result_fifo_0_M_AXIS [get_bd_intf_pins axis_64_to_512_0/data_in] [get_bd_intf_pins axis_integration_result_fifo_0/M_AXIS]
  connect_bd_intf_net -intf_net axis_register_slice_data_1_M_AXIS [get_bd_intf_pins axis_register_slice_data_1/M_AXIS] [get_bd_intf_pins frame_summation_0/data_in]
  connect_bd_intf_net -intf_net axis_register_slice_data_2_M_AXIS [get_bd_intf_pins axis_data_fifo_5/S_AXIS] [get_bd_intf_pins axis_register_slice_data_2/M_AXIS]
  connect_bd_intf_net -intf_net axis_register_slice_data_3_M_AXIS [get_bd_intf_pins data_out] [get_bd_intf_pins axis_register_slice_data_3/M_AXIS]
  connect_bd_intf_net -intf_net axis_spot_finder_fifo_0_M_AXIS [get_bd_intf_pins axis_32_to_512_0/data_in] [get_bd_intf_pins axis_spot_finder_fifo_0/M_AXIS]
  connect_bd_intf_net -intf_net data_in_1 [get_bd_intf_pins data_in] [get_bd_intf_pins axis_data_fifo_0/S_AXIS]
  connect_bd_intf_net -intf_net frame_summation_0_data_out [get_bd_intf_pins axis_register_slice_data_2/S_AXIS] [get_bd_intf_pins frame_summation_0/data_out]
  connect_bd_intf_net -intf_net frame_summation_0_m_axis_completion [get_bd_intf_pins axis_compl_fifo_4/S_AXIS] [get_bd_intf_pins frame_summation_0/m_axis_completion]
  connect_bd_intf_net -intf_net integration_0_data_out [get_bd_intf_pins axis_data_fifo_6/S_AXIS] [get_bd_intf_pins integration_0/data_out]
  connect_bd_intf_net -intf_net integration_0_m_axis_completion [get_bd_intf_pins m_axis_completion] [get_bd_intf_pins integration_0/m_axis_completion]
  connect_bd_intf_net -intf_net integration_0_result_out [get_bd_intf_pins axis_integration_result_fifo_0/S_AXIS] [get_bd_intf_pins integration_0/result_out]
  connect_bd_intf_net -intf_net jf_conversion_0_data_out [get_bd_intf_pins axis_data_fifo_4/S_AXIS] [get_bd_intf_pins jf_conversion_0/data_out]
  connect_bd_intf_net -intf_net jf_conversion_0_m_axis_completion [get_bd_intf_pins axis_compl_fifo_3/S_AXIS] [get_bd_intf_pins jf_conversion_0/m_axis_completion]
  connect_bd_intf_net -intf_net mask_missing_0_data_out [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins mask_missing_0/data_out]
  connect_bd_intf_net -intf_net mask_missing_0_m_axis_completion [get_bd_intf_pins axis_compl_fifo_2/S_AXIS] [get_bd_intf_pins mask_missing_0/m_axis_completion]
  connect_bd_intf_net -intf_net pedestal_0_data_out [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins pedestal_0/data_out]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p0 [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_0/S00_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p0_w [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p0_w] [get_bd_intf_pins smartconnect_0/S01_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p1 [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p1] [get_bd_intf_pins smartconnect_1/S00_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p1_w [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p1_w] [get_bd_intf_pins smartconnect_1/S01_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p2 [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p2] [get_bd_intf_pins smartconnect_2/S00_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p2_w [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p2_w] [get_bd_intf_pins smartconnect_2/S01_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p3 [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p3] [get_bd_intf_pins smartconnect_3/S00_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p3_w [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p3_w] [get_bd_intf_pins smartconnect_3/S01_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p4 [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p4] [get_bd_intf_pins smartconnect_4/S00_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p4_w [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p4_w] [get_bd_intf_pins smartconnect_4/S01_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p5 [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p5] [get_bd_intf_pins smartconnect_5/S00_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axi_d_hbm_p5_w [get_bd_intf_pins pedestal_0/m_axi_d_hbm_p5_w] [get_bd_intf_pins smartconnect_5/S01_AXI]
  connect_bd_intf_net -intf_net pedestal_0_m_axis_completion [get_bd_intf_pins axis_compl_fifo_0/S_AXIS] [get_bd_intf_pins pedestal_0/m_axis_completion]
  connect_bd_intf_net -intf_net s_axis_completion_1 [get_bd_intf_pins s_axis_completion] [get_bd_intf_pins pedestal_0/s_axis_completion]
  connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p22] [get_bd_intf_pins smartconnect_0/M00_AXI]
  connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p23] [get_bd_intf_pins smartconnect_1/M00_AXI]
  connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p24] [get_bd_intf_pins smartconnect_2/M00_AXI]
  connect_bd_intf_net -intf_net smartconnect_3_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p25] [get_bd_intf_pins smartconnect_3/M00_AXI]
  connect_bd_intf_net -intf_net smartconnect_4_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p26] [get_bd_intf_pins smartconnect_4/M00_AXI]
  connect_bd_intf_net -intf_net smartconnect_5_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p27] [get_bd_intf_pins smartconnect_5/M00_AXI]
  connect_bd_intf_net -intf_net spot_finder_0_data_out [get_bd_intf_pins axis_data_fifo_7/S_AXIS] [get_bd_intf_pins spot_finder_0/data_out]
  connect_bd_intf_net -intf_net spot_finder_0_strong_pixel_out [get_bd_intf_pins axis_spot_finder_fifo_0/S_AXIS] [get_bd_intf_pins spot_finder_0/strong_pixel_out]
  connect_bd_intf_net -intf_net stream_24bit_conv_0_data_out [get_bd_intf_pins axis_register_slice_data_3/S_AXIS] [get_bd_intf_pins stream_24bit_conv_0/data_out]

  # Create port connections
  connect_bd_net -net ap_rst_n_1 [get_bd_pins ap_rst_n] [get_bd_pins adu_histo_0/ap_rst_n] [get_bd_pins axis_32_to_512_0/ap_rst_n] [get_bd_pins axis_64_to_512_0/ap_rst_n] [get_bd_pins frame_summation_0/ap_rst_n] [get_bd_pins integration_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins pedestal_0/ap_rst_n] [get_bd_pins spot_finder_0/ap_rst_n] [get_bd_pins stream_24bit_conv_0/ap_rst_n]
  connect_bd_net -net ap_start_1 [get_bd_pins frame_summation_0/ap_start] [get_bd_pins one/dout] [get_bd_pins spot_finder_0/ap_start] [get_bd_pins stream_24bit_conv_0/ap_start] [get_bd_pins integration_0/ap_start]
  connect_bd_net -net axi_clk_1 [get_bd_pins axi_clk] [get_bd_pins adu_histo_0/ap_clk] [get_bd_pins axis_32_to_512_0/ap_clk] [get_bd_pins axis_64_to_512_0/ap_clk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_compl_fifo_3/s_axis_aclk] [get_bd_pins axis_compl_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_7/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_0/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_1/s_axis_aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_2/aclk] [get_bd_pins axis_register_slice_data_3/aclk] [get_bd_pins axis_spot_finder_fifo_0/s_axis_aclk] [get_bd_pins axis_spot_finder_fifo_1/s_axis_aclk] [get_bd_pins frame_summation_0/ap_clk] [get_bd_pins integration_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins pedestal_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins smartconnect_3/aclk] [get_bd_pins smartconnect_4/aclk] [get_bd_pins smartconnect_5/aclk] [get_bd_pins spot_finder_0/ap_clk] [get_bd_pins stream_24bit_conv_0/ap_clk]
  connect_bd_net -net axi_rst_n_1 [get_bd_pins axi_rst_n] [get_bd_pins axis_compl_fifo_0/s_axis_aresetn] [get_bd_pins axis_compl_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_compl_fifo_3/s_axis_aresetn] [get_bd_pins axis_compl_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_7/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_0/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_1/s_axis_aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_2/aresetn] [get_bd_pins axis_register_slice_data_3/aresetn] [get_bd_pins axis_spot_finder_fifo_0/s_axis_aresetn] [get_bd_pins axis_spot_finder_fifo_1/s_axis_aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn] [get_bd_pins smartconnect_3/aresetn] [get_bd_pins smartconnect_4/aresetn] [get_bd_pins smartconnect_5/aresetn]
  connect_bd_net -net axis_data_fifo_6_almost_empty [get_bd_pins proc_fifo_empty] [get_bd_pins axis_data_fifo_6/almost_empty]
  connect_bd_net -net axis_data_fifo_6_almost_full [get_bd_pins proc_fifo_full] [get_bd_pins axis_data_fifo_6/almost_full]
  connect_bd_net -net hbm_size_bytes_1 [get_bd_pins hbm_size_bytes] [get_bd_pins integration_0/hbm_size_bytes] [get_bd_pins jf_conversion_0/hbm_size_bytes] [get_bd_pins pedestal_0/hbm_size_bytes]
  connect_bd_net -net in_count_threshold_1 [get_bd_pins in_count_threshold] [get_bd_pins spot_finder_0/in_count_threshold]
  connect_bd_net -net in_snr_threshold_1 [get_bd_pins in_snr_threshold] [get_bd_pins spot_finder_0/in_snr_threshold]

  # Restore current instance
  current_bd_instance $oldCurInst
}