// Copyright (2019-2023) Paul Scherrer Institute

#ifndef DEFINITIONS_H
#define DEFINITIONS_H

#define WVL_1A_IN_KEV           12.39854f

#define DELAY_FRAMES_STOP_AND_QUIT 5
#define RAW_MODULE_LINES        (512L)
#define RAW_MODULE_COLS         (1024L)
#define RAW_MODULE_SIZE         (RAW_MODULE_LINES * RAW_MODULE_COLS)

#define CONVERTED_MODULE_LINES  (514L)
#define CONVERTED_MODULE_COLS   (1030L)
#define CONVERTED_MODULE_SIZE   (CONVERTED_MODULE_LINES * CONVERTED_MODULE_COLS)
#define JUNGFRAU_PACKET_SIZE_BYTES  (8192)

#define FPGA_BUFFER_LOCATION_SIZE (RAW_MODULE_SIZE * sizeof(short) * 4) // account for space for data processing results and 32-bit frames

#define MIN_COUNT_TIME_IN_US 5
#define MIN_FRAME_TIME_HALF_SPEED_IN_US 1000
#define MIN_FRAME_TIME_FULL_SPEED_IN_US 470
#define MAX_FRAME_TIME 2000
#define MIN_STORAGE_CELL_DELAY_IN_NS 2100
#define READOUT_TIME_IN_US 20

#define GRPC_MAX_MESSAGE_SIZE (2*1000L*1000L*1000L)
#define MIN_ENERGY 0.1
#define MAX_ENERGY 25.0

#define PEDESTAL_WINDOW_SIZE 128
#define PEDESTAL_WRONG       16384

#define FRAME_TIME_PEDE_G1G2_IN_US (10*1000)

#define SENSOR_THICKNESS_IN_UM 320.0
#define PIXEL_SIZE_IN_UM        75.0
#define PIXEL_SIZE_IN_MM       (PIXEL_SIZE_IN_UM/1000.0)
#define SENSOR_MATERIAL        "Si"

#define GAIN_G0_MULTIPLIER 32
#define GAIN_G1_MULTIPLIER (-1)
#define GAIN_G2_MULTIPLIER (-1)

#define DEFAULT_G0_FACTOR   (41.0)
#define DEFAULT_G1_FACTOR   (-1.439)
#define DEFAULT_G2_FACTOR   (-0.1145)

#define TASK_NO_DATA_STREAM UINT16_MAX

// For FPGA
#define ACTION_TYPE   0x52324158
#define RELEASE_LEVEL 0x004A

#define MODE_CONV                    0x0001L
#define MODE_32BIT                   0x0002L
#define MODE_UNSIGNED                0x0004L
#define MODE_PEDESTAL_G0             0x0010L
#define MODE_PEDESTAL_G1             0x0020L
#define MODE_PEDESTAL_G2             0x0040L

#define STREAM_MERGE_SRC_NONE        0
#define STREAM_MERGE_SRC_100G        1
#define STREAM_MERGE_SRC_4x10G       2
#define STREAM_MERGE_SRC_FRAME_GEN   3

#define PIXEL_OUT_LOST          (INT16_MIN)

#define LOAD_CALIBRATION_DEST_CALIB       0
#define LOAD_CALIBRATION_DEST_INTEGRATION 1
#define LOAD_CALIBRATION_DEST_FRAME_GEN   2

#define HANDLE_START      (UINT16_MAX - 1)
#define HANDLE_END        (UINT16_MAX    )

#define INT_PKT_GEN_DEBUG       0x0
#define INT_PKT_GEN_BUNCHID     0xCACACACACA
#define INT_PKT_GEN_EXPTTIME    10000

#define FPGA_INTEGRATION_BIN_COUNT 1024

#define MAX_MODULES_FPGA  32
#define MAX_FPGA_SUMMATION 256

#define ADU_HISTO_BIN_WIDTH 32
#define ADU_HISTO_BIN_COUNT (65536/ ADU_HISTO_BIN_WIDTH)

#endif //DEFINITIONS_H