// Copyright (2019-2023) Paul Scherrer Institute // SPDX-License-Identifier: GPL-3.0-or-later #include "hls_jfjoch.h" void load_from_hbm(STREAM_512 &data_out, hls::stream &completion_in, hls::stream &completion_out, hls::burst_maxi d_hbm_p0, hls::burst_maxi d_hbm_p1, ap_uint<32> hbm_size) { #pragma HLS INTERFACE ap_ctrl_none port=return #pragma HLS INTERFACE register both axis port=data_out #pragma HLS INTERFACE register both axis port=completion_in #pragma HLS INTERFACE register both axis port=completion_out #pragma HLS INTERFACE register ap_none port=hbm_size #pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8 #pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8 axis_completion cmpl; completion_in >> cmpl; ap_uint<32> offset_hbm_0 = 12 * (hbm_size / 32); ap_uint<32> offset_hbm_1 = 14 * (hbm_size / 32); while (!cmpl.last) { completion_out << cmpl; for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) { #pragma HLS PIPELINE II=1 if (i % 16 == 0) { d_hbm_p0.read_request(offset_hbm_0 + cmpl.handle * RAW_MODULE_SIZE * sizeof(uint16_t) / 32 / 2 + i, 16); d_hbm_p1.read_request(offset_hbm_1 + cmpl.handle * RAW_MODULE_SIZE * sizeof(uint16_t) / 32 / 2 + i, 16); } packet_512_t packet_out; packet_out.data(255, 0) = d_hbm_p0.read(); packet_out.data(511,256) = d_hbm_p1.read(); if (cmpl.packet_mask[i/128] == 0) { for (int i = 0; i < 32; i++) packet_out.data(16*i+15,16*i) = PIXEL_OUT_LOST; } packet_out.keep = UINT64_MAX; packet_out.strb = UINT64_MAX; packet_out.last = (i == (RAW_MODULE_SIZE / 32 * 2 - 1)); data_out << packet_out; } completion_in >> cmpl; } completion_out << cmpl; }