// Copyright (2019-2022) Paul Scherrer Institute
// SPDX-License-Identifier: GPL-3.0-or-later

#ifndef DEFINITIONS_H
#define DEFINITIONS_H

#define WVL_1A_IN_KEV           12.39854f

#define DELAY_FRAMES_STOP_AND_QUIT 5
#define RAW_MODULE_LINES        (512L)
#define RAW_MODULE_COLS         (1024L)
#define RAW_MODULE_SIZE         (RAW_MODULE_LINES * RAW_MODULE_COLS)

#define CONVERTED_MODULE_LINES  (514L)
#define CONVERTED_MODULE_COLS   (1030L)
#define CONVERTED_MODULE_SIZE   (CONVERTED_MODULE_LINES * CONVERTED_MODULE_COLS)
#define JUNGFRAU_PACKET_SIZE_BYTES  (8192)

#define FPGA_BUFFER_LOCATION_SIZE (RAW_MODULE_SIZE * sizeof(short))

#define MIN_COUNT_TIME_IN_US 10
#define MIN_FRAME_TIME_HALF_SPEED_IN_US 1000
#define MIN_FRAME_TIME_FULL_SPEED_IN_US 470
#define MAX_FRAME_TIME 2000
#define MAX_SUMMATION 5000

#define READOUT_TIME_IN_US 20

#define GRPC_MAX_MESSAGE_SIZE (1000L*1000L*1000L)
#define MIN_ENERGY 0.1
#define MAX_ENERGY 25.0

#define PEDESTAL_WINDOW_SIZE 128
#define PEDESTAL_WRONG       16384

#define FRAME_TIME_PEDE_G1G2_IN_US (10*1000)

#define SENSOR_THICKNESS_IN_UM 320.0
#define PIXEL_SIZE_IN_UM        75.0
#define PIXEL_SIZE_IN_MM       (PIXEL_SIZE_IN_UM/1000.0)
#define SENSOR_MATERIAL        "Si"

#define GAIN_G0_MULTIPLIER 32
#define GAIN_G1_MULTIPLIER (-1)
#define GAIN_G2_MULTIPLIER (-1)

#define DEFAULT_G0_FACTOR   (41.0)
#define DEFAULT_G1_FACTOR   (-1.439)
#define DEFAULT_G2_FACTOR   (-0.1145)

// For FPGA
#define ACTION_TYPE   0x52324158
#define RELEASE_LEVEL 0x0036

#define MODE_CONV                    0x0001L
#define MODE_INTERNAL_PACKET_GEN     0x0002L
#define MODE_NONBLOCKING_ON_WR       0x0004L // Don't block acquisition if there is no WR available

#define TASK_NO_DATA_STREAM UINT16_MAX

#define PIXEL_OUT_SATURATION    (INT16_MAX)
#define PIXEL_OUT_LOST          (INT16_MIN)
#define PIXEL_OUT_0xFFFF        (INT16_MIN)
#define PIXEL_OUT_G1_SATURATION (INT16_MIN)
#define PIXEL_OUT_GAINBIT_2     (INT16_MIN)

#define LOAD_CALIBRATION_BRAM_SIZE 1024

// FPGA register map

#define ADDR_CTRL_REGISTER       0x0000
#define ADDR_GIT_SHA1            0x000C
#define ADDR_ACTION_TYPE         0x0010
#define ADDR_RELEASE_LEVEL       0x0014
#define ADDR_HBM_TEMP            0x0018
#define ADDR_HBM_MAX_TEMP        0x001C
#define ADDR_MAX_MODULES_FPGA    0x0020
#define ADDR_MODS_INT_PKT_GEN    0x0024
#define ADDR_STALLS_HOST_LO      0x0028
#define ADDR_STALLS_HOST_HI      0x002C
#define ADDR_STALLS_HBM_LO       0x0030
#define ADDR_STALLS_HBM_HI       0x0034
#define ADDR_FIFO_STATUS         0x0038

#define ADDR_PACKETS_PROC_LO     0x0040
#define ADDR_PACKETS_PROC_HI     0x0044
#define ADDR_PACKETS_ETH_LO      0x0048
#define ADDR_PACKETS_ETH_HI      0x004C
#define ADDR_PACKETS_ICMP_LO     0x0050
#define ADDR_PACKETS_ICMP_HI     0x0054
#define ADDR_PACKETS_UDP_LO      0x0058
#define ADDR_PACKETS_UDP_HI      0x005C
#define ADDR_PACKETS_SLS_LO      0x0060
#define ADDR_PACKETS_SLS_HI      0x0064
#define ADDR_PACKETS_ERR_LEN     0x0068
#define ADDR_PACKETS_ERR_ETH     0x006C

#define ADDR_MAC_ADDR_LO         0x0080
#define ADDR_MAC_ADDR_HI         0x0084
#define ADDR_IPV4_ADDR           0x0088
#define ADDR_NMODULES            0x008C
#define ADDR_DATA_COL_MODE       0x0090
#define ADDR_ONE_OVER_ENERGY     0x0094
#define ADDR_NFRAMES             0x0098
#define ADDR_NSTORAGE_CELLS      0x009C

#define ADDR_MAILBOX_WRDATA      0x00
#define ADDR_MAILBOX_RDDATA      0x08
#define ADDR_MAILBOX_STATUS      0x10
#define ADDR_MAILBOX_SIT         0x18
#define ADDR_MAILBOX_RIT         0x1C

#define MAILBOX_EMPTY            (1 << 0)
#define MAILBOX_FULL             (1 << 1)
#define MAILBOX_STA              (1 << 2)
#define MAILBOX_RTA              (1 << 3)

#define CTRL_REGISTER_IDLE               (1<<1u)

#define HANDLE_START      (UINT32_MAX - 1)
#define HANDLE_SKIP_FRAME (UINT32_MAX - 2)
#define HANDLE_END        (UINT32_MAX    )

#endif //DEFINITIONS_H