# Tools Besides the main services ([`jfjoch_broker`](JFJOCH_BROKER.md), [`jfjoch_writer`](JFJOCH_WRITER.md), [`jfjoch_viewer`](JFJOCH_VIEWER.md)), the repository ships a number of command-line tools. Each prints its own usage when run with `-h` or without arguments. ## Data analysis ### jfjoch_process Offline CLI tool that runs the full crystallographic analysis pipeline (spot finding, indexing, integration, scaling/merging) on a stored HDF5 dataset, producing a `_process.h5` file and, when merging, reflection files. See [jfjoch_process](JFJOCH_PROCESS.md). ### jfjoch_scale Re-scales and merges the already-integrated reflections from one or more `_process.h5` files (no re-integration). Useful to re-merge with a different space group, partiality, resolution limit or reference MTZ, or to combine several runs. See [jfjoch_process](JFJOCH_PROCESS.md). ### jfjoch_extract_hkl Extracts reflections (HKL list) from a Jungfraujoch master file; can sum the same HKL across neighbouring images and compare against an XDS `INTEGRATE.HKL` reference. ## FPGA / PCIe card management ### jfjoch_pcie_status Prints detailed status information about the card. Safe to run during data collection: ``` ./jfjoch_pcie_status /dev/jfjoch0 ``` ### jfjoch_pcie_net_cfg Reads and modifies the network configuration of the card's interfaces: ``` jfjoch_pcie_net_cfg Read configuration for all network interfaces of a device jfjoch_pcie_net_cfg |fgen Read configuration for a particular network interface / internal frame generator jfjoch_pcie_net_cfg |fgen ipv4 Set IPv4 address for a particular network interface / internal frame generator jfjoch_pcie_net_cfg |fgen direct 0|1 Set direct mode for a particular network interface / internal frame generator jfjoch_pcie_net_cfg |fgen clear Clear Ethernet counters for a particular network interface / internal frame generator ``` ### jfjoch_pcie_clear_net_counters Resets the card's Ethernet, UDP and ICMP packet counters (which otherwise run from power-on): ``` ./jfjoch_pcie_clear_net_counters /dev/jfjoch0 ``` ### jfjoch_pcie_read_register Reads raw Jungfraujoch FPGA registers. ## Testing, benchmarking and simulation ### jfjoch_udp_simulator UDP packet simulator used to test the Jungfraujoch FPGA receiver. ### jfjoch_fpga_test Exercises and benchmarks the FPGA data path and receiver. With `-H` it runs the high-level synthesis C model on the CPU, so no FPGA device is required. ### jfjoch_lite_perf_test Performance test of the lite (CPU/GPU) analysis path — indexing, integration and optional file writing. ### jfjoch_hdf5_test Tests single-threaded HDF5 writer performance. ### jfjoch_azint_test Tests the azimuthal integration code on synthetic data. ### jfjoch_simplon_test Minimal test client for a DECTRIS SIMPLON detector API.