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mx/Jungfraujoch
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Code Issues Pull Requests 1 Actions Packages Projects Releases 55 Wiki Activity
671 Commits 73 Branches 140 Tags
7d48c5f2cde3c040fdfd8f7cb183b6a2a12bc1b2
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5 Commits

Author SHA1 Message Date
leonarski_f 31304553be FPGA: sls_detector had hardcoded max module number -> fixed 2023-11-01 13:28:17 +01:00
leonarski_f 4011c4541d HLS: frames inside HLS logic are counted from 0, even if JUNGFRAU counts them from 1 2023-10-26 19:42:15 +02:00
leonarski_f 16bbf54f2a Remove open source license (for now) 2023-09-15 10:47:21 +02:00
leonarski_f 309dabd32b FPGA: Use dedicated struct for address exchange 2023-09-11 11:19:05 +02:00
leonarski_f 7a98766304 FPGA: Split receiver and FPGA design directories 2023-06-07 21:21:22 +02:00
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