From e041e7bf2646a4da3e8d6e9965f81a1216c8eead Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Sun, 17 Sep 2023 19:41:04 +0200 Subject: [PATCH] Revert "FPGA: double HBM latency & number of outstanding operations" This reverts commit 0f903607a028e1827dd965b13f87f913cc81d6b1. --- fpga/hls/load_from_hbm.cpp | 4 ++-- fpga/hls/save_to_hbm.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/fpga/hls/load_from_hbm.cpp b/fpga/hls/load_from_hbm.cpp index d81190b9..7e366b1c 100644 --- a/fpga/hls/load_from_hbm.cpp +++ b/fpga/hls/load_from_hbm.cpp @@ -20,9 +20,9 @@ void load_from_hbm(STREAM_512 &data_in, #pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes #pragma HLS INTERFACE mode=m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \ - max_read_burst_length=16 max_write_burst_length=2 latency=240 num_write_outstanding=2 num_read_outstanding=16 + max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8 #pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ - max_read_burst_length=16 max_write_burst_length=2 latency=240 num_write_outstanding=2 num_read_outstanding=16 + max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8 packet_512_t packet; data_in >> packet; diff --git a/fpga/hls/save_to_hbm.cpp b/fpga/hls/save_to_hbm.cpp index 88984aca..05cd0469 100644 --- a/fpga/hls/save_to_hbm.cpp +++ b/fpga/hls/save_to_hbm.cpp @@ -20,9 +20,9 @@ void save_to_hbm(STREAM_512 &data_in, #pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes #pragma HLS INTERFACE mode=m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \ - max_read_burst_length=2 max_write_burst_length=16 latency=240 num_write_outstanding=16 num_read_outstanding=2 + max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 #pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ - max_read_burst_length=2 max_write_burst_length=16 latency=240 num_write_outstanding=16 num_read_outstanding=2 + max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 axis_completion cmpl[MAX_MODULES_FPGA*2];