v1.0.0-rc.31
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@@ -1992,18 +1992,24 @@ TEST_CASE("HLS_C_Simulation_count_sat_and_err_pixels", "[FPGA][Full]") {
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DiffractionExperiment x((DetectorGeometry(nmodules)));
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x.Mode(DetectorMode::Raw);
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x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0);
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x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0).PixelSigned(true);
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HLSSimulatedDevice test(0, 64);
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std::vector<uint16_t> v(RAW_MODULE_SIZE, 0);
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v[567] = 0xc000;
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v[RAW_MODULE_COLS * 511 + 255] = 0xc000;
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v[RAW_MODULE_COLS * 250 + 233] = 0xffff;
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v[0] = 0xffff;
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v[RAW_MODULE_SIZE-1] = 0xffff;
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std::vector<int16_t> v(RAW_MODULE_SIZE, 0);
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v[567] = INT16_MAX;
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v[RAW_MODULE_COLS * 511 + 255] = INT16_MAX;
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v[RAW_MODULE_COLS * 250 + 233] = INT16_MIN;
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v[0] = INT16_MIN;
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v[RAW_MODULE_SIZE-1] = INT16_MIN;
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v[23] = 23;
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v[24] = -24;
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v[25] = 27;
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v[1500] = -25;
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v[1501] = 30;
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v[1502] = INT16_MIN + 25;
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for (int m = 0; m < x.GetModulesNum(); m++)
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test.SetInternalGeneratorFrame(v.data(), m);
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test.SetInternalGeneratorFrame((uint16_t *) v.data(), m);
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REQUIRE_NOTHROW(test.StartAction(x));
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@@ -2014,6 +2020,8 @@ TEST_CASE("HLS_C_Simulation_count_sat_and_err_pixels", "[FPGA][Full]") {
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for (int m = 0; m < nmodules; m++) {
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CHECK(test.GetDeviceOutput(image, m)->module_statistics.saturated_pixels == 2);
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CHECK(test.GetDeviceOutput(image, m)->module_statistics.err_pixels == 3);
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CHECK(test.GetDeviceOutput(image, m)->module_statistics.max_value == 30);
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CHECK(test.GetDeviceOutput(image, m)->module_statistics.load_calibration_destination == INT16_MIN + 25);
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}
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}
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}
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