From d66b6b949dfede2593bc0458f6504311055687bb Mon Sep 17 00:00:00 2001 From: leonarski_f Date: Sat, 16 Dec 2023 09:20:46 +0100 Subject: [PATCH] Fix spot finding + fix FPGA network LEDs behavior --- fpga/CMakeLists.txt | 2 +- fpga/README.md | 19 +++++++++++++++++-- fpga/hdl/eth_4x10g_leds.v | 15 +++++++++++++++ fpga/hls/spot_finder.cpp | 4 +++- fpga/scripts/bd_pcie.tcl | 17 +++++++++++++---- fpga/scripts/build_pcie_design.tcl | 1 + fpga/scripts/mac_100g_pcie.tcl | 16 ++++------------ fpga/scripts/mac_4x10g.tcl | 21 ++++++++++++++++++++- fpga/xdc/pcie_u55c.xdc | 6 ++++-- image_analysis/StrongPixelSet.cpp | 15 ++++++++++++++- image_analysis/StrongPixelSet.h | 5 +++++ receiver/JFJochReceiver.cpp | 4 ++-- receiver/JFJochReceiverService.cpp | 2 ++ receiver/JFJochReceiverTest.cpp | 2 +- 14 files changed, 102 insertions(+), 27 deletions(-) create mode 100644 fpga/hdl/eth_4x10g_leds.v diff --git a/fpga/CMakeLists.txt b/fpga/CMakeLists.txt index 0a707e7d..49287ced 100644 --- a/fpga/CMakeLists.txt +++ b/fpga/CMakeLists.txt @@ -21,7 +21,7 @@ ADD_SUBDIRECTORY(host_library) IF(VIVADO_HLS AND VIVADO) ADD_CUSTOM_COMMAND(OUTPUT action/hw/hdl/action_config.v COMMAND ${CMAKE_COMMAND} -E env SRC_DIR=${CMAKE_CURRENT_SOURCE_DIR} HLS_IP_DIR=${CMAKE_CURRENT_BINARY_DIR}/action/ip/hls bash ${CMAKE_CURRENT_SOURCE_DIR}/scripts/setup_action.sh - DEPENDS hls hdl/action_config.v hdl/gen_xdma_descriptor.v scripts/bd_pcie.tcl scripts/jfjoch.tcl scripts/network_stack.tcl scripts/hbm_u55c.tcl scripts/mac_100g_pcie.tcl scripts/pcie_dma.tcl scripts/setup_action.sh + DEPENDS hls hdl/action_config.v hdl/gen_xdma_descriptor.v hdl/eth_4x10g_leds.v scripts/bd_pcie.tcl scripts/jfjoch.tcl scripts/network_stack.tcl scripts/hbm_u55c.tcl scripts/mac_100g_pcie.tcl scripts/pcie_dma.tcl scripts/setup_action.sh ) ADD_CUSTOM_TARGET(action_pcie DEPENDS action/hw/hdl/action_config.v hls diff --git a/fpga/README.md b/fpga/README.md index a174869f..d3a14b60 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -1,11 +1,26 @@ # FPGA Smart Network Interface Card ## Hardware -Currently supported FPGA is only **Xilinx Alveo U55C**. +Currently supported FPGA is only **Xilinx Alveo U55C**. + +See AMD/Xilinx webpage for [card user guide (UG1469)](https://docs.xilinx.com/r/en-US/ug1469-alveo-u55c). +According to the user guide: +``` +Alveo data center accelerator cards are designed to be installed into a data center server, where controlled air flow provides direct cooling. +``` Card needs to be placed in PCI Express (PCIe) Gen4 x8 slot, though mechanically slot has to accommodate x16 card. There is no need to connect additional power cable, as power of the card is not exceeding 75 W load available from PCIe edge connector. -Current power estimation is about 30 W when idle and 40 W in operation. +Current power estimation is about 30 W when idle and 45 W in operation. The card has built-in protection, which will cut power to the card if HBM temperature is above 120°C. + +Card is equipped with two network connectors: + +| Port | Location | Network type | Transceiver type | LED | +|-------|--------------------------------|--------------|------------------|------------------------------------------| +| QSFP0 | Upper port on the PCIe bracket | 100G | QSFP28 | green = OK | +| QSFP1 | Lower port on the PCIe bracket | 4x10G | QSFP+ | green = all OK, yellow = at least one OK | + +See [host library documentation](pcie_driver/README.md) for details of network. ## Content of directories diff --git a/fpga/hdl/eth_4x10g_leds.v b/fpga/hdl/eth_4x10g_leds.v new file mode 100644 index 00000000..20c41986 --- /dev/null +++ b/fpga/hdl/eth_4x10g_leds.v @@ -0,0 +1,15 @@ +// Copyright (2019-2023) Paul Scherrer Institute + +`timescale 1ns / 1ps + +module eth_4x10g_leds( + input stat_rx_status_0, + input stat_rx_status_1, + input stat_rx_status_2, + input stat_rx_status_3, + output led_green, + output led_yellow +); + assign led_green = stat_rx_status_0 && stat_rx_status_1 && stat_rx_status_2 && stat_rx_status_3; + assign led_yellow = (stat_rx_status_0 || stat_rx_status_1 || stat_rx_status_2 || stat_rx_status_3) && !led_green; +endmodule diff --git a/fpga/hls/spot_finder.cpp b/fpga/hls/spot_finder.cpp index b5f96f46..9dcb6a68 100644 --- a/fpga/hls/spot_finder.cpp +++ b/fpga/hls/spot_finder.cpp @@ -222,11 +222,13 @@ void spot_finder_apply_threshold(hls::stream &data_in, data_out << packet_768_t{.data = packet_in.data, .user = packet_in.user, .last = packet_in.last}; ap_int<24> data_unpacked[32]; unpack32(packet_in.data, data_unpacked); - ap_uint<32> strong_pixel = spot_finder_count_threshold(data_unpacked, count_threshold) & spot_finder_snr_threshold(data_unpacked, snr_threshold_2, sum[i % 32], sum2[i % 32], valid[i % 32]); + if ((snr_threshold == 0) && (count_threshold <= 0)) + strong_pixel = 0; + strong_pixel_out << ap_axiu<32,1,1,1>{.data = strong_pixel, .user = 0}; strong_pixel_count += count_pixels(strong_pixel); data_in >> packet_in; diff --git a/fpga/scripts/bd_pcie.tcl b/fpga/scripts/bd_pcie.tcl index bb2fb937..b5477cc2 100644 --- a/fpga/scripts/bd_pcie.tcl +++ b/fpga/scripts/bd_pcie.tcl @@ -206,6 +206,7 @@ if { $bCheckModules == 1 } { set list_check_mods "\ action_config\ gen_xdma_descriptor\ +eth_4x10g_leds\ " set list_mods_missing "" @@ -293,9 +294,14 @@ proc create_root_design { parentCell } { # Create ports - set hbm_cattrip [ create_bd_port -dir O -from 0 -to 0 hbm_cattrip ] + set hbm_cattrip [ create_bd_port -dir O hbm_cattrip ] set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] - set qsfp0_led_conn [ create_bd_port -dir O -from 0 -to 0 qsfp0_led_conn ] + set qsfp0_led_conn_green [ create_bd_port -dir O qsfp0_led_conn_green ] + set qsfp0_led_conn_yellow [ create_bd_port -dir O qsfp0_led_conn_yellow ] + set qsfp0_led_busy [ create_bd_port -dir O qsfp0_led_busy ] + set qsfp1_led_conn_green [ create_bd_port -dir O qsfp1_led_conn_green ] + set qsfp1_led_conn_yellow [ create_bd_port -dir O qsfp1_led_conn_yellow ] + set qsfp1_led_busy [ create_bd_port -dir O qsfp1_led_busy ] set satellite_gpio_0 [ create_bd_port -dir I -from 3 -to 0 -type intr satellite_gpio_0 ] set_property -dict [ list \ CONFIG.PortWidth {4} \ @@ -464,7 +470,10 @@ proc create_root_design { parentCell } { connect_bd_net -net hbm_infrastructure_hbm_temperature_0 [get_bd_pins cms_subsystem_0/hbm_temp_1] [get_bd_pins hbm_infrastructure/hbm_temperature_0] connect_bd_net -net hbm_infrastructure_hbm_temperature_1 [get_bd_pins cms_subsystem_0/hbm_temp_2] [get_bd_pins hbm_infrastructure/hbm_temperature_1] connect_bd_net -net jungfraujoch_Interrupt_0 [get_bd_pins jungfraujoch/Interrupt_0] [get_bd_pins xlconcat_irq/In1] - connect_bd_net -net mac_100g_stat_rx_aligned_n [get_bd_ports qsfp0_led_conn] [get_bd_pins mac_100g/stat_rx_aligned_n] + connect_bd_net -net mac_100g_led_green [get_bd_ports qsfp0_led_conn_green] [get_bd_pins mac_100g/led_green] + connect_bd_net -net mac_100g_led_yellow [get_bd_ports qsfp0_led_conn_yellow] [get_bd_pins mac_100g/led_yellow] + connect_bd_net -net mac_4x10g_led_green [get_bd_ports qsfp1_led_conn_green] [get_bd_pins mac_4x10g/led_green] + connect_bd_net -net mac_4x10g_led_yellow [get_bd_ports qsfp1_led_conn_yellow] [get_bd_pins mac_4x10g/led_yellow] connect_bd_net -net net_refclk50 [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins cms_subsystem_0/aclk_ctrl] [get_bd_pins mac_4x10g/refclk50] [get_bd_pins proc_sys_reset_refclk/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk2] connect_bd_net -net net_refclk100 [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins hbm_infrastructure/refclk100] [get_bd_pins mac_100g/refclk100] [get_bd_pins smartconnect_0/aclk1] connect_bd_net -net net_refclk200 [get_bd_pins clk_wiz_0/clk_out3] [get_bd_pins hbm_infrastructure/axi_clk] [get_bd_pins jungfraujoch/axi_clk] [get_bd_pins mac_100g/axiclk] [get_bd_pins mac_4x10g/m_axis_aclk] [get_bd_pins pcie_dma_0/refclk200] [get_bd_pins smartconnect_0/aclk] @@ -477,7 +486,7 @@ proc create_root_design { parentCell } { connect_bd_net -net satellite_gpio_0_1 [get_bd_ports satellite_gpio_0] [get_bd_pins cms_subsystem_0/satellite_gpio] connect_bd_net -net xlconcat_0_dout [get_bd_pins pcie_dma_0/usr_irq_req] [get_bd_pins xlconcat_irq/dout] connect_bd_net -net xlconcat_irq_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_intc/dout] - connect_bd_net -net zero_dout [get_bd_pins axi_quad_spi_0/usrcclkts] [get_bd_pins zero/dout] + connect_bd_net -net zero_dout [get_bd_pins axi_quad_spi_0/usrcclkts] [get_bd_pins zero/dout] [get_bd_ports qsfp0_led_busy] [get_bd_ports qsfp1_led_busy] # Create address segments assign_bd_address -offset 0x00010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch/action_config_0/s_axi/reg0] -force diff --git a/fpga/scripts/build_pcie_design.tcl b/fpga/scripts/build_pcie_design.tcl index f71992f8..cc01b825 100644 --- a/fpga/scripts/build_pcie_design.tcl +++ b/fpga/scripts/build_pcie_design.tcl @@ -21,6 +21,7 @@ set source_set [get_filesets sources_1] set hdl_files [list \ [file normalize "action/hw/hdl/action_config.v"] \ [file normalize "action/hw/hdl/gen_xdma_descriptor.v"] \ + [file normalize "action/hw/hdl/eth_4x10g_leds.v"] \ ] if { [llength $hdl_files] > 0 } { diff --git a/fpga/scripts/mac_100g_pcie.tcl b/fpga/scripts/mac_100g_pcie.tcl index 27d65111..5de2fcf7 100644 --- a/fpga/scripts/mac_100g_pcie.tcl +++ b/fpga/scripts/mac_100g_pcie.tcl @@ -51,7 +51,8 @@ proc create_hier_cell_mac_100g { parentCell nameHier } { create_bd_pin -dir I -type clk axiclk create_bd_pin -dir I -type clk refclk100 create_bd_pin -dir I -type rst resetn - create_bd_pin -dir O -from 0 -to 0 stat_rx_aligned_n + create_bd_pin -dir O led_green + create_bd_pin -dir O led_yellow # Create instance: axis_data_fifo_rx_0, and set properties set axis_data_fifo_rx_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_rx_0 ] @@ -130,14 +131,6 @@ proc create_hier_cell_mac_100g { parentCell nameHier } { CONFIG.LOGO_FILE {data/sym_notgate.png} \ ] $util_vector_logic_1 - # Create instance: util_vector_logic_2, and set properties - set util_vector_logic_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_2 ] - set_property -dict [ list \ - CONFIG.C_OPERATION {not} \ - CONFIG.C_SIZE {1} \ - CONFIG.LOGO_FILE {data/sym_notgate.png} \ - ] $util_vector_logic_2 - # Create instance: zero_0, and set properties set zero_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zero_0 ] set_property -dict [ list \ @@ -161,14 +154,13 @@ proc create_hier_cell_mac_100g { parentCell nameHier } { connect_bd_net -net ap_rst_n_1 [get_bd_pins ap_rst_n] [get_bd_pins util_vector_logic_0/Op1] connect_bd_net -net axi_clk_net [get_bd_pins axiclk] [get_bd_pins axis_data_fifo_rx_0/m_axis_aclk] [get_bd_pins axis_data_fifo_rx_1/s_axis_aclk] [get_bd_pins axis_data_fifo_tx/s_axis_aclk] [get_bd_pins axis_register_slice_rx_0/aclk] [get_bd_pins axis_register_slice_rx_1/aclk] [get_bd_pins axis_register_slice_tx/aclk] connect_bd_net -net cmac_usplus_0_gt_txusrclk2 [get_bd_pins axis_data_fifo_rx_0/s_axis_aclk] [get_bd_pins axis_data_fifo_tx/m_axis_aclk] [get_bd_pins cmac_usplus_0/gt_txusrclk2] [get_bd_pins cmac_usplus_0/rx_clk] - connect_bd_net -net cmac_usplus_0_stat_rx_aligned [get_bd_pins cmac_usplus_0/stat_rx_aligned] [get_bd_pins util_vector_logic_2/Op1] + connect_bd_net -net cmac_usplus_0_stat_rx_status [get_bd_pins cmac_usplus_0/stat_rx_status] [get_bd_pins led_green] connect_bd_net -net cmac_usplus_0_usr_rx_reset [get_bd_pins cmac_usplus_0/usr_rx_reset] [get_bd_pins util_vector_logic_1/Op1] connect_bd_net -net init_clk_1 [get_bd_pins refclk100] [get_bd_pins cmac_usplus_0/init_clk] [get_bd_pins cmac_usplus_0/s_axi_aclk] connect_bd_net -net resetn_1 [get_bd_pins resetn] [get_bd_pins axis_data_fifo_rx_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_tx/s_axis_aresetn] [get_bd_pins axis_register_slice_rx_0/aresetn] [get_bd_pins axis_register_slice_rx_1/aresetn] [get_bd_pins axis_register_slice_tx/aresetn] connect_bd_net -net util_vector_logic_0_Res [get_bd_pins cmac_usplus_0/s_axi_sreset] [get_bd_pins cmac_usplus_0/sys_reset] [get_bd_pins util_vector_logic_0/Res] connect_bd_net -net util_vector_logic_1_Res [get_bd_pins axis_data_fifo_rx_0/s_axis_aresetn] [get_bd_pins util_vector_logic_1/Res] - connect_bd_net -net util_vector_logic_2_Res [get_bd_pins stat_rx_aligned_n] [get_bd_pins util_vector_logic_2/Res] - connect_bd_net -net zero_0_dout [get_bd_pins cmac_usplus_0/core_drp_reset] [get_bd_pins cmac_usplus_0/core_rx_reset] [get_bd_pins cmac_usplus_0/core_tx_reset] [get_bd_pins cmac_usplus_0/drp_clk] [get_bd_pins zero_0/dout] + connect_bd_net -net zero_0_dout [get_bd_pins cmac_usplus_0/core_drp_reset] [get_bd_pins cmac_usplus_0/core_rx_reset] [get_bd_pins cmac_usplus_0/core_tx_reset] [get_bd_pins cmac_usplus_0/drp_clk] [get_bd_pins zero_0/dout] [get_bd_pins led_yellow] # Restore current instance current_bd_instance $oldCurInst diff --git a/fpga/scripts/mac_4x10g.tcl b/fpga/scripts/mac_4x10g.tcl index 95b8b561..118a83a8 100644 --- a/fpga/scripts/mac_4x10g.tcl +++ b/fpga/scripts/mac_4x10g.tcl @@ -46,6 +46,8 @@ proc create_hier_cell_mac_4x10g { parentCell nameHier } { # Create pins create_bd_pin -dir I -type rst axi_aresetn + create_bd_pin -dir O led_green + create_bd_pin -dir O led_yellow create_bd_pin -dir I -type clk m_axis_aclk create_bd_pin -dir I -type clk refclk50 @@ -93,6 +95,17 @@ proc create_hier_cell_mac_4x10g { parentCell nameHier } { CONFIG.S03_FIFO_MODE {1} \ ] $axis_interconnect_0 + # Create instance: eth_4x10g_leds_0, and set properties + set block_name eth_4x10g_leds + set block_cell_name eth_4x10g_leds_0 + if { [catch {set eth_4x10g_leds_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $eth_4x10g_leds_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + # Create instance: smartconnect_0, and set properties set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] set_property -dict [ list \ @@ -191,6 +204,8 @@ proc create_hier_cell_mac_4x10g { parentCell nameHier } { # Create port connections connect_bd_net -net dclk_1 [get_bd_pins refclk50] [get_bd_pins smartconnect_0/aclk] [get_bd_pins xxv_ethernet_0/dclk] [get_bd_pins xxv_ethernet_0/s_axi_aclk_0] [get_bd_pins xxv_ethernet_0/s_axi_aclk_1] [get_bd_pins xxv_ethernet_0/s_axi_aclk_2] [get_bd_pins xxv_ethernet_0/s_axi_aclk_3] + connect_bd_net -net eth_4x10g_leds_0_led_green [get_bd_pins led_green] [get_bd_pins eth_4x10g_leds_0/led_green] + connect_bd_net -net eth_4x10g_leds_0_led_yellow [get_bd_pins led_yellow] [get_bd_pins eth_4x10g_leds_0/led_yellow] connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins axis_interconnect_0/ACLK] [get_bd_pins axis_interconnect_0/M00_AXIS_ACLK] connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins axi_aresetn] [get_bd_pins axis_interconnect_0/ARESETN] [get_bd_pins axis_interconnect_0/M00_AXIS_ARESETN] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins util_vector_logic_4/Op1] [get_bd_pins xxv_ethernet_0/s_axi_aresetn_0] [get_bd_pins xxv_ethernet_0/s_axi_aresetn_1] [get_bd_pins xxv_ethernet_0/s_axi_aresetn_2] [get_bd_pins xxv_ethernet_0/s_axi_aresetn_3] connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_4/Res] [get_bd_pins xxv_ethernet_0/sys_reset] @@ -199,6 +214,10 @@ proc create_hier_cell_mac_4x10g { parentCell nameHier } { connect_bd_net -net util_vector_logic_2_Res [get_bd_pins axis_dwidth_converter_2/aresetn] [get_bd_pins axis_interconnect_0/S02_AXIS_ARESETN] [get_bd_pins util_vector_logic_2/Res] connect_bd_net -net util_vector_logic_3_Res [get_bd_pins axis_dwidth_converter_3/aresetn] [get_bd_pins axis_interconnect_0/S03_AXIS_ARESETN] [get_bd_pins util_vector_logic_3/Res] connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] [get_bd_pins xxv_ethernet_0/rxoutclksel_in_0] [get_bd_pins xxv_ethernet_0/rxoutclksel_in_1] [get_bd_pins xxv_ethernet_0/rxoutclksel_in_2] [get_bd_pins xxv_ethernet_0/rxoutclksel_in_3] [get_bd_pins xxv_ethernet_0/txoutclksel_in_0] [get_bd_pins xxv_ethernet_0/txoutclksel_in_1] [get_bd_pins xxv_ethernet_0/txoutclksel_in_2] [get_bd_pins xxv_ethernet_0/txoutclksel_in_3] + connect_bd_net -net xxv_ethernet_0_stat_rx_status_0 [get_bd_pins eth_4x10g_leds_0/stat_rx_status_0] [get_bd_pins xxv_ethernet_0/stat_rx_status_0] + connect_bd_net -net xxv_ethernet_0_stat_rx_status_1 [get_bd_pins eth_4x10g_leds_0/stat_rx_status_1] [get_bd_pins xxv_ethernet_0/stat_rx_status_1] + connect_bd_net -net xxv_ethernet_0_stat_rx_status_2 [get_bd_pins eth_4x10g_leds_0/stat_rx_status_2] [get_bd_pins xxv_ethernet_0/stat_rx_status_2] + connect_bd_net -net xxv_ethernet_0_stat_rx_status_3 [get_bd_pins eth_4x10g_leds_0/stat_rx_status_3] [get_bd_pins xxv_ethernet_0/stat_rx_status_3] connect_bd_net -net xxv_ethernet_0_tx_clk_out_0 [get_bd_pins axis_dwidth_converter_0/aclk] [get_bd_pins axis_interconnect_0/S00_AXIS_ACLK] [get_bd_pins xxv_ethernet_0/rx_core_clk_0] [get_bd_pins xxv_ethernet_0/tx_clk_out_0] connect_bd_net -net xxv_ethernet_0_tx_clk_out_1 [get_bd_pins axis_dwidth_converter_1/aclk] [get_bd_pins axis_interconnect_0/S01_AXIS_ACLK] [get_bd_pins xxv_ethernet_0/rx_core_clk_1] [get_bd_pins xxv_ethernet_0/tx_clk_out_1] connect_bd_net -net xxv_ethernet_0_tx_clk_out_2 [get_bd_pins axis_dwidth_converter_2/aclk] [get_bd_pins axis_interconnect_0/S02_AXIS_ACLK] [get_bd_pins xxv_ethernet_0/rx_core_clk_2] [get_bd_pins xxv_ethernet_0/tx_clk_out_2] @@ -211,4 +230,4 @@ proc create_hier_cell_mac_4x10g { parentCell nameHier } { # Restore current instance current_bd_instance $oldCurInst -} \ No newline at end of file +} diff --git a/fpga/xdc/pcie_u55c.xdc b/fpga/xdc/pcie_u55c.xdc index ed06066d..78a561b0 100644 --- a/fpga/xdc/pcie_u55c.xdc +++ b/fpga/xdc/pcie_u55c.xdc @@ -67,11 +67,13 @@ set_property PACKAGE_PIN BK10 [get_ports {ref100_clk_p}] set_property IOSTANDARD LVDS [get_ports {ref100_clk_p}] ## User LEDs -set_property PACKAGE_PIN BK11 [get_ports {qsfp0_led_conn}] +set_property PACKAGE_PIN BK11 [get_ports {qsfp0_led_conn_green}] +set_property PACKAGE_PIN BJ11 [get_ports {qsfp0_led_conn_yellow}] set_property PACKAGE_PIN BL13 [get_ports {qsfp0_led_busy}] set_property IOSTANDARD LVCMOS18 [get_ports {qsfp0_led_*}] -set_property PACKAGE_PIN BK15 [get_ports {qsfp1_led_conn}] +set_property PACKAGE_PIN BK15 [get_ports {qsfp1_led_conn_green}] +set_property PACKAGE_PIN BL12 [get_ports {qsfp1_led_conn_yellow}] set_property PACKAGE_PIN BK14 [get_ports {qsfp1_led_busy}] set_property IOSTANDARD LVCMOS18 [get_ports {qsfp1_led_*}] diff --git a/image_analysis/StrongPixelSet.cpp b/image_analysis/StrongPixelSet.cpp index aeda1181..ea9d73bf 100644 --- a/image_analysis/StrongPixelSet.cpp +++ b/image_analysis/StrongPixelSet.cpp @@ -7,7 +7,8 @@ StrongPixelSet::StrongPixelSet(const DiffractionExperiment &experiment) : xpixel(experiment.GetXPixelsNum()), ypixel(experiment.GetYPixelsNum()), - strong_pixel_vector(experiment.GetPixelsNum(), false) { + strong_pixel_vector(experiment.GetPixelsNum(), false), + strong_pixel_count(0) { } void StrongPixelSet::AddStrongPixel(uint16_t col, uint16_t line, int32_t photons) { @@ -128,6 +129,14 @@ size_t StrongPixelSet::Common(const StrongPixelSet &set) const { void StrongPixelSet::ReadFPGAOutput(const DiffractionExperiment& experiment, const DeviceOutput &output, uint16_t module) { + strong_pixel_count += output.spot_finding_result.strong_pixel_count; + + // Too many strong pixels will kill performance in data processing, so protection is needed + // Also if there are no strong pixels, there is no point in looking for them + if ((output.spot_finding_result.strong_pixel_count == 0) || + (output.spot_finding_result.strong_pixel_count > max_strong_pixels_fpga)) + return; + auto out_ptr = (uint32_t *) output.spot_finding_result.strong_pixel; for (int i = 0; i < RAW_MODULE_SIZE / (8 * sizeof(out_ptr[0])); i++) { if (out_ptr[i]) { @@ -141,3 +150,7 @@ void StrongPixelSet::ReadFPGAOutput(const DiffractionExperiment& experiment, } } } + +uint32_t StrongPixelSet::GetStrongPixelCount() const { + return strong_pixel_count; +} diff --git a/image_analysis/StrongPixelSet.h b/image_analysis/StrongPixelSet.h index 16ffe885..042eb2d0 100644 --- a/image_analysis/StrongPixelSet.h +++ b/image_analysis/StrongPixelSet.h @@ -24,9 +24,13 @@ inline uint16_t col_from_strong_pixel(uint32_t strong_pixel) { } class StrongPixelSet { + static const constexpr uint32_t max_strong_pixels_fpga = 4096; std::unordered_map strong_pixel_map; uint32_t xpixel; uint32_t ypixel; + + uint32_t strong_pixel_count; + std::vector strong_pixel_vector; void AddNeighbor(DiffractionSpot &spot, uint16_t col, uint16_t line); DiffractionSpot BuildSpot(std::unordered_map::iterator &it_frames); @@ -38,6 +42,7 @@ public: void AddStrongPixel(uint16_t col, uint16_t line, int32_t photons = 1); void FindSpots(const DiffractionExperiment &experiment, const SpotFindingSettings &settings, std::vector &spots); size_t Common(const StrongPixelSet &set) const; + uint32_t GetStrongPixelCount() const; }; diff --git a/receiver/JFJochReceiver.cpp b/receiver/JFJochReceiver.cpp index be861087..2c900bca 100644 --- a/receiver/JFJochReceiver.cpp +++ b/receiver/JFJochReceiver.cpp @@ -327,8 +327,8 @@ void JFJochReceiver::FrameTransformationThread() { if (rad_int_profile_image) rad_int_profile_image->Add(*output); - //if (find_spots) - // strong_pixel_set.ReadFPGAOutput(experiment, *output, m); + if (find_spots) + strong_pixel_set.ReadFPGAOutput(experiment, *output, m); } else src = acquisition_device[d].GetErrorFrameBuffer(); diff --git a/receiver/JFJochReceiverService.cpp b/receiver/JFJochReceiverService.cpp index 870d3dc2..9ce19180 100644 --- a/receiver/JFJochReceiverService.cpp +++ b/receiver/JFJochReceiverService.cpp @@ -117,10 +117,12 @@ JFJochReceiverOutput JFJochReceiverService::Stop() { void JFJochReceiverService::SetSpotFindingSettings(const SpotFindingSettings &settings) { try { std::unique_lock ul(state_mutex); + DiffractionExperiment::CheckDataProcessingSettings(settings); data_processing_settings = settings; if (state != ReceiverState::Idle) receiver->SetSpotFindingSettings(settings); } catch (std::exception &e) { + logger.ErrorException(e); throw; } } diff --git a/receiver/JFJochReceiverTest.cpp b/receiver/JFJochReceiverTest.cpp index ecb9989a..52460e94 100644 --- a/receiver/JFJochReceiverTest.cpp +++ b/receiver/JFJochReceiverTest.cpp @@ -19,7 +19,7 @@ JFJochReceiverOutput RunJFJochReceiverTest(AcquisitionDeviceGroup &aq_devices, I JFJochReceiverService service(aq_devices, logger, pusher); service.PreviewPublisher(in_preview_writer).NumThreads(nthreads).NUMAPolicy(numa_policy); - SpotFindingSettings settings; + SpotFindingSettings settings = DiffractionExperiment::DefaultDataProcessingSettings(); settings.signal_to_noise_threshold = 2.5; settings.photon_count_threshold = 5; settings.min_pix_per_spot = 3;