FPGA: Internal packet generator uses external memory to store image, and this memory is accessible via PCIe BAR
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@@ -41,7 +41,7 @@ HLSSimulatedDevice::HLSSimulatedDevice(uint16_t data_stream, size_t in_frame_buf
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MapBuffersStandard(in_frame_buffer_size_modules,
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(3 + 3 * 16) * max_modules + 2, numa_node);
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auto in_mem_location32 = (uint32_t *) in_mem_location;
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auto in_mem_location32 = (uint32_t *) calibration_addr_bram;
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for (int i = 0; i < max_modules * (3 + 3 * 16) + 2; i++) {
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in_mem_location32[2 * i ] = ((uint64_t) buffer_device[i]) & UINT32_MAX;
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@@ -51,6 +51,8 @@ HLSSimulatedDevice::HLSSimulatedDevice(uint16_t data_stream, size_t in_frame_buf
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for (auto &i: hbm_memory)
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// i.resize(SIZE_OF_HBM_BLOCK_IN_BYTES);
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i.resize(32*1024*1024); // only 32 MiB instead of 256 MiB per HBM interface (should be more than enough for all the tests anyway)
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internal_packet_generator_uram.resize(RAW_MODULE_SIZE * sizeof(uint16_t) / 512 * 8);
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}
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void HLSSimulatedDevice::CreateFinalPacket(const DiffractionExperiment& experiment) {
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@@ -286,10 +288,11 @@ void HLSSimulatedDevice::HLSMainThread() {
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// Load external calibration
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hls_cores.emplace_back([&] { load_calibration(raw1, raw2, datamover_in.GetCtrlStream(), datamover_in.GetDataStream(),
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in_mem_location); });
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calibration_addr_bram); });
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// Generate internal packets
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hls_cores.emplace_back([&] { internal_packet_generator(raw2, raw3, addr1, addr2, cancel_data_collection); });
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hls_cores.emplace_back([&] { internal_packet_generator(raw2, raw3, addr1, addr2, internal_packet_generator_uram.data(),
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cancel_data_collection); });
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// Timer procedure - count how many times pedestal_corr/gain_corr is not accepting input (to help track down latency issues)
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hls_cores.emplace_back([&] { timer_hbm(raw3, raw4, counter_hbm); });
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