diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 8fbfdfc0..78c95e6d 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -65,11 +65,11 @@ build:x86:vitis_hls:
rules:
- if: '$CI_PIPELINE_SOURCE == "push"'
changes:
- - receiver/hls/*
- - receiver/hdl/*
- - receiver/scripts/*
- - receiver/xdc/*
- - receiver/microblaze/*
+ - fpga/hls/*
+ - fpga/hdl/*
+ - fpga/scripts/*
+ - fpga/xdc/*
+ - fpga/microblaze/*
- common/Definitions.h
script:
- source /opt/Xilinx/Vitis_HLS/2022.1/settings64.sh
@@ -185,8 +185,7 @@ test:x86:xia2.ssx:
- source /usr/local/dials-v3-13-0/dials_env.sh
- xia2.ssx image=writing_test_master.h5 space_group=P43212 unit_cell=78.551,78.551,36.914,90.000,90.000,90.000
-
-synthesis:vivado_pcie:
+synthesis:vivado_pcie_100g:
stage: synthesis
variables:
GIT_SUBMODULE_STRATEGY: recursive
@@ -196,17 +195,17 @@ synthesis:vivado_pcie:
rules:
- if: '$CI_PIPELINE_SOURCE == "push"'
changes:
- - receiver/hls/*
- - receiver/hdl/*
- - receiver/scripts/*
- - receiver/xdc/*
+ - fpga/hls/*
+ - fpga/hdl/*
+ - fpga/scripts/*
+ - fpga/xdc/*
- common/Definitions.h
tags:
- vivado
artifacts:
paths:
- - build/receiver/*.mcs
- - build/receiver/*.bit
+ - build/fpga/*.mcs
+ - build/fpga/*.bit
expire_in: 1 week
script:
- source /opt/grpc/grpc.sh
diff --git a/.gitmodules b/.gitmodules
index 03b3076b..abbb89b9 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -11,3 +11,6 @@
path = detector_control/slsDetectorPackage
url = https://github.com/slsdetectorgroup/slsDetectorPackage
branch = "developer"
+[submodule "compression/bitshuffle_hperf"]
+ path = compression/bitshuffle_hperf
+ url = https://github.com/kalcutter/bitshuffle
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 70480655..09362380 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -11,13 +11,15 @@ SET(CMAKE_C_FLAGS_RELEASE "-O3 -march=native -mtune=native")
INCLUDE(CheckLanguage)
CHECK_LANGUAGE(CUDA)
-SET(CMAKE_CUDA_ARCHITECTURES 70 75 80 86) # V100, T4, A100, RTX A4000
+SET(CMAKE_CUDA_ARCHITECTURES 70 75 80 86 89) # V100, T4, A100, RTX A4000, L4
SET(CMAKE_CUDA_STANDARD 17)
SET(CMAKE_CUDA_FLAGS_RELEASE "-O3")
IF (CMAKE_CUDA_COMPILER)
ENABLE_LANGUAGE(CUDA)
MESSAGE(STATUS "CUDA VERSION: ${CMAKE_CUDA_COMPILER_VERSION}")
+ ADD_COMPILE_DEFINITIONS(JFJOCH_USE_CUDA)
+ FIND_LIBRARY(CUDART_LIBRARY cudart_static PATHS ${CMAKE_CUDA_IMPLICIT_LINK_DIRECTORIES} REQUIRED)
ENDIF()
SET(JFJOCH_COMPILE_WRITER ON CACHE BOOL "Compile HDF5 writer")
@@ -47,6 +49,7 @@ ADD_SUBDIRECTORY(etc)
SET(jfjoch_executables jfjoch_broker)
IF (JFJOCH_COMPILE_TESTS OR JFJOCH_COMPILE_RECEIVER)
+ ADD_SUBDIRECTORY(fpga)
ADD_SUBDIRECTORY(receiver)
ADD_SUBDIRECTORY(image_analysis)
LIST(APPEND jfjoch_executables jfjoch_receiver)
diff --git a/LICENSE.GPL b/LICENSE.GPL
deleted file mode 100644
index 7a3b7c2f..00000000
--- a/LICENSE.GPL
+++ /dev/null
@@ -1,674 +0,0 @@
- GNU GENERAL PUBLIC LICENSE
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-
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-software for all its users. We, the Free Software Foundation, use the
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-your programs, too.
-
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-to the third party based on the extent of your activity of conveying
-the work, and under which the third party grants, to any of the
-parties who would receive the covered work from you, a discriminatory
-patent license (a) in connection with copies of the covered work
-conveyed by you (or copies made from those copies), or (b) primarily
-for and in connection with specific products or compilations that
-contain the covered work, unless you entered into that arrangement,
-or that patent license was granted, prior to 28 March 2007.
-
- Nothing in this License shall be construed as excluding or limiting
-any implied license or other defenses to infringement that may
-otherwise be available to you under applicable patent law.
-
- 12. No Surrender of Others' Freedom.
-
- If conditions are imposed on you (whether by court order, agreement or
-otherwise) that contradict the conditions of this License, they do not
-excuse you from the conditions of this License. If you cannot convey a
-covered work so as to satisfy simultaneously your obligations under this
-License and any other pertinent obligations, then as a consequence you may
-not convey it at all. For example, if you agree to terms that obligate you
-to collect a royalty for further conveying from those to whom you convey
-the Program, the only way you could satisfy both those terms and this
-License would be to refrain entirely from conveying the Program.
-
- 13. Use with the GNU Affero General Public License.
-
- Notwithstanding any other provision of this License, you have
-permission to link or combine any covered work with a work licensed
-under version 3 of the GNU Affero General Public License into a single
-combined work, and to convey the resulting work. The terms of this
-License will continue to apply to the part which is the covered work,
-but the special requirements of the GNU Affero General Public License,
-section 13, concerning interaction through a network will apply to the
-combination as such.
-
- 14. Revised Versions of this License.
-
- The Free Software Foundation may publish revised and/or new versions of
-the GNU General Public License from time to time. Such new versions will
-be similar in spirit to the present version, but may differ in detail to
-address new problems or concerns.
-
- Each version is given a distinguishing version number. If the
-Program specifies that a certain numbered version of the GNU General
-Public License "or any later version" applies to it, you have the
-option of following the terms and conditions either of that numbered
-version or of any later version published by the Free Software
-Foundation. If the Program does not specify a version number of the
-GNU General Public License, you may choose any version ever published
-by the Free Software Foundation.
-
- If the Program specifies that a proxy can decide which future
-versions of the GNU General Public License can be used, that proxy's
-public statement of acceptance of a version permanently authorizes you
-to choose that version for the Program.
-
- Later license versions may give you additional or different
-permissions. However, no additional obligations are imposed on any
-author or copyright holder as a result of your choosing to follow a
-later version.
-
- 15. Disclaimer of Warranty.
-
- THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
-APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
-HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
-OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
-THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
-IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
-ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
-
- 16. Limitation of Liability.
-
- IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
-THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
-GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
-USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
-DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
-PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
-EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
-SUCH DAMAGES.
-
- 17. Interpretation of Sections 15 and 16.
-
- If the disclaimer of warranty and limitation of liability provided
-above cannot be given local legal effect according to their terms,
-reviewing courts shall apply local law that most closely approximates
-an absolute waiver of all civil liability in connection with the
-Program, unless a warranty or assumption of liability accompanies a
-copy of the Program in return for a fee.
-
- END OF TERMS AND CONDITIONS
-
- How to Apply These Terms to Your New Programs
-
- If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
- To do so, attach the following notices to the program. It is safest
-to attach them to the start of each source file to most effectively
-state the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
-
- Copyright (C)
-
- This program is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
-Also add information on how to contact you by electronic and paper mail.
-
- If the program does terminal interaction, make it output a short
-notice like this when it starts in an interactive mode:
-
- Copyright (C)
- This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
- This is free software, and you are welcome to redistribute it
- under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License. Of course, your program's commands
-might be different; for a GUI interface, you would use an "about box".
-
- You should also get your employer (if you work as a programmer) or school,
-if any, to sign a "copyright disclaimer" for the program, if necessary.
-For more information on this, and how to apply and follow the GNU GPL, see
-.
-
- The GNU General Public License does not permit incorporating your program
-into proprietary programs. If your program is a subroutine library, you
-may consider it more useful to permit linking proprietary applications with
-the library. If this is what you want to do, use the GNU Lesser General
-Public License instead of this License. But first, please read
-.
\ No newline at end of file
diff --git a/LICENSE.OHL-S b/LICENSE.OHL-S
deleted file mode 100644
index dc764b43..00000000
--- a/LICENSE.OHL-S
+++ /dev/null
@@ -1,289 +0,0 @@
-CERN Open Hardware Licence Version 2 - Strongly Reciprocal
-
-
-Preamble
-
-CERN has developed this licence to promote collaboration among
-hardware designers and to provide a legal tool which supports the
-freedom to use, study, modify, share and distribute hardware designs
-and products based on those designs. Version 2 of the CERN Open
-Hardware Licence comes in three variants: CERN-OHL-P (permissive); and
-two reciprocal licences: CERN-OHL-W (weakly reciprocal) and this
-licence, CERN-OHL-S (strongly reciprocal).
-
-The CERN-OHL-S is copyright CERN 2020. Anyone is welcome to use it, in
-unmodified form only.
-
-Use of this Licence does not imply any endorsement by CERN of any
-Licensor or their designs nor does it imply any involvement by CERN in
-their development.
-
-
-1 Definitions
-
- 1.1 'Licence' means this CERN-OHL-S.
-
- 1.2 'Compatible Licence' means
-
- a) any earlier version of the CERN Open Hardware licence, or
-
- b) any version of the CERN-OHL-S, or
-
- c) any licence which permits You to treat the Source to which
- it applies as licensed under CERN-OHL-S provided that on
- Conveyance of any such Source, or any associated Product You
- treat the Source in question as being licensed under
- CERN-OHL-S.
-
- 1.3 'Source' means information such as design materials or digital
- code which can be applied to Make or test a Product or to
- prepare a Product for use, Conveyance or sale, regardless of its
- medium or how it is expressed. It may include Notices.
-
- 1.4 'Covered Source' means Source that is explicitly made available
- under this Licence.
-
- 1.5 'Product' means any device, component, work or physical object,
- whether in finished or intermediate form, arising from the use,
- application or processing of Covered Source.
-
- 1.6 'Make' means to create or configure something, whether by
- manufacture, assembly, compiling, loading or applying Covered
- Source or another Product or otherwise.
-
- 1.7 'Available Component' means any part, sub-assembly, library or
- code which:
-
- a) is licensed to You as Complete Source under a Compatible
- Licence; or
-
- b) is available, at the time a Product or the Source containing
- it is first Conveyed, to You and any other prospective
- licensees
-
- i) as a physical part with sufficient rights and
- information (including any configuration and
- programming files and information about its
- characteristics and interfaces) to enable it either to
- be Made itself, or to be sourced and used to Make the
- Product; or
- ii) as part of the normal distribution of a tool used to
- design or Make the Product.
-
- 1.8 'Complete Source' means the set of all Source necessary to Make
- a Product, in the preferred form for making modifications,
- including necessary installation and interfacing information
- both for the Product, and for any included Available Components.
- If the format is proprietary, it must also be made available in
- a format (if the proprietary tool can create it) which is
- viewable with a tool available to potential licensees and
- licensed under a licence approved by the Free Software
- Foundation or the Open Source Initiative. Complete Source need
- not include the Source of any Available Component, provided that
- You include in the Complete Source sufficient information to
- enable a recipient to Make or source and use the Available
- Component to Make the Product.
-
- 1.9 'Source Location' means a location where a Licensor has placed
- Covered Source, and which that Licensor reasonably believes will
- remain easily accessible for at least three years for anyone to
- obtain a digital copy.
-
- 1.10 'Notice' means copyright, acknowledgement and trademark notices,
- Source Location references, modification notices (subsection
- 3.3(b)) and all notices that refer to this Licence and to the
- disclaimer of warranties that are included in the Covered
- Source.
-
- 1.11 'Licensee' or 'You' means any person exercising rights under
- this Licence.
-
- 1.12 'Licensor' means a natural or legal person who creates or
- modifies Covered Source. A person may be a Licensee and a
- Licensor at the same time.
-
- 1.13 'Convey' means to communicate to the public or distribute.
-
-
-2 Applicability
-
- 2.1 This Licence governs the use, copying, modification, Conveying
- of Covered Source and Products, and the Making of Products. By
- exercising any right granted under this Licence, You irrevocably
- accept these terms and conditions.
-
- 2.2 This Licence is granted by the Licensor directly to You, and
- shall apply worldwide and without limitation in time.
-
- 2.3 You shall not attempt to restrict by contract or otherwise the
- rights granted under this Licence to other Licensees.
-
- 2.4 This Licence is not intended to restrict fair use, fair dealing,
- or any other similar right.
-
-
-3 Copying, Modifying and Conveying Covered Source
-
- 3.1 You may copy and Convey verbatim copies of Covered Source, in
- any medium, provided You retain all Notices.
-
- 3.2 You may modify Covered Source, other than Notices, provided that
- You irrevocably undertake to make that modified Covered Source
- available from a Source Location should You Convey a Product in
- circumstances where the recipient does not otherwise receive a
- copy of the modified Covered Source. In each case subsection 3.3
- shall apply.
-
- You may only delete Notices if they are no longer applicable to
- the corresponding Covered Source as modified by You and You may
- add additional Notices applicable to Your modifications.
- Including Covered Source in a larger work is modifying the
- Covered Source, and the larger work becomes modified Covered
- Source.
-
- 3.3 You may Convey modified Covered Source (with the effect that You
- shall also become a Licensor) provided that You:
-
- a) retain Notices as required in subsection 3.2;
-
- b) add a Notice to the modified Covered Source stating that You
- have modified it, with the date and brief description of how
- You have modified it;
-
- c) add a Source Location Notice for the modified Covered Source
- if You Convey in circumstances where the recipient does not
- otherwise receive a copy of the modified Covered Source; and
-
- d) license the modified Covered Source under the terms and
- conditions of this Licence (or, as set out in subsection
- 8.3, a later version, if permitted by the licence of the
- original Covered Source). Such modified Covered Source must
- be licensed as a whole, but excluding Available Components
- contained in it, which remain licensed under their own
- applicable licences.
-
-
-4 Making and Conveying Products
-
-You may Make Products, and/or Convey them, provided that You either
-provide each recipient with a copy of the Complete Source or ensure
-that each recipient is notified of the Source Location of the Complete
-Source. That Complete Source is Covered Source, and You must
-accordingly satisfy Your obligations set out in subsection 3.3. If
-specified in a Notice, the Product must visibly and securely display
-the Source Location on it or its packaging or documentation in the
-manner specified in that Notice.
-
-
-5 Research and Development
-
-You may Convey Covered Source, modified Covered Source or Products to
-a legal entity carrying out development, testing or quality assurance
-work on Your behalf provided that the work is performed on terms which
-prevent the entity from both using the Source or Products for its own
-internal purposes and Conveying the Source or Products or any
-modifications to them to any person other than You. Any modifications
-made by the entity shall be deemed to be made by You pursuant to
-subsection 3.2.
-
-
-6 DISCLAIMER AND LIABILITY
-
- 6.1 DISCLAIMER OF WARRANTY -- The Covered Source and any Products
- are provided 'as is' and any express or implied warranties,
- including, but not limited to, implied warranties of
- merchantability, of satisfactory quality, non-infringement of
- third party rights, and fitness for a particular purpose or use
- are disclaimed in respect of any Source or Product to the
- maximum extent permitted by law. The Licensor makes no
- representation that any Source or Product does not or will not
- infringe any patent, copyright, trade secret or other
- proprietary right. The entire risk as to the use, quality, and
- performance of any Source or Product shall be with You and not
- the Licensor. This disclaimer of warranty is an essential part
- of this Licence and a condition for the grant of any rights
- granted under this Licence.
-
- 6.2 EXCLUSION AND LIMITATION OF LIABILITY -- The Licensor shall, to
- the maximum extent permitted by law, have no liability for
- direct, indirect, special, incidental, consequential, exemplary,
- punitive or other damages of any character including, without
- limitation, procurement of substitute goods or services, loss of
- use, data or profits, or business interruption, however caused
- and on any theory of contract, warranty, tort (including
- negligence), product liability or otherwise, arising in any way
- in relation to the Covered Source, modified Covered Source
- and/or the Making or Conveyance of a Product, even if advised of
- the possibility of such damages, and You shall hold the
- Licensor(s) free and harmless from any liability, costs,
- damages, fees and expenses, including claims by third parties,
- in relation to such use.
-
-
-7 Patents
-
- 7.1 Subject to the terms and conditions of this Licence, each
- Licensor hereby grants to You a perpetual, worldwide,
- non-exclusive, no-charge, royalty-free, irrevocable (except as
- stated in subsections 7.2 and 8.4) patent licence to Make, have
- Made, use, offer to sell, sell, import, and otherwise transfer
- the Covered Source and Products, where such licence applies only
- to those patent claims licensable by such Licensor that are
- necessarily infringed by exercising rights under the Covered
- Source as Conveyed by that Licensor.
-
- 7.2 If You institute patent litigation against any entity (including
- a cross-claim or counterclaim in a lawsuit) alleging that the
- Covered Source or a Product constitutes direct or contributory
- patent infringement, or You seek any declaration that a patent
- licensed to You under this Licence is invalid or unenforceable
- then any rights granted to You under this Licence shall
- terminate as of the date such process is initiated.
-
-
-8 General
-
- 8.1 If any provisions of this Licence are or subsequently become
- invalid or unenforceable for any reason, the remaining
- provisions shall remain effective.
-
- 8.2 You shall not use any of the name (including acronyms and
- abbreviations), image, or logo by which the Licensor or CERN is
- known, except where needed to comply with section 3, or where
- the use is otherwise allowed by law. Any such permitted use
- shall be factual and shall not be made so as to suggest any kind
- of endorsement or implication of involvement by the Licensor or
- its personnel.
-
- 8.3 CERN may publish updated versions and variants of this Licence
- which it considers to be in the spirit of this version, but may
- differ in detail to address new problems or concerns. New
- versions will be published with a unique version number and a
- variant identifier specifying the variant. If the Licensor has
- specified that a given variant applies to the Covered Source
- without specifying a version, You may treat that Covered Source
- as being released under any version of the CERN-OHL with that
- variant. If no variant is specified, the Covered Source shall be
- treated as being released under CERN-OHL-S. The Licensor may
- also specify that the Covered Source is subject to a specific
- version of the CERN-OHL or any later version in which case You
- may apply this or any later version of CERN-OHL with the same
- variant identifier published by CERN.
-
- 8.4 This Licence shall terminate with immediate effect if You fail
- to comply with any of its terms and conditions.
-
- 8.5 However, if You cease all breaches of this Licence, then Your
- Licence from any Licensor is reinstated unless such Licensor has
- terminated this Licence by giving You, while You remain in
- breach, a notice specifying the breach and requiring You to cure
- it within 30 days, and You have failed to come into compliance
- in all material respects by the end of the 30 day period. Should
- You repeat the breach after receipt of a cure notice and
- subsequent reinstatement, this Licence will terminate
- immediately and permanently. Section 6 shall continue to apply
- after any termination.
-
- 8.6 This Licence shall not be enforceable except by a Licensor
- acting as such, and third party beneficiary rights are
- specifically excluded.
\ No newline at end of file
diff --git a/README.md b/README.md
index 1d372252..63219d37 100644
--- a/README.md
+++ b/README.md
@@ -6,9 +6,7 @@ Citation: F. Leonarski, M. Bruckner, C. Lopez-Cuenca, A. Mozzanica, H.-C. Stadle
## License
-Software components are licensed with GNU Public License version 3.
-
-Hardware components are licensed with Strongly-reciprocal CERN Open Hardware Licence version 2.
+Operating Jungfraujoch, as well as sharing sources code requires explicit license from PSI.
## Hardware requirements
1. JUNGFRAU detector (optimally 4M with 2 kHz enabled read-out boards)
diff --git a/broker/JFJochBroker.cpp b/broker/JFJochBroker.cpp
index fba68673..1e36f54f 100644
--- a/broker/JFJochBroker.cpp
+++ b/broker/JFJochBroker.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "JFJochBroker.h"
diff --git a/broker/JFJochBroker.h b/broker/JFJochBroker.h
index 4d1bfdff..95efda4e 100644
--- a/broker/JFJochBroker.h
+++ b/broker/JFJochBroker.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_JFJOCHBROKER_H
#define JUNGFRAUJOCH_JFJOCHBROKER_H
diff --git a/broker/JFJochBrokerParser.cpp b/broker/JFJochBrokerParser.cpp
index b3d6868d..f94f906c 100644
--- a/broker/JFJochBrokerParser.cpp
+++ b/broker/JFJochBrokerParser.cpp
@@ -1,5 +1,4 @@
// Copyright (2019-2023) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
#include "JFJochBrokerParser.h"
#include "JFJochBroker.h"
diff --git a/broker/JFJochBrokerParser.h b/broker/JFJochBrokerParser.h
index 8efbc1b3..b6a6f084 100644
--- a/broker/JFJochBrokerParser.h
+++ b/broker/JFJochBrokerParser.h
@@ -1,5 +1,4 @@
// Copyright (2019-2023) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
#ifndef JUNGFRAUJOCH_JFJOCHBROKERPARSER_H
#define JUNGFRAUJOCH_JFJOCHBROKERPARSER_H
diff --git a/broker/JFJochServices.cpp b/broker/JFJochServices.cpp
index f4946422..2bcdf7de 100644
--- a/broker/JFJochServices.cpp
+++ b/broker/JFJochServices.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "JFJochServices.h"
#include "../common/JFJochException.h"
diff --git a/broker/JFJochServices.h b/broker/JFJochServices.h
index cd7b9421..e11c83d7 100644
--- a/broker/JFJochServices.h
+++ b/broker/JFJochServices.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_JFJOCHSERVICES_H
#define JUNGFRAUJOCH_JFJOCHSERVICES_H
diff --git a/broker/JFJochStateMachine.cpp b/broker/JFJochStateMachine.cpp
index 90f6177b..e034955c 100644
--- a/broker/JFJochStateMachine.cpp
+++ b/broker/JFJochStateMachine.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include
@@ -64,7 +63,11 @@ void JFJochStateMachine::TakePedestalInternalG0(std::unique_lock &ul
state = JFJochState::Pedestal;
DiffractionExperiment local_experiment(experiment);
local_experiment.Mode(DetectorMode::PedestalG0);
- local_experiment.StorageCellStart(16 - local_experiment.GetStorageCellNumber());
+
+ if (local_experiment.GetStorageCellNumber() == 1)
+ local_experiment.StorageCellStart(15);
+ else
+ local_experiment.StorageCellStart(0);
if (!cancel_sequence && (local_experiment.GetPedestalG0Frames() > 0)) {
services.Start(local_experiment, *calibration);
@@ -88,6 +91,8 @@ void JFJochStateMachine::TakePedestalInternalG1(std::unique_lock &ul
if (local_experiment.GetStorageCellNumber() == 2)
local_experiment.StorageCellStart((storage_cell + 15) % 16); // one previous
+ else
+ local_experiment.StorageCellStart(15);
if (!cancel_sequence && (local_experiment.GetPedestalG1Frames() > 0)) {
services.Start(local_experiment, *calibration);
@@ -111,6 +116,8 @@ void JFJochStateMachine::TakePedestalInternalG2(std::unique_lock &ul
if (local_experiment.GetStorageCellNumber() == 2)
local_experiment.StorageCellStart((storage_cell + 15) % 16); // one previous
+ else
+ local_experiment.StorageCellStart(15);
if (!cancel_sequence && (local_experiment.GetPedestalG2Frames() > 0)) {
services.Start(local_experiment, *calibration);
@@ -180,7 +187,10 @@ void JFJochStateMachine::Start(const JFJochProtoBuf::DatasetSettings& settings)
ClearAndSetMeasurementStatistics();
cancel_sequence = false;
- experiment.StorageCellStart(16 - experiment.GetStorageCellNumber());
+ if (experiment.GetStorageCellNumber() == 1)
+ experiment.StorageCellStart(15);
+ else
+ experiment.StorageCellStart(0);
try {
state = JFJochState::Busy;
diff --git a/broker/JFJochStateMachine.h b/broker/JFJochStateMachine.h
index 07ff62f8..a8c6b430 100644
--- a/broker/JFJochStateMachine.h
+++ b/broker/JFJochStateMachine.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_JFJOCHSTATEMACHINE_H
#define JUNGFRAUJOCH_JFJOCHSTATEMACHINE_H
diff --git a/broker/jfjoch_broker.cpp b/broker/jfjoch_broker.cpp
index c67a775b..a768596c 100644
--- a/broker/jfjoch_broker.cpp
+++ b/broker/jfjoch_broker.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include
#include
diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt
index df35a7f9..96eae103 100644
--- a/common/CMakeLists.txt
+++ b/common/CMakeLists.txt
@@ -43,11 +43,24 @@ ADD_LIBRARY( CommonFunctions STATIC
grpcToJson.h jsonToGrpc.h to_fixed.h
DetectorGeometry.cpp DetectorGeometry.h
DetectorModuleGeometry.cpp DetectorModuleGeometry.h
- DetectorSetup.h DetectorSetup.cpp ZeroCopyReturnValue.h Histogram.h)
+ DetectorSetup.h DetectorSetup.cpp ZeroCopyReturnValue.h Histogram.h DiffractionGeometry.h
+ ROIFilter.h
+ CUDAWrapper.cpp
+ CUDAWrapper.h
+ NUMAHWPolicy.cpp
+ NUMAHWPolicy.h)
TARGET_LINK_LIBRARIES(CommonFunctions Compression FrameSerialize libzmq JFCalibration JFJochProtoBuf -lrt)
-IF(HAS_NUMAIF AND NUMA_LIBRARY)
- TARGET_COMPILE_DEFINITIONS(CommonFunctions PRIVATE -DJFJOCH_USE_NUMA)
- TARGET_LINK_LIBRARIES(CommonFunctions ${NUMA_LIBRARY})
+IF (CMAKE_CUDA_COMPILER)
+ TARGET_SOURCES(CommonFunctions PRIVATE CUDAWrapper.cu )
+ TARGET_LINK_LIBRARIES(CommonFunctions ${CUDART_LIBRARY} ${CMAKE_DL_LIBS} rt)
+ENDIF()
+
+IF(HAS_NUMAIF AND HAS_NUMA_H AND NUMA_LIBRARY)
+ TARGET_COMPILE_DEFINITIONS(CommonFunctions PUBLIC JFJOCH_USE_NUMA)
+ TARGET_LINK_LIBRARIES(CommonFunctions ${NUMA_LIBRARY})
+ MESSAGE(STATUS "NUMA memory/CPU pinning enabled")
+ELSE()
+ MESSAGE(WARNING "NUMA memory/CPU pinning disabled")
ENDIF()
diff --git a/common/CUDAWrapper.cpp b/common/CUDAWrapper.cpp
new file mode 100644
index 00000000..fd2cb331
--- /dev/null
+++ b/common/CUDAWrapper.cpp
@@ -0,0 +1,13 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#ifndef JFJOCH_USE_CUDA
+
+#include "CUDAWrapper.h"
+
+int32_t get_gpu_count() {
+ return 0;
+}
+
+void set_gpu(int32_t dev_id) {}
+
+#endif
diff --git a/common/CUDAWrapper.cu b/common/CUDAWrapper.cu
new file mode 100644
index 00000000..2a259f1c
--- /dev/null
+++ b/common/CUDAWrapper.cu
@@ -0,0 +1,24 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#include "CUDAWrapper.h"
+#include "JFJochException.h"
+
+inline void cuda_err(cudaError_t val) {
+ if (val != cudaSuccess)
+ throw JFJochException(JFJochExceptionCategory::GPUCUDAError, cudaGetErrorString(val));
+}
+
+int32_t get_gpu_count() {
+ int device_count;
+ cuda_err(cudaGetDeviceCount(&device_count));
+ return device_count;
+}
+
+void set_gpu(int32_t dev_id) {
+ auto dev_count = get_gpu_count();
+
+ if ((dev_id < 0) || (dev_id >= dev_count))
+ throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "Device ID cannot be negative");
+
+ cuda_err(cudaSetDevice(dev_id));
+}
\ No newline at end of file
diff --git a/common/CUDAWrapper.h b/common/CUDAWrapper.h
new file mode 100644
index 00000000..af422548
--- /dev/null
+++ b/common/CUDAWrapper.h
@@ -0,0 +1,11 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#ifndef JUNGFRAUJOCH_CUDAWRAPPER_H
+#define JUNGFRAUJOCH_CUDAWRAPPER_H
+
+#include
+
+int32_t get_gpu_count();
+void set_gpu(int32_t dev_id);
+
+#endif //JUNGFRAUJOCH_CUDAWRAPPER_H
diff --git a/common/Coord.cpp b/common/Coord.cpp
index a46308cb..e529c62d 100644
--- a/common/Coord.cpp
+++ b/common/Coord.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include
#include "Coord.h"
diff --git a/common/Coord.h b/common/Coord.h
index d7ad8a05..d6e87118 100644
--- a/common/Coord.h
+++ b/common/Coord.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef INDEX_COORD_H
#define INDEX_COORD_H
diff --git a/common/Definitions.h b/common/Definitions.h
index f6721194..05263436 100644
--- a/common/Definitions.h
+++ b/common/Definitions.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef DEFINITIONS_H
#define DEFINITIONS_H
@@ -18,12 +17,12 @@
#define FPGA_BUFFER_LOCATION_SIZE (RAW_MODULE_SIZE * sizeof(short))
-#define MIN_COUNT_TIME_IN_US 10
+#define MIN_COUNT_TIME_IN_US 5
#define MIN_FRAME_TIME_HALF_SPEED_IN_US 1000
#define MIN_FRAME_TIME_FULL_SPEED_IN_US 470
#define MAX_FRAME_TIME 2000
#define MAX_SUMMATION 5000
-
+#define MIN_STORAGE_CELL_DELAY_IN_NS 2100
#define READOUT_TIME_IN_US 20
#define GRPC_MAX_MESSAGE_SIZE (1000L*1000L*1000L)
@@ -49,12 +48,11 @@
#define DEFAULT_G2_FACTOR (-0.1145)
// For FPGA
-/* This number is unique and is declared in ~snap/ActionTypes.md */
#define ACTION_TYPE 0x52324158
-#define RELEASE_LEVEL 0x0035
+#define RELEASE_LEVEL 0x003C
#define MODE_CONV 0x0001L
-#define MODE_INTERNAL_PACKET_GEN 0x0002L
+#define MODE_NONBLOCKING_ON_WR 0x0002L // Don't block acquisition if there is no WR available
#define TASK_NO_DATA_STREAM UINT16_MAX
@@ -117,4 +115,12 @@
#define CTRL_REGISTER_IDLE (1<<1u)
+#define HANDLE_START (UINT32_MAX - 1)
+#define HANDLE_SKIP_FRAME (UINT32_MAX - 2)
+#define HANDLE_END (UINT32_MAX )
+
+#define INT_PKT_GEN_DEBUG 0x0
+#define INT_PKT_GEN_TIMESTAMP 0xABCDEFABCDEF
+#define INT_PKT_GEN_BUNCHID 0xCACACACACA
+#define INT_PKT_GEN_EXPTTIME 10000
#endif //DEFINITIONS_H
diff --git a/common/DetectorGeometry.cpp b/common/DetectorGeometry.cpp
index 05243ab1..75730e33 100644
--- a/common/DetectorGeometry.cpp
+++ b/common/DetectorGeometry.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "DetectorGeometry.h"
#include "JFJochException.h"
@@ -29,6 +28,8 @@ DetectorGeometry::DetectorGeometry(int32_t nmodules, int32_t horizontal_stacking
throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "Gap x has to be non-negative");
if (gap_y < 0)
throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "Gap y has to be non-negative");
+ if (nmodules < horizontal_stacking)
+ horizontal_stacking = nmodules;
width = horizontal_stacking * CONVERTED_MODULE_COLS + (horizontal_stacking - 1) * gap_x;
int64_t conv_lines = nmodules / horizontal_stacking + (nmodules % horizontal_stacking > 0 ? 1 : 0);
diff --git a/common/DetectorGeometry.h b/common/DetectorGeometry.h
index 2cae7175..44a1d22d 100644
--- a/common/DetectorGeometry.h
+++ b/common/DetectorGeometry.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_DETECTORGEOMETRY_H
#define JUNGFRAUJOCH_DETECTORGEOMETRY_H
diff --git a/common/DetectorModuleGeometry.cpp b/common/DetectorModuleGeometry.cpp
index 0cc391d7..5240b988 100644
--- a/common/DetectorModuleGeometry.cpp
+++ b/common/DetectorModuleGeometry.cpp
@@ -1,5 +1,4 @@
// Copyright (2019-2023) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
#include "DetectorModuleGeometry.h"
#include "JFJochException.h"
diff --git a/common/DetectorModuleGeometry.h b/common/DetectorModuleGeometry.h
index f10583aa..74b2eca7 100644
--- a/common/DetectorModuleGeometry.h
+++ b/common/DetectorModuleGeometry.h
@@ -1,5 +1,4 @@
// Copyright (2019-2023) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
#ifndef JUNGFRAUJOCH_DETECTORMODULEGEOMETRY_H
#define JUNGFRAUJOCH_DETECTORMODULEGEOMETRY_H
diff --git a/common/DetectorSetup.cpp b/common/DetectorSetup.cpp
index e03b4e48..126911ef 100644
--- a/common/DetectorSetup.cpp
+++ b/common/DetectorSetup.cpp
@@ -1,5 +1,4 @@
// Copyright (2019-2023) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
#include "DetectorSetup.h"
#include "JFJochException.h"
diff --git a/common/DetectorSetup.h b/common/DetectorSetup.h
index 47b6c8c6..60fd1456 100644
--- a/common/DetectorSetup.h
+++ b/common/DetectorSetup.h
@@ -1,5 +1,4 @@
// Copyright (2019-2023) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
#ifndef JUNGFRAUJOCH_DETECTORSETUP_H
#define JUNGFRAUJOCH_DETECTORSETUP_H
diff --git a/common/DiffractionExperiment.cpp b/common/DiffractionExperiment.cpp
index ad38a9f7..5d4f4351 100644
--- a/common/DiffractionExperiment.cpp
+++ b/common/DiffractionExperiment.cpp
@@ -1,7 +1,5 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
-#include
#include
#include "NetworkAddressConvert.h"
@@ -37,9 +35,6 @@ DiffractionExperiment::DiffractionExperiment() : DiffractionExperiment(DetectorG
DiffractionExperiment::DiffractionExperiment(const DetectorSetup& det_setup) {
dataset.set_photon_energy_kev(WVL_1A_IN_KEV);
dataset.set_detector_distance_mm(100);
- dataset.mutable_scattering_vector()->set_x(0);
- dataset.mutable_scattering_vector()->set_y(0);
- dataset.mutable_scattering_vector()->set_z(1);
dataset.set_data_file_count(1);
dataset.set_file_prefix("test");
@@ -51,6 +46,12 @@ DiffractionExperiment::DiffractionExperiment(const DetectorSetup& det_setup) {
dataset.set_compression(JFJochProtoBuf::BSHUF_LZ4);
+ dataset.set_rad_int_polarization_corr(false);
+ dataset.set_rad_int_solid_angle_corr(false);
+ dataset.set_save_calibration(false);
+
+ internal.set_debug_pixel_mask(false);
+
internal.set_ndatastreams(1);
internal.set_frame_time_us(MIN_FRAME_TIME_HALF_SPEED_IN_US);
@@ -73,7 +74,7 @@ DiffractionExperiment::DiffractionExperiment(const DetectorSetup& det_setup) {
internal.set_storage_cells(1);
internal.set_storage_cell_start(15);
-
+ internal.set_storage_cell_delay_ns(10*1000);
Detector(det_setup);
Mode(DetectorMode::Conversion);
}
@@ -106,7 +107,7 @@ DiffractionExperiment &DiffractionExperiment::Mode(DetectorMode input) {
}
DiffractionExperiment &DiffractionExperiment::DataStreams(int64_t input) {
- check_max("Number of data streams", input, 7);
+ check_max("Number of data streams", input, 16);
check_min("Number of data streams", input, 1);
internal.set_ndatastreams(input);
return *this;
@@ -209,19 +210,6 @@ DiffractionExperiment &DiffractionExperiment::DetectorDistance_mm(float input) {
return *this;
}
-DiffractionExperiment &DiffractionExperiment::ScatteringVector(Coord input) {
- auto c = input.Normalize();
- dataset.mutable_scattering_vector()->set_x(c.x);
- dataset.mutable_scattering_vector()->set_y(c.y);
- dataset.mutable_scattering_vector()->set_z(c.z);
- return *this;
-}
-
-DiffractionExperiment &DiffractionExperiment::ScatteringVector() {
- dataset.clear_scattering_vector();
- return *this;
-}
-
DiffractionExperiment &DiffractionExperiment::FilePrefix(std::string input) {
// File prefix with front slash is not allowed for security reasons
if (input.front() == '/')
@@ -349,9 +337,9 @@ DiffractionExperiment &DiffractionExperiment::SpaceGroupNumber(int64_t input) {
DiffractionExperiment &DiffractionExperiment::StorageCells(int64_t input) {
check_min("Storage cell number", input, 1);
check_max("Storage cell number", input, 16);
- if ((input != 1) && (input != 2) && (input != 4) && (input != 8) && (input != 16))
- throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
- "Storage cell count invalid, must be power of 2");
+ //if ((input != 1) && (input != 2) && (input != 4) && (input != 8) && (input != 16))
+ // throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
+ // "Storage cell count invalid, must be power of 2");
internal.set_storage_cells(input);
return *this;
}
@@ -551,11 +539,7 @@ float DiffractionExperiment::GetDetectorDistance_mm() const {
}
Coord DiffractionExperiment::GetScatteringVector() const {
- if (dataset.has_scattering_vector())
- return Coord(dataset.scattering_vector().x(), dataset.scattering_vector().y(), dataset.scattering_vector().z())
- * (dataset.photon_energy_kev() / WVL_1A_IN_KEV);
- else
- return {0,0,dataset.photon_energy_kev() / WVL_1A_IN_KEV};
+ return {0,0,dataset.photon_energy_kev() / WVL_1A_IN_KEV};
}
std::string DiffractionExperiment::GetFilePrefix() const {
@@ -773,23 +757,6 @@ bool DiffractionExperiment::HasUnitCell() const {
return dataset.has_unit_cell();
}
-float DiffractionExperiment::ResToPxl(float resolution) const {
- if (resolution == 0)
- return INFINITY;
-
- float sin_theta = GetWavelength_A() / (2 * resolution);
- float theta = asinf(sin_theta);
- float tan_2theta = tanf(2 * theta);
- return tan_2theta * GetDetectorDistance_mm() / GetPixelSize_mm();
-}
-
-float DiffractionExperiment::CalcRadIntSolidAngleCorr(float q) const {
- float sin_theta = q * GetWavelength_A() / (4 * static_cast(M_PI));
- float cos_two_theta = 1.0f - 2.0f * sin_theta * sin_theta; // cos(2*alpha) = 1 - 2 * sin(alpha)^2
- float cos_two_theta_3 = cos_two_theta * cos_two_theta * cos_two_theta;
- return cos_two_theta_3;
-}
-
Coord DiffractionExperiment::LabCoord(float detector_x, float detector_y) const {
// Assumes planar detector, 90 deg towards beam
return {(detector_x - GetBeamX_pxl()) * GetPixelSize_mm() ,
@@ -797,20 +764,6 @@ Coord DiffractionExperiment::LabCoord(float detector_x, float detector_y) const
GetDetectorDistance_mm()};
}
-float DiffractionExperiment::PxlToRes(float detector_x, float detector_y) const {
- auto lab = LabCoord(detector_x, detector_y);
-
- float beam_path = lab.Length();
- if (beam_path == GetDetectorDistance_mm()) return std::numeric_limits::infinity();
-
- float cos_2theta = GetDetectorDistance_mm() / beam_path;
- // cos(2theta) = cos(theta)^2 - sin(theta)^2
- // cos(2theta) = 1 - 2*sin(theta)^2
- // Technically two solutions for two theta, but it makes sense only to take positive one in this case
- float sin_theta = sqrtf((1-cos_2theta)/2);
- return GetWavelength_A() / (2 * sin_theta);
-}
-
int64_t DiffractionExperiment::GetSpaceGroupNumber() const {
return dataset.space_group_number();
}
@@ -880,7 +833,7 @@ DiffractionExperiment::operator JFJochProtoBuf::DetectorInput() const {
}
ret.set_storage_cell_start(GetStorageCellStart());
ret.set_storage_cell_number(GetStorageCellNumber());
- ret.set_storage_cell_delay(7.5);
+ ret.set_storage_cell_delay_ns(GetStorageCellDelay().count());
if (GetStorageCellNumber() > 1) {
ret.set_period_us((GetFrameTime().count() +10) * GetStorageCellNumber());
@@ -946,11 +899,9 @@ void DiffractionExperiment::LoadDatasetSettings(const JFJochProtoBuf::DatasetSet
SetUnitCell();
SpaceGroupNumber(settings.space_group_number());
SampleName(settings.sample_name());
- if (settings.has_scattering_vector())
- ScatteringVector({0,0,1});
Compression(settings.compression());
- ApplyPixelMaskInFPGA(settings.apply_pixel_mask());
Binning2x2(settings.binning2x2());
+ SaveCalibration(settings.save_calibration());
} catch (...) {
dataset = tmp;
throw;
@@ -982,7 +933,8 @@ void DiffractionExperiment::LoadDetectorSettings(const JFJochProtoBuf::DetectorS
if (settings.has_pedestal_g2_frames())
PedestalG2Frames(settings.pedestal_g2_frames());
-
+ if (settings.has_storage_cell_delay_ns())
+ StorageCellDelay(std::chrono::nanoseconds(settings.storage_cell_delay_ns()));
ConversionOnCPU(settings.conversion_on_cpu());
} catch (...) {
internal = tmp;
@@ -1000,6 +952,7 @@ JFJochProtoBuf::DetectorSettings DiffractionExperiment::GetDetectorSettings() co
ret.set_pedestal_g0_frames(GetPedestalG0Frames());
ret.set_pedestal_g1_frames(GetPedestalG1Frames());
ret.set_pedestal_g2_frames(GetPedestalG2Frames());
+ ret.set_storage_cell_delay_ns(GetStorageCellDelay().count());
return ret;
}
@@ -1079,6 +1032,7 @@ void DiffractionExperiment::FillMessage(StartMessage &message) const {
message.compression_block_size = JFJochBitShuffleCompressor::DefaultBlockSize;
message.pixel_bit_depth = GetPixelDepth() * 8;
message.storage_cell_number = GetStorageCellNumber();
+ message.storage_cell_delay_ns = GetStorageCellDelay().count();
message.file_prefix = GetFilePrefix();
message.pixel_signed = IsPixelSigned();
message.sample_name = GetSampleName();
@@ -1111,13 +1065,13 @@ void DiffractionExperiment::FillMessage(StartMessage &message) const {
}
DiffractionExperiment &DiffractionExperiment::ApplyPixelMaskInFPGA(bool input) {
- dataset.set_apply_pixel_mask(input);
+ internal.set_debug_pixel_mask(!input);
return *this;
}
bool DiffractionExperiment::GetApplyPixelMaskInFPGA() const {
if (GetDetectorMode() == DetectorMode::Conversion)
- return dataset.apply_pixel_mask();
+ return !internal.debug_pixel_mask();
else
return false;
}
@@ -1204,3 +1158,77 @@ bool DiffractionExperiment::GetPedestalWithExternalTrigger() const {
return (GetStorageCellNumber() > 1);
}
+DiffractionExperiment &DiffractionExperiment::ApplySolidAngleCorr(bool input) {
+ dataset.set_rad_int_solid_angle_corr(input);
+ return *this;
+}
+
+DiffractionExperiment &DiffractionExperiment::ApplyPolarizationCorr(bool input) {
+ dataset.set_rad_int_polarization_corr(input);
+ return *this;
+}
+
+DiffractionExperiment &DiffractionExperiment::PolarizationFactor(float input) {
+ dataset.set_rad_int_polarization_factor(input);
+ return *this;
+}
+
+bool DiffractionExperiment::GetApplySolidAngleCorr() const {
+ return dataset.rad_int_solid_angle_corr();
+}
+
+bool DiffractionExperiment::GetApplyPolarizationCorr() const {
+ return dataset.rad_int_polarization_corr();
+}
+
+float DiffractionExperiment::GetPolarizationFactor() const {
+ return dataset.rad_int_polarization_factor();
+}
+
+DiffractionExperiment &DiffractionExperiment::ApplyROI(bool input) {
+ internal.set_roi_apply(input);
+ return *this;
+}
+
+DiffractionExperiment &DiffractionExperiment::AddROIRectangle(int32_t x, int32_t y, int32_t width, int32_t height) {
+ auto *tmp = internal.add_roi_rectangle();
+ tmp->set_x0(x);
+ tmp->set_y0(y);
+ tmp->set_width(width);
+ tmp->set_height(height);
+ return *this;
+}
+
+DiffractionExperiment &DiffractionExperiment::ClearROI() {
+ internal.clear_roi_rectangle();
+ return *this;
+}
+
+bool DiffractionExperiment::GetApplyROI() const {
+ return internal.roi_apply();
+}
+
+void DiffractionExperiment::SetupROIFilter(ROIFilter &filter) {
+ for (const auto& i: internal.roi_rectangle())
+ filter.SetRectangle(i.x0(), i.y0(), i.width(), i.height());
+}
+
+DiffractionExperiment &DiffractionExperiment::SaveCalibration(bool input) {
+ dataset.set_save_calibration(input);
+ return *this;
+}
+
+bool DiffractionExperiment::GetSaveCalibration() const {
+ return dataset.save_calibration();
+}
+
+DiffractionExperiment &DiffractionExperiment::StorageCellDelay(std::chrono::nanoseconds input) {
+ check_min("Storage cell delay [ns]", input.count(), MIN_STORAGE_CELL_DELAY_IN_NS);
+ internal.set_storage_cell_delay_ns(input.count());
+ return *this;
+}
+
+std::chrono::nanoseconds DiffractionExperiment::GetStorageCellDelay() const {
+ return std::chrono::nanoseconds(internal.storage_cell_delay_ns());
+}
+
diff --git a/common/DiffractionExperiment.h b/common/DiffractionExperiment.h
index 8723865e..619e7a78 100644
--- a/common/DiffractionExperiment.h
+++ b/common/DiffractionExperiment.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef DIFFRACTIONEXPERIMENT_H
#define DIFFRACTIONEXPERIMENT_H
@@ -15,9 +14,9 @@
#include "UnitCell.h"
#include "Coord.h"
#include "Definitions.h"
-#include "../frame_serialize/StartMessage.h"
-#include "../frame_serialize/EndMessage.h"
+#include "../frame_serialize/CBORMessages.h"
#include "DetectorSetup.h"
+#include "ROIFilter.h"
enum class DetectorMode : int {
Conversion, Raw, PedestalG0, PedestalG1, PedestalG2
@@ -59,8 +58,6 @@ public:
DiffractionExperiment& BeamY_pxl(float input);
DiffractionExperiment& DetectorDistance_mm(float input);
- DiffractionExperiment& ScatteringVector(Coord input);
- DiffractionExperiment& ScatteringVector();
DiffractionExperiment& FilePrefix(std::string input);
DiffractionExperiment& DataFileCount(int64_t input);
@@ -131,6 +128,9 @@ public:
std::chrono::microseconds GetImageCountTime() const;
std::chrono::microseconds GetFrameCountTime() const;
+ DiffractionExperiment& StorageCellDelay(std::chrono::nanoseconds input);
+ std::chrono::nanoseconds GetStorageCellDelay() const;
+
float GetPhotonEnergy_keV() const;
float GetWavelength_A() const;
float GetBeamX_pxl() const;
@@ -184,10 +184,7 @@ public:
UnitCell GetUnitCell() const;
bool HasUnitCell() const;
- float ResToPxl(float resolution) const;
Coord LabCoord(float detector_x, float detector_y) const;
- float PxlToRes(float detector_x, float detector_y) const;
- float CalcRadIntSolidAngleCorr(float q) const;
float GetLowQForRadialInt_recipA() const;
float GetHighQForRadialInt_recipA() const;
@@ -217,6 +214,22 @@ public:
void GetDetectorModuleHostname(std::vector& output) const;
bool GetPedestalWithExternalTrigger() const;
+
+ DiffractionExperiment& ApplySolidAngleCorr(bool input);
+ DiffractionExperiment& ApplyPolarizationCorr(bool input);
+ DiffractionExperiment& PolarizationFactor(float input);
+ bool GetApplySolidAngleCorr() const;
+ bool GetApplyPolarizationCorr() const;
+ float GetPolarizationFactor() const;
+
+ DiffractionExperiment& ApplyROI(bool input);
+ DiffractionExperiment& AddROIRectangle(int32_t x, int32_t y, int32_t width, int32_t height);
+ DiffractionExperiment& ClearROI();
+ bool GetApplyROI() const;
+ void SetupROIFilter(ROIFilter& filter);
+
+ DiffractionExperiment& SaveCalibration(bool input);
+ bool GetSaveCalibration() const;
};
inline int64_t CalculateStride(const std::chrono::microseconds &frame_time, const std::chrono::microseconds &preview_time) {
diff --git a/common/DiffractionGeometry.h b/common/DiffractionGeometry.h
new file mode 100644
index 00000000..b89b82d1
--- /dev/null
+++ b/common/DiffractionGeometry.h
@@ -0,0 +1,99 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#ifndef JUNGFRAUJOCH_DIFFRACTIONGEOMETRY_H
+#define JUNGFRAUJOCH_DIFFRACTIONGEOMETRY_H
+
+#include "DiffractionExperiment.h"
+#include
+
+inline Coord DetectorToRecip(const DiffractionExperiment &experiment, float x, float y) {
+ return experiment.LabCoord(x, y).Normalize() / experiment.GetWavelength_A() - experiment.GetScatteringVector();
+}
+
+inline std::pair RecipToDector(const DiffractionExperiment &experiment, const Coord &recip) {
+ auto S = recip + experiment.GetScatteringVector();
+ float coeff = experiment.GetDetectorDistance_mm() / (S.z * experiment.GetPixelSize_mm());
+ float x = experiment.GetBeamX_pxl() + S.x * coeff;
+ float y = experiment.GetBeamY_pxl() + S.y * coeff;
+ return {x, y};
+}
+
+inline float CosTwoTheta(const DiffractionExperiment& experiment, float x, float y) {
+ auto lab = experiment.LabCoord(x, y);
+ return experiment.GetDetectorDistance_mm() / lab.Length();
+}
+
+inline float Phi(const DiffractionExperiment& experiment, float x, float y) {
+ auto lab = experiment.LabCoord(x, y);
+ return atan2f(lab.y, lab.x);
+}
+
+inline float PxlToRes(const DiffractionExperiment& experiment, float x, float y) {
+ float cos_2theta = CosTwoTheta(experiment, x, y);
+ if (cos_2theta == 1.0f)
+ return std::numeric_limits::infinity();
+
+ // cos(2theta) = cos(theta)^2 - sin(theta)^2
+ // cos(2theta) = 1 - 2*sin(theta)^2
+ // Technically two solutions for two theta, but it makes sense only to take positive one in this case
+ float sin_theta = sqrtf((1 - cos_2theta)/2);
+ return experiment.GetWavelength_A() / (2 * sin_theta);
+}
+
+inline float ResToPxl(const DiffractionExperiment& experiment, float d) {
+ if (d == 0)
+ return INFINITY;
+
+ float sin_theta = experiment.GetWavelength_A() / (2 * d);
+ float theta = asinf(sin_theta);
+ float tan_2theta = tanf(2 * theta);
+ return tan_2theta * experiment.GetDetectorDistance_mm() / experiment.GetPixelSize_mm();
+}
+
+inline float DistFromEwaldSphere(const DiffractionExperiment& experiment, const Coord& recip) {
+ auto S = recip + experiment.GetScatteringVector();
+ return fabsf(S.Length() - (1.0f/experiment.GetWavelength_A()));
+}
+
+inline float CalcRadIntSolidAngleCorr(const DiffractionExperiment& experiment, float q) {
+ float sin_theta = q * experiment.GetWavelength_A() / (4 * static_cast(M_PI));
+ float cos_2theta = 1.0f - 2.0f * sin_theta * sin_theta; // cos(2*alpha) = 1 - 2 * sin(alpha)^2
+ float cos_2theta_3 = cos_2theta * cos_2theta * cos_2theta;
+ return cos_2theta_3;
+}
+
+inline float CalcRadIntSolidAngleCorr(const DiffractionExperiment& experiment, float x, float y) {
+ float cos_2theta = CosTwoTheta(experiment, x, y);
+ float cos_2theta_3 = cos_2theta * cos_2theta * cos_2theta;
+ return cos_2theta_3;
+}
+
+inline float CalcRadIntPolarizationCorr(const DiffractionExperiment& experiment, float x, float y) {
+ auto cos_2theta = CosTwoTheta(experiment, x, y);
+ float cos_2theta_2 = cos_2theta * cos_2theta;
+ float cos_2phi = cosf(2.0f * Phi(experiment, x, y));
+ return 0.5f * (1.0f + cos_2theta_2 - experiment.GetPolarizationFactor() * cos_2phi * (1.0f - cos_2theta_2));
+}
+
+inline std::vector CalcRadIntCorr(const DiffractionExperiment& experiment) {
+ std::vector corr(experiment.GetPixelsNum(), 1.0);
+ auto xpixels = experiment.GetXPixelsNum();
+ auto ypixels = experiment.GetYPixelsNum();
+
+ for (int y = 0; y < ypixels; y++) {
+ for (int x = 0; x < xpixels; x++) {
+ if (experiment.GetApplySolidAngleCorr())
+ corr[y * xpixels + x] *= CalcRadIntSolidAngleCorr(experiment,
+ static_cast(x),
+ static_cast(y));
+ if (experiment.GetApplyPolarizationCorr())
+ corr[y * xpixels + x] *= CalcRadIntPolarizationCorr(experiment,
+ static_cast(x),
+ static_cast(y));
+ }
+ }
+
+ return corr;
+}
+
+#endif //JUNGFRAUJOCH_DIFFRACTIONGEOMETRY_H
diff --git a/common/DiffractionSpot.cpp b/common/DiffractionSpot.cpp
index ea6526ae..f408777f 100644
--- a/common/DiffractionSpot.cpp
+++ b/common/DiffractionSpot.cpp
@@ -1,8 +1,7 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "DiffractionSpot.h"
-#include "RawToConvertedGeometry.h"
+#include "DiffractionGeometry.h"
DiffractionSpot::DiffractionSpot(uint32_t col, uint32_t line, int64_t in_photons) {
if (in_photons < 0) in_photons = 0;
@@ -38,17 +37,16 @@ int64_t DiffractionSpot::PixelCount() const {
return pixel_count;
}
-Coord DiffractionSpot::LabCoord(const DiffractionExperiment &experiment, uint16_t data_stream) const {
+Coord DiffractionSpot::LabCoord(const DiffractionExperiment &experiment) const {
return experiment.LabCoord(x / (float)photons, y / (float)photons);
}
-Coord DiffractionSpot::ReciprocalCoord(const DiffractionExperiment &experiment, uint16_t data_stream) const {
- return LabCoord(experiment, data_stream).Normalize() / experiment.GetWavelength_A()
- - experiment.GetScatteringVector();
+Coord DiffractionSpot::ReciprocalCoord(const DiffractionExperiment &experiment) const {
+ return DetectorToRecip(experiment, x / (float)photons, y / (float)photons);
}
-double DiffractionSpot::GetResolution(const DiffractionExperiment &experiment, uint16_t data_stream) const {
- return experiment.PxlToRes(x / (float)photons, y / (float)photons);
+double DiffractionSpot::GetResolution(const DiffractionExperiment &experiment) const {
+ return PxlToRes(experiment, x / (float)photons, y / (float)photons);
}
DiffractionSpot::operator SpotToSave() const {
diff --git a/common/DiffractionSpot.h b/common/DiffractionSpot.h
index d2359f77..dd138f7f 100644
--- a/common/DiffractionSpot.h
+++ b/common/DiffractionSpot.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_DIFFRACTIONSPOT_H
#define JUNGFRAUJOCH_DIFFRACTIONSPOT_H
@@ -23,9 +22,9 @@ public:
int64_t Count() const;
int64_t MaxCount() const;
Coord RawCoord() const;
- Coord LabCoord(const DiffractionExperiment &experiment, uint16_t data_stream = TASK_NO_DATA_STREAM) const;
- double GetResolution(const DiffractionExperiment &experiment, uint16_t data_stream = TASK_NO_DATA_STREAM) const;
- Coord ReciprocalCoord(const DiffractionExperiment &experiment, uint16_t data_stream = TASK_NO_DATA_STREAM) const;
+ Coord LabCoord(const DiffractionExperiment &experiment) const;
+ double GetResolution(const DiffractionExperiment &experiment) const;
+ Coord ReciprocalCoord(const DiffractionExperiment &experiment) const;
operator SpotToSave() const;
void AddPixel(uint32_t col, uint32_t line, int64_t photons);
};
diff --git a/common/FrameTransformation.cpp b/common/FrameTransformation.cpp
index 924a29a2..7f412eca 100644
--- a/common/FrameTransformation.cpp
+++ b/common/FrameTransformation.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include
@@ -12,7 +11,7 @@
FrameTransformation::FrameTransformation(const DiffractionExperiment &in_experiment) :
experiment(in_experiment), summation(experiment.GetSummation()),
pixel_depth(experiment.GetPixelDepth()), compressor(in_experiment.GetCompressionAlgorithmEnum()),
- binning_2x2(experiment.GetBinning2x2()) {
+ binning_2x2(experiment.GetBinning2x2()), conversion_buffer(RAW_MODULE_SIZE) {
if ((experiment.GetDetectorMode() == DetectorMode::Conversion) && (summation > 1)) {
for (int i = 0; i < experiment.GetModulesNum(); i++)
@@ -143,6 +142,13 @@ void FrameTransformation::ProcessModule(const int16_t *input, uint16_t module_nu
}
}
+void FrameTransformation::ApplyROI(const ROIFilter &filter) {
+ if (pixel_depth == 2)
+ filter.Apply((int16_t *) precompression_buffer.data(), static_cast(INT16_MIN));
+ else
+ filter.Apply((int32_t *) precompression_buffer.data(), static_cast(INT32_MIN));
+}
+
int16_t *FrameTransformation::GetPreview16BitImage() {
if (pixel_depth == 2)
return (int16_t *) precompression_buffer.data();
@@ -163,11 +169,15 @@ void FrameTransformation::ProcessModule(JFConversion &conv, const int16_t *input
if (experiment.GetDetectorMode() != DetectorMode::Conversion)
memcpy(output + RAW_MODULE_SIZE * module_number_abs, input, RAW_MODULE_SIZE * experiment.GetPixelDepth());
- else
- conv.ConvertAdjustGeom((int16_t *) output, (uint16_t *) input,
- experiment.GetModuleSlowDirectionStep(module_number_abs),
- experiment.GetModuleFastDirectionStep(module_number_abs),
- experiment.GetPixel0OfModule(module_number_abs));
+ else {
+ conv.ConvertModule(conversion_buffer.data(), (uint16_t *) input);
+ TransferModuleAdjustMultipixels(output, conversion_buffer.data(),
+ experiment.GetModuleSlowDirectionStep(module_number_abs),
+ static_cast(INT16_MIN),
+ static_cast(INT16_MAX),
+ experiment.GetModuleFastDirectionStep(module_number_abs),
+ experiment.GetPixel0OfModule(module_number_abs));
+ }
} else {
throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
"Summation with CPU conversion not supported at the moment");
diff --git a/common/FrameTransformation.h b/common/FrameTransformation.h
index 13442a2d..d212d9dd 100644
--- a/common/FrameTransformation.h
+++ b/common/FrameTransformation.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_FRAMETRANSFORMATION_H
#define JUNGFRAUJOCH_FRAMETRANSFORMATION_H
@@ -7,6 +6,7 @@
#include "DiffractionExperiment.h"
#include "../compression/JFJochCompressor.h"
#include "../jungfrau/JFConversion.h"
+#include "ROIFilter.h"
class FrameTransformation {
const DiffractionExperiment& experiment;
@@ -14,6 +14,7 @@ class FrameTransformation {
std::vector > summation_buffer;
std::vector precompression_buffer;
+ std::vector conversion_buffer;
std::vector image16bit;
const size_t summation;
@@ -30,6 +31,7 @@ public:
int data_stream);
void Pack(); // transfer summed image to converted coordinates, clear summation buffer
size_t SaveCompressedImage(void *output);
+ void ApplyROI(const ROIFilter &filter);
int16_t *GetPreview16BitImage();
};
diff --git a/common/GitInfo.cpp.in b/common/GitInfo.cpp.in
index 63ec4475..ca5bf312 100644
--- a/common/GitInfo.cpp.in
+++ b/common/GitInfo.cpp.in
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include
diff --git a/common/GitInfo.h b/common/GitInfo.h
index ff359763..fc87481f 100644
--- a/common/GitInfo.h
+++ b/common/GitInfo.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_GITINFO_H
#define JUNGFRAUJOCH_GITINFO_H
diff --git a/common/Histogram.h b/common/Histogram.h
index 7202c616..477aa646 100644
--- a/common/Histogram.h
+++ b/common/Histogram.h
@@ -1,5 +1,4 @@
// Copyright (2019-2023) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
#ifndef JUNGFRAUJOCH_HISTOGRAM_H
#define JUNGFRAUJOCH_HISTOGRAM_H
diff --git a/common/ImagePusher.cpp b/common/ImagePusher.cpp
index 64c9f54f..a88ba5c4 100644
--- a/common/ImagePusher.cpp
+++ b/common/ImagePusher.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "ImagePusher.h"
@@ -12,6 +11,7 @@ void PrepareCBORImage(DataMessage& message,
message.image.ypixel = experiment.GetYPixelsNum();
message.image.pixel_depth_bytes = experiment.GetPixelDepth();
message.image.pixel_is_signed = experiment.IsPixelSigned();
+ message.image.pixel_is_float = false;
message.image.algorithm = experiment.GetCompressionAlgorithmEnum();
message.image.channel = "default";
}
diff --git a/common/ImagePusher.h b/common/ImagePusher.h
index bde64161..8cc4d514 100644
--- a/common/ImagePusher.h
+++ b/common/ImagePusher.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_IMAGEPUSHER_H
#define JUNGFRAUJOCH_IMAGEPUSHER_H
@@ -10,8 +9,7 @@
#include "DiffractionExperiment.h"
#include "DiffractionSpot.h"
#include "../frame_serialize/JFJochFrameSerializer.h"
-#include "../frame_serialize/StartMessage.h"
-#include "../frame_serialize/EndMessage.h"
+#include "../frame_serialize/CBORMessages.h"
#include "ZeroCopyReturnValue.h"
void PrepareCBORImage(DataMessage& message,
diff --git a/common/JFJochException.h b/common/JFJochException.h
index 329d65f5..d57f005a 100644
--- a/common/JFJochException.h
+++ b/common/JFJochException.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef SLSEXCEPTION_H
#define SLSEXCEPTION_H
diff --git a/common/Logger.cpp b/common/Logger.cpp
index 23cc0485..b426da26 100644
--- a/common/Logger.cpp
+++ b/common/Logger.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "spdlog/sinks/daily_file_sink.h"
#include "spdlog/sinks/stdout_color_sinks.h"
diff --git a/common/Logger.h b/common/Logger.h
index fea2c3fd..cf279bca 100644
--- a/common/Logger.h
+++ b/common/Logger.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_LOGGER_H
#define JUNGFRAUJOCH_LOGGER_H
diff --git a/common/NUMAHWPolicy.cpp b/common/NUMAHWPolicy.cpp
new file mode 100644
index 00000000..6aa0433a
--- /dev/null
+++ b/common/NUMAHWPolicy.cpp
@@ -0,0 +1,128 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#include "NUMAHWPolicy.h"
+
+#include "../common/CUDAWrapper.h"
+#include "JFJochException.h"
+
+#ifdef JFJOCH_USE_NUMA
+#include
+#endif
+
+NUMAHWPolicy::NUMAHWPolicy(const std::string &policy) : name(policy) {
+ if ((policy.empty()) || (policy == "none")) {
+ name = "none";
+ } else if (policy == "n2g2") {
+ bindings.emplace_back(NUMABinding{.cpu_node = 0, .mem_node = 0, .gpu = 0});
+ bindings.emplace_back(NUMABinding{.cpu_node = 1, .mem_node = 1, .gpu = 1});
+ } else if (policy == "n2g4") {
+ bindings.emplace_back(NUMABinding{.cpu_node = 0, .mem_node = 0, .gpu = 0});
+ bindings.emplace_back(NUMABinding{.cpu_node = 1, .mem_node = 1, .gpu = 2});
+ bindings.emplace_back(NUMABinding{.cpu_node = 0, .mem_node = 0, .gpu = 1});
+ bindings.emplace_back(NUMABinding{.cpu_node = 1, .mem_node = 1, .gpu = 3});
+ } else if (policy == "n2g4_hbm") {
+ bindings.emplace_back(NUMABinding{.cpu_node = 0, .mem_node = 2, .gpu = 0});
+ bindings.emplace_back(NUMABinding{.cpu_node = 1, .mem_node = 3, .gpu = 2});
+ bindings.emplace_back(NUMABinding{.cpu_node = 0, .mem_node = 2, .gpu = 1});
+ bindings.emplace_back(NUMABinding{.cpu_node = 1, .mem_node = 3, .gpu = 3});
+ } else if (policy == "n8g4") {
+ for (int32_t i = 0; i < 8; i++)
+ bindings.emplace_back(NUMABinding{.cpu_node = i, .mem_node = i, .gpu = i/2});
+ } else if (policy == "n8g4_hbm") {
+ for (int32_t i = 0; i < 8; i++)
+ bindings.emplace_back(NUMABinding{.cpu_node = i, .mem_node = i + 8, .gpu = i / 2});
+ } else if (policy == "g2") {
+ bindings.emplace_back(NUMABinding{.cpu_node = -1, .mem_node = -1, .gpu = 0});
+ bindings.emplace_back(NUMABinding{.cpu_node = -1, .mem_node = -1, .gpu = 1});
+ } else if (policy == "g4") {
+ bindings.emplace_back(NUMABinding{.cpu_node = -1, .mem_node = -1, .gpu = 0});
+ bindings.emplace_back(NUMABinding{.cpu_node = -1, .mem_node = -1, .gpu = 1});
+ bindings.emplace_back(NUMABinding{.cpu_node = -1, .mem_node = -1, .gpu = 2});
+ bindings.emplace_back(NUMABinding{.cpu_node = -1, .mem_node = -1, .gpu = 3});
+ } else
+ throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "Unknown NUMA policy");
+}
+
+NUMAHWPolicy::NUMAHWPolicy(const NUMAHWPolicy &other) : bindings(other.bindings), name(other.name), curr_thread(0) {}
+
+NUMAHWPolicy &NUMAHWPolicy::operator=(const NUMAHWPolicy &other) {
+ bindings = other.bindings;
+ name = other.name;
+ curr_thread = 0;
+ return *this;
+}
+
+NUMABinding NUMAHWPolicy::GetBinding(uint32_t thread) {
+ if (bindings.empty())
+ return NUMABinding{.cpu_node = -1, .mem_node = -1, .gpu = -1};
+ else
+ return bindings.at(thread % bindings.size());
+}
+
+NUMABinding NUMAHWPolicy::GetBinding() {
+ return GetBinding(curr_thread++);
+}
+
+void NUMAHWPolicy::Bind() {
+ Bind(GetBinding());
+}
+
+void NUMAHWPolicy::Bind(uint32_t thread) {
+ Bind(GetBinding(thread));
+}
+
+void NUMAHWPolicy::Bind(const NUMABinding &binding) {
+ RunOnNode(binding.cpu_node);
+ MemOnNode(binding.mem_node);
+ SelectGPU(binding.gpu);
+}
+
+void NUMAHWPolicy::RunOnNode(int32_t cpu_node) {
+#ifdef JFJOCH_USE_NUMA
+ if (numa_available() != -1) {
+ auto max_nodes = numa_num_configured_nodes();
+
+ if (cpu_node >= 0) {
+ if (cpu_node < max_nodes)
+ numa_run_on_node(cpu_node);
+ else
+ throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "CPU NUMA node out of bounds");
+ }
+ }
+#endif
+}
+
+void NUMAHWPolicy::MemOnNode(int32_t mem_node) {
+#ifdef JFJOCH_USE_NUMA
+ if (numa_available() != -1) {
+ auto max_nodes = numa_num_configured_nodes();
+
+ if (mem_node >= 0) {
+ if (mem_node < max_nodes) {
+ struct bitmask *mask = numa_allocate_nodemask();
+ numa_bitmask_setbit(mask, mem_node);
+ numa_set_membind(mask);
+ numa_bitmask_free(mask);
+ } else
+ throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "Memory NUMA node out of bounds");
+ }
+ }
+#endif
+}
+
+void NUMAHWPolicy::SelectGPU(int32_t gpu) {
+#ifdef JFJOCH_USE_CUDA
+ if (gpu > 0) {
+ if (gpu < get_gpu_count())
+ set_gpu(gpu);
+ else
+ throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "GPU device out of bounds");
+ }
+#endif
+}
+
+const std::string &NUMAHWPolicy::GetName() const {
+ return name;
+}
+
+
diff --git a/common/NUMAHWPolicy.h b/common/NUMAHWPolicy.h
new file mode 100644
index 00000000..7829eed4
--- /dev/null
+++ b/common/NUMAHWPolicy.h
@@ -0,0 +1,39 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#ifndef JUNGFRAUJOCH_NUMAHWPOLICY_H
+#define JUNGFRAUJOCH_NUMAHWPOLICY_H
+
+#include
+#include
+#include
+#include
+
+struct NUMABinding {
+ int32_t cpu_node;
+ int32_t mem_node;
+ int32_t gpu;
+};
+
+class NUMAHWPolicy {
+ std::string name;
+ std::vector bindings;
+ std::atomic curr_thread = 0;
+public:
+ NUMAHWPolicy() = default;
+ explicit NUMAHWPolicy(const std::string& policy);
+ NUMAHWPolicy(const NUMAHWPolicy& other);
+ NUMAHWPolicy& operator=(const NUMAHWPolicy& other);
+ NUMABinding GetBinding(uint32_t thread);
+ NUMABinding GetBinding(); // round-robin
+
+ const std::string &GetName() const;
+
+ void Bind(uint32_t thread);
+ void Bind(); // round-robin
+ static void Bind(const NUMABinding &binding);
+ static void RunOnNode(int32_t cpu_node);
+ static void MemOnNode(int32_t mem_node);
+ static void SelectGPU(int32_t gpu);
+};
+
+#endif //JUNGFRAUJOCH_NUMAHWPOLICY_H
diff --git a/common/NetworkAddressConvert.cpp b/common/NetworkAddressConvert.cpp
index c1d2570f..6e0ac0e4 100644
--- a/common/NetworkAddressConvert.cpp
+++ b/common/NetworkAddressConvert.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include
#include
diff --git a/common/NetworkAddressConvert.h b/common/NetworkAddressConvert.h
index 78854c7b..ea8da982 100644
--- a/common/NetworkAddressConvert.h
+++ b/common/NetworkAddressConvert.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_NETWORKADDRESSCONVERT_H
#define JUNGFRAUJOCH_NETWORKADDRESSCONVERT_H
diff --git a/common/ROIFilter.h b/common/ROIFilter.h
new file mode 100644
index 00000000..3cac8404
--- /dev/null
+++ b/common/ROIFilter.h
@@ -0,0 +1,79 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#ifndef JUNGFRAUJOCH_ROIFILTER_H
+#define JUNGFRAUJOCH_ROIFILTER_H
+
+#include
+#include
+#include
+#include "JFJochException.h"
+
+class ROIFilter {
+ int32_t width, height;
+ std::vector mask;
+public:
+ ROIFilter(int32_t in_width, int32_t in_height, uint8_t fill_value = 0)
+ : width(in_width), height(in_height) {
+ if ((width < 0) || (height < 0))
+ throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "Negative dimensions are wrong");
+ mask = std::vector(in_width * in_height, fill_value);
+ }
+
+ void SetRectangle(int32_t x0, int32_t y0, int32_t in_width, int32_t in_height, uint8_t mask_value = 1) {
+ if (x0 < 0) { in_width += x0; x0 = 0; }
+ if (in_width <= 0) return;
+
+ if (x0 >= width) return;
+ if (x0 + in_width >= width) in_width = width - x0;
+
+ if (y0 < 0) { in_height += y0; y0 = 0; }
+ if (in_height <= 0) return;
+
+ if (y0 >= height) return;
+ if (y0 + in_height >= height) in_height = height - y0;
+
+ for (size_t y = y0; y < y0 + in_height; y++) {
+ for (size_t x = x0; x < x0 + in_width; x++) {
+ mask[y * width + x] |= mask_value;
+ }
+ }
+ }
+
+ void ClearRectangle(int32_t x0, int32_t y0, int32_t in_width, int32_t in_height, uint8_t mask_value = 1) {
+ if (x0 < 0) { in_width += x0; x0 = 0; }
+ if (in_width <= 0) return;
+
+ if (x0 >= width) return;
+ if (x0 + in_width >= width) in_width = width - x0;
+
+ if (y0 < 0) { in_height += y0; y0 = 0; }
+ if (in_height <= 0) return;
+
+ if (y0 >= height) return;
+ if (y0 + in_height >= height) in_height = height - y0;
+
+ for (size_t y = y0; y < y0 + in_height; y++) {
+ for (size_t x = x0; x < x0 + in_width; x++) {
+ mask[y * width + x] &= ~mask_value;
+ }
+ }
+ }
+
+ template
+ void Apply(T* data, T fill_value) const {
+ for (size_t i = 0; i < mask.size(); i++) {
+ if (mask[i] == 0)
+ data[i] = fill_value;
+ }
+ }
+
+ template
+ void Apply(std::vector &data, T fill_value) const {
+ if (data.size() != mask.size())
+ throw JFJochException(JFJochExceptionCategory::ArrayOutOfBounds, "Mismatch in array size");
+ Apply(data.data(), fill_value);
+ }
+};
+
+
+#endif //JUNGFRAUJOCH_ROIFILTER_H
diff --git a/common/RawToConvertedGeometry.h b/common/RawToConvertedGeometry.h
index 310f597d..ec59d178 100644
--- a/common/RawToConvertedGeometry.h
+++ b/common/RawToConvertedGeometry.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_RAWTOCONVERTEDGEOMETRY_H
#define JUNGFRAUJOCH_RAWTOCONVERTEDGEOMETRY_H
diff --git a/common/SpotToSave.h b/common/SpotToSave.h
index 5b7dd56d..c63ff7b4 100644
--- a/common/SpotToSave.h
+++ b/common/SpotToSave.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_SPOTTOSAVE_H
#define JUNGFRAUJOCH_SPOTTOSAVE_H
diff --git a/common/StatusVector.h b/common/StatusVector.h
index 980c8a40..9f8206cd 100644
--- a/common/StatusVector.h
+++ b/common/StatusVector.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_STATUSVECTOR_H
#define JUNGFRAUJOCH_STATUSVECTOR_H
diff --git a/common/TestImagePusher.cpp b/common/TestImagePusher.cpp
index 99d4c6bc..fe0aec7e 100644
--- a/common/TestImagePusher.cpp
+++ b/common/TestImagePusher.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "TestImagePusher.h"
#include "../tests/FPGAUnitTest.h"
@@ -106,13 +105,13 @@ bool TestImagePusher::CheckImage(const DiffractionExperiment &x, const std::vect
decompressed_image.data(),
storage_cell);
if (x.GetBinning2x2() && (result > 1.5)) {
- logger.Error("Mean conversion error ({}) larger than threshold", result);
+ logger.Error("Mean conversion error ({:.3f}) larger than threshold", result);
no_errors = false;
} else if (!x.GetBinning2x2() && (result > 0.5)) {
- logger.Error("Mean conversion error ({}) larger than threshold", result);
+ logger.Error("Mean conversion error ({:.3f}) larger than threshold", result);
no_errors = false;
} else
- logger.Info("Mean conversion error: {}", result);
+ logger.Info("Mean conversion error: {:.3f}", result);
} else if (x.GetDetectorMode() == DetectorMode::Raw) {
if (memcmp(raw_reference_image.data(), decompressed_image.data(), sizeof(uint16_t) * x.GetPixelsNum()) !=
0) {
diff --git a/common/TestImagePusher.h b/common/TestImagePusher.h
index 5102b6fa..98098c0b 100644
--- a/common/TestImagePusher.h
+++ b/common/TestImagePusher.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_TESTIMAGEPUSHER_H
#define JUNGFRAUJOCH_TESTIMAGEPUSHER_H
diff --git a/common/ThreadSafeFIFO.h b/common/ThreadSafeFIFO.h
index ca9b0841..b73dd635 100644
--- a/common/ThreadSafeFIFO.h
+++ b/common/ThreadSafeFIFO.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_THREADSAFEFIFO_H
#define JUNGFRAUJOCH_THREADSAFEFIFO_H
diff --git a/common/UnitCell.h b/common/UnitCell.h
index 011fef3f..d9cb1536 100644
--- a/common/UnitCell.h
+++ b/common/UnitCell.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_UNITCELL_H
#define JUNGFRAUJOCH_UNITCELL_H
diff --git a/common/ZMQImagePusher.cpp b/common/ZMQImagePusher.cpp
index 6b7681bf..f45e6d80 100644
--- a/common/ZMQImagePusher.cpp
+++ b/common/ZMQImagePusher.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "ZMQImagePusher.h"
#include "JFJochException.h"
@@ -56,7 +55,7 @@ void ZMQImagePusher::SendImage(const uint8_t *image_data, size_t image_size, int
}
void ZMQImagePusher::StartDataCollection(const StartMessage& message) {
- std::vector serialization_buffer(80*1024*1024);
+ std::vector serialization_buffer(message.approx_size);
JFJochFrameSerializer serializer(serialization_buffer.data(), serialization_buffer.size()); // 80 MiB should be safe even for 16M
if (message.data_file_count < 1)
diff --git a/common/ZMQImagePusher.h b/common/ZMQImagePusher.h
index 9d1af851..eb433cb2 100644
--- a/common/ZMQImagePusher.h
+++ b/common/ZMQImagePusher.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_ZMQIMAGEPUSHER_H
#define JUNGFRAUJOCH_ZMQIMAGEPUSHER_H
diff --git a/common/ZMQPreviewPublisher.cpp b/common/ZMQPreviewPublisher.cpp
index e116cf20..ae298f2f 100644
--- a/common/ZMQPreviewPublisher.cpp
+++ b/common/ZMQPreviewPublisher.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "ZMQPreviewPublisher.h"
#include "grpcToJson.h"
diff --git a/common/ZMQPreviewPublisher.h b/common/ZMQPreviewPublisher.h
index 489ee898..004adf47 100644
--- a/common/ZMQPreviewPublisher.h
+++ b/common/ZMQPreviewPublisher.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_ZMQPREVIEWPUBLISHER_H
#define JUNGFRAUJOCH_ZMQPREVIEWPUBLISHER_H
@@ -9,7 +8,7 @@
#include "ZMQWrappers.h"
#include "DiffractionExperiment.h"
#include "../jungfrau/JFCalibration.h"
-#include "../frame_serialize/ImageMessage.h"
+#include "../frame_serialize/CBORMessages.h"
class ZMQPreviewPublisher {
ZMQSocket socket;
diff --git a/common/ZMQWrappers.cpp b/common/ZMQWrappers.cpp
index f235d95a..f0d569b9 100644
--- a/common/ZMQWrappers.cpp
+++ b/common/ZMQWrappers.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "ZMQWrappers.h"
#include
diff --git a/common/ZMQWrappers.h b/common/ZMQWrappers.h
index 6cc68927..41597d29 100644
--- a/common/ZMQWrappers.h
+++ b/common/ZMQWrappers.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_ZMQWRAPPERS_H
#define JUNGFRAUJOCH_ZMQWRAPPERS_H
@@ -9,7 +8,6 @@
#include
#include
#include
-#include
#include "JFJochException.h"
#include "ZeroCopyReturnValue.h"
diff --git a/common/ZeroCopyReturnValue.h b/common/ZeroCopyReturnValue.h
index 59742d76..ce0fb672 100644
--- a/common/ZeroCopyReturnValue.h
+++ b/common/ZeroCopyReturnValue.h
@@ -1,5 +1,4 @@
// Copyright (2019-2023) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
#ifndef JUNGFRAUJOCH_ZEROCOPYRETURNVALUE_H
#define JUNGFRAUJOCH_ZEROCOPYRETURNVALUE_H
diff --git a/common/grpcToJson.h b/common/grpcToJson.h
index bac0a040..3614fdb6 100644
--- a/common/grpcToJson.h
+++ b/common/grpcToJson.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_GRPCTOJSON_H
#define JUNGFRAUJOCH_GRPCTOJSON_H
@@ -18,7 +17,7 @@ inline std::string grpcToJson(const google::protobuf::Message &message) {
std::string s;
auto status = google::protobuf::util::MessageToJsonString(message, &s, opts);
if (!status.ok())
- throw JFJochException(JFJochExceptionCategory::JSON, "Error in generating JSON from ProtoBuf: " + status.message().ToString());
+ throw JFJochException(JFJochExceptionCategory::JSON, "Error in generating JSON from ProtoBuf");
return s;
}
diff --git a/common/jsonToGrpc.h b/common/jsonToGrpc.h
index a06accbd..5e88135b 100644
--- a/common/jsonToGrpc.h
+++ b/common/jsonToGrpc.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_JSONTOGRPC_H
#define JUNGFRAUJOCH_JSONTOGRPC_H
@@ -18,7 +17,7 @@ T jsonToGrpc(const std::string& json) {
auto status = google::protobuf::util::JsonStringToMessage(json, &output, opts);
if (!status.ok())
- throw JFJochException(JFJochExceptionCategory::JSON, "Error in generating ProtoBuf from JSON: " + status.message().ToString());
+ throw JFJochException(JFJochExceptionCategory::JSON, "Error in generating ProtoBuf from JSON");
return output;
}
diff --git a/common/to_fixed.h b/common/to_fixed.h
index 0389a1b4..351d0638 100644
--- a/common/to_fixed.h
+++ b/common/to_fixed.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_TO_FIXED_H
#define JUNGFRAUJOCH_TO_FIXED_H
diff --git a/compression/CMakeLists.txt b/compression/CMakeLists.txt
index e2fc0669..fd1ca7c1 100644
--- a/compression/CMakeLists.txt
+++ b/compression/CMakeLists.txt
@@ -4,6 +4,8 @@ ADD_LIBRARY(Compression STATIC
bitshuffle/bitshuffle.c
bitshuffle/bitshuffle_core.c
bitshuffle/iochain.c
+ bitshuffle_hperf/src/bitshuffle.c
+ bitshuffle_hperf/src/bitshuffle.h
JFJochZstdCompressor.cpp
JFJochZstdCompressor.h
JFJochCompressor.cpp
diff --git a/compression/CompressionAlgorithmEnum.h b/compression/CompressionAlgorithmEnum.h
index 10321cee..eb9c0fbf 100644
--- a/compression/CompressionAlgorithmEnum.h
+++ b/compression/CompressionAlgorithmEnum.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_COMPRESSIONALGORITHMENUM_H
#define JUNGFRAUJOCH_COMPRESSIONALGORITHMENUM_H
diff --git a/compression/JFJochCompressor.cpp b/compression/JFJochCompressor.cpp
index 1263f251..b9efa8c0 100644
--- a/compression/JFJochCompressor.cpp
+++ b/compression/JFJochCompressor.cpp
@@ -1,11 +1,11 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "JFJochCompressor.h"
#include
#include
#include
+#include
#include
#include
@@ -22,8 +22,7 @@ JFJochBitShuffleCompressor::JFJochBitShuffleCompressor(CompressionAlgorithm in_a
size_t JFJochBitShuffleCompressor::CompressBlock(char *dest, const char *source, size_t nelements, size_t elem_size) {
// Assert nelements < block_size
const char *src_ptr;
-
- int64_t bshuf_ret = bshuf_trans_bit_elem(source, tmp_space.data(), nelements, elem_size);
+ int64_t bshuf_ret = bitshuf_encode_block(tmp_space.data(), source, scratch, nelements, elem_size);
if (bshuf_ret < 0)
throw JFJochException(JFJochExceptionCategory::Compression, "bshuf_trans_bit_elem error");
src_ptr = tmp_space.data();
diff --git a/compression/JFJochCompressor.h b/compression/JFJochCompressor.h
index 7aff36a5..7da600a7 100644
--- a/compression/JFJochCompressor.h
+++ b/compression/JFJochCompressor.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_JFJOCHCOMPRESSOR_H
#define JUNGFRAUJOCH_JFJOCHCOMPRESSOR_H
@@ -10,6 +9,7 @@
#include
#include
#include "CompressionAlgorithmEnum.h"
+#include "MaxCompressedSize.h"
#include "JFJochZstdCompressor.h"
@@ -17,16 +17,29 @@ class JFJochBitShuffleCompressor {
JFJochZstdCompressor zstd_compressor;
CompressionAlgorithm algorithm;
std::vector tmp_space;
+
size_t CompressBlock(char *dest, const char * source, size_t nelements, size_t elem_size);
public:
constexpr static const size_t DefaultBlockSize = 4096;
- JFJochBitShuffleCompressor(CompressionAlgorithm algorithm);
+ explicit JFJochBitShuffleCompressor(CompressionAlgorithm algorithm);
+
template
size_t Compress(void *dest, const std::vector &src) {
return Compress((char *) dest, (char *) src.data(), src.size(), sizeof(T));
};
+
+ template
+ std::vector Compress(const std::vector &src) {
+ std::vector tmp(MaxCompressedSize(algorithm, src.size(), sizeof(T)));
+ size_t tmp_size = Compress(tmp.data(), src);
+ tmp.resize(tmp_size);
+ return tmp;
+ }
+
size_t Compress(char *dest, const char* source, size_t nelements, size_t elem_size);
+private:
+ char scratch[DefaultBlockSize * sizeof(uint64_t)];
};
template std::vector bitshuffle(const std::vector &input, size_t block_size) {
diff --git a/compression/JFJochDecompress.h b/compression/JFJochDecompress.h
index b373bd72..f6424992 100644
--- a/compression/JFJochDecompress.h
+++ b/compression/JFJochDecompress.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_JFJOCHDECOMPRESS_H
#define JUNGFRAUJOCH_JFJOCHDECOMPRESS_H
diff --git a/compression/JFJochZstdCompressor.cpp b/compression/JFJochZstdCompressor.cpp
index 2ec156b7..8fca994a 100644
--- a/compression/JFJochZstdCompressor.cpp
+++ b/compression/JFJochZstdCompressor.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "JFJochZstdCompressor.h"
diff --git a/compression/JFJochZstdCompressor.h b/compression/JFJochZstdCompressor.h
index 2775e134..28084bea 100644
--- a/compression/JFJochZstdCompressor.h
+++ b/compression/JFJochZstdCompressor.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_JFJOCHZSTDCOMPRESSOR_H
#define JUNGFRAUJOCH_JFJOCHZSTDCOMPRESSOR_H
diff --git a/compression/MaxCompressedSize.cpp b/compression/MaxCompressedSize.cpp
index c21132e9..0646e607 100644
--- a/compression/MaxCompressedSize.cpp
+++ b/compression/MaxCompressedSize.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include
diff --git a/compression/MaxCompressedSize.h b/compression/MaxCompressedSize.h
index 52689674..6ecd3e17 100644
--- a/compression/MaxCompressedSize.h
+++ b/compression/MaxCompressedSize.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_MAXCOMPRESSEDSIZE_H
#define JUNGFRAUJOCH_MAXCOMPRESSEDSIZE_H
diff --git a/compression/bitshuffle_hperf b/compression/bitshuffle_hperf
new file mode 160000
index 00000000..be844a76
--- /dev/null
+++ b/compression/bitshuffle_hperf
@@ -0,0 +1 @@
+Subproject commit be844a76f4d4ed3927fcb240a36c6d52bb3908a3
diff --git a/detector_control/DetectorWrapper.cpp b/detector_control/DetectorWrapper.cpp
index cbaf5b9d..b434f059 100644
--- a/detector_control/DetectorWrapper.cpp
+++ b/detector_control/DetectorWrapper.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include
@@ -10,8 +9,17 @@
void DetectorWrapper::Configure(const JFJochProtoBuf::DetectorConfig &request) {
logger.Info("Configure");
try {
- if (det.size() > 0)
+ if (det.size() > 0) {
+ // Only if the detector is already defined
+
+ // Stop the detector
InternalStop();
+
+ // Clear synchronization prior to reconfiguring the detector
+ det.setMaster(false, 0);
+ det.setSynchronization(false);
+ }
+
if (request.module_hostname_size() > 0) {
std::vector module_hostname;
for (const auto &iter: request.module_hostname())
@@ -100,7 +108,7 @@ void DetectorWrapper::Start(const JFJochProtoBuf::DetectorInput &request) {
det.setNumberOfTriggers(request.num_triggers());
det.setStorageCellStart(request.storage_cell_start());
det.setNumberOfAdditionalStorageCells(request.storage_cell_number() - 1);
- det.setStorageCellDelay(std::chrono::nanoseconds(static_cast(request.storage_cell_delay() * 1000)));
+ det.setStorageCellDelay(std::chrono::nanoseconds(request.storage_cell_delay_ns() - MIN_STORAGE_CELL_DELAY_IN_NS));
if (request.period_us() < MIN_FRAME_TIME_HALF_SPEED_IN_US)
det.setReadoutSpeed(slsDetectorDefs::speedLevel::FULL_SPEED);
diff --git a/detector_control/DetectorWrapper.h b/detector_control/DetectorWrapper.h
index ed8d280d..2bc09426 100644
--- a/detector_control/DetectorWrapper.h
+++ b/detector_control/DetectorWrapper.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_DETECTORWRAPPER_H
#define JUNGFRAUJOCH_DETECTORWRAPPER_H
diff --git a/detector_control/JFJochDetector.cpp b/detector_control/JFJochDetector.cpp
index 45503c8c..fa328863 100644
--- a/detector_control/JFJochDetector.cpp
+++ b/detector_control/JFJochDetector.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "JFJochDetector.h"
#include "../common/JFJochException.h"
diff --git a/detector_control/JFJochDetector.h b/detector_control/JFJochDetector.h
index 61e21094..4c88e4a6 100644
--- a/detector_control/JFJochDetector.h
+++ b/detector_control/JFJochDetector.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef DETECTORWRAPPER_H
#define DETECTORWRAPPER_H
diff --git a/detector_control/jfjoch_detector.cpp b/detector_control/jfjoch_detector.cpp
index 520d8849..d3f0e133 100644
--- a/detector_control/jfjoch_detector.cpp
+++ b/detector_control/jfjoch_detector.cpp
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include
#include
diff --git a/detector_control/slsDetectorPackage b/detector_control/slsDetectorPackage
index 77c558a7..f761046b 160000
--- a/detector_control/slsDetectorPackage
+++ b/detector_control/slsDetectorPackage
@@ -1 +1 @@
-Subproject commit 77c558a7be56ff1e7391e35ed4c01dc3a36412a1
+Subproject commit f761046bfc1aa8d3fc4e52730fedfe206b1c79a7
diff --git a/fpga/CMakeLists.txt b/fpga/CMakeLists.txt
new file mode 100644
index 00000000..a331b46d
--- /dev/null
+++ b/fpga/CMakeLists.txt
@@ -0,0 +1,30 @@
+FIND_PROGRAM(VIVADO vivado DOC "Xilinx Vivado")
+IF (VIVADO)
+ MESSAGE(STATUS "Xilinx Vivado found: ${VIVADO}")
+ELSE()
+ MESSAGE(STATUS "Xilinx Vivado not found")
+ENDIF()
+
+FIND_PROGRAM(VIVADO_HLS NAMES vitis_hls DOC "Xilinx HLS")
+IF (VIVADO_HLS)
+ MESSAGE(STATUS "Xilinx HLS compiler found: ${VIVADO_HLS}")
+ELSE()
+ MESSAGE(STATUS "Xilinx HLS compiler not found")
+ENDIF()
+
+INCLUDE_DIRECTORIES(include)
+
+ADD_SUBDIRECTORY(hls)
+ADD_SUBDIRECTORY(pcie_driver)
+
+IF(VIVADO_HLS AND VIVADO)
+ ADD_CUSTOM_COMMAND(OUTPUT action/hw/hdl/action_config.v
+ COMMAND ${CMAKE_COMMAND} -E env SRC_DIR=${CMAKE_CURRENT_SOURCE_DIR} HLS_IP_DIR=${CMAKE_CURRENT_BINARY_DIR}/action/ip/hls bash ${CMAKE_CURRENT_SOURCE_DIR}/scripts/setup_action.sh
+ DEPENDS hls hdl/action_config.v hdl/check_datamover_error.v hdl/check_eth_busy.v hdl/gen_xdma_descriptor.v hdl/refclk300to100.v hdl/action_wrapper.v hdl/resetn_sync.v scripts/bd_pcie.tcl scripts/jfjoch.tcl scripts/network_stack.tcl scripts/hbm_u55c.tcl scripts/mac_100g_pcie.tcl scripts/pcie_dma.tcl scripts/setup_action.sh
+ )
+
+ ADD_CUSTOM_TARGET(action_pcie DEPENDS action/hw/hdl/action_config.v hls
+ COMMAND ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_SOURCE_DIR}/scripts/build_pcie_design.tcl
+ COMMAND ${CMAKE_COMMAND} -E env FLOW=pcie_100gbit VIV_PROJECT_PATH=${CMAKE_CURRENT_BINARY_DIR}/vivado/jfjoch_pcie.xpr ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_BINARY_DIR}/action/scripts/synth_and_impl.tcl
+ )
+ENDIF()
diff --git a/fpga/README.md b/fpga/README.md
new file mode 100644
index 00000000..ac7593e9
--- /dev/null
+++ b/fpga/README.md
@@ -0,0 +1,136 @@
+# FPGA Smart Network Interface Card
+
+## Hardware
+Currently supported FPGA is only Xilinx Alveo U55C
+
+## Content of directories
+
+CPU Part:
+
+* `pcie_driver` Linux kernel driver for PCIe version of the FPGA board
+
+FPGA part:
+
+* `scripts` Scripts for FPGA synthesis
+* `xdc` Constraints for FPGA
+* `hdl` FPGA design parts developed in Verilog
+* `hls` FPGA design parts developed in C++ with high-level synthesis
+
+Dependencies:
+
+* `include` External (Xilinx) headers for high-level synthesis code
+
+
+## HLS compilation
+Make HLS routines:
+```
+mkdir build
+cd build
+cmake3 ..
+make hls
+```
+
+## Synthesis
+Create PCIe bitstream with 2 data stream (200 Gbit/s) and bifurcated 2 x Gen4x8 PCIe design:
+```
+mkdir build
+cd build
+cmake3 ..
+make action_pcie
+```
+
+Create PCIe bitstream with 1 data stream (100 Gbit/s) and single Gen4x8 PCIe interface:
+```
+mkdir build
+cd build
+cmake3 ..
+make action_pcie_100g
+```
+
+## Hardware verification
+
+To test that FPGA board is working properly without access to a JUNGFRAU detector, you can use `jfjoch_action_test` tool.
+
+## FPGA reference
+FPGA setup can be done via 32-bit registers:
+
+| Address | Bits | Meaning | Mode | Notes |
+|---------------------|------|------------------------------------------------------------------------------------------------------|:-----|----------------------------------------------|
+| 0x00000 - 0x0FFFF | | Reserved (in case using MicroBlaze in the future, this has to reserved for internal memory) | | |
+| 0x010000 | 32 | Action Control Register | | |
+| | | Bit 0 - Action start | R/W | |
+| | | Bit 1 - Action idle | R | |
+| | | Bit 2 - Action cancel | R/W | cleared on reset or action start |
+| | | Bit 3 - Clear network counters | R/W | cleared on reset or action start |
+| | | Bit 4 - Host writer idle | R | cleared on reset |
+| | | Bit 7 - Design number | R | 0 = PCIe #0, 1 = PCIe #1 |
+| | | Bit 16 - AXI Mailbox interrupt 0 | R | |
+| | | Bit 17 - AXI Mailbox interrupt 1 | R | |
+| | | Bits 24-27 - Various errors in host memory writer | R | cleared on reset or action start |
+| 0x010004 | 32 | Reserved | - | |
+| 0x01000C | 32 | Action GIT SHA1 | R | |
+| 0x010010 | 32 | Action Type | R | |
+| 0x010014 | 32 | Action Release Level | R | |
+| 0x010020 | 32 | Max. number supported detector modules | R | constant |
+| 0x010024 | 32 | Number of modules in internal packet generator memory | R | constant |
+| 0x010028 | 64 | Pipeline stalls before writing to host memory | R | reset on action start |
+| 0x010030 | 64 | Pipeline stalls before accessing HBM | R | reset on action start |
+| 0x010038 | 32 | FIFO status (see action_config.v for details) | R | |
+| 0x01003C | 32 | Size of single HBM channel in bytes (default value for the particular card) | R/W | should not be altered for standard operation |
+| 0x010040 | 64 | Packets processed by the action | R | cleared on reset or action start |
+| 0x010048 | 64 | Valid ethernet packets | R | cleared on reset |
+| 0x010050 | 64 | Valid ICMP packets | R | cleared on reset |
+| 0x010058 | 64 | Valid UDP packets | R | cleared on reset |
+| 0x010060 | 64 | MAC address of FPGA card | R/W | network byte order |
+| 0x010068 | 32 | IPv4 address of FPGA card | R/W | network byte order |
+| 0x01006C | 32 | Number of detector modules | R/W | |
+| 0x010070 | 32 | Data collection mode | R/W | |
+| | | Bit 0 - Conversion to photons | | |
+| | | Bit 1 - Use internal packet generator | | |
+| | | Bit 2 - Nonblocking operation (host writer will ignore frames if there is no available work request) | | |
+| | | Bit 16:31 - Data collection ID (carried with completions) | | |
+| 0x010074 | 32 | One over energy in keV (in fixed-point:12 int. + 24 frac. bit format) | R/W | |
+| 0x010078 | 32 | Number of frames to be generated by internal packet generator | R/W | |
+| 0x01007C | 32 | Number of storage cells | R/W | |
+| | | | | |
+| 0x020000 - 0x02FFFF | | CMAC 100G | | See Xilinx PG203 for register map |
+| 0x030000 - 0x03FFFF | | AXI Mailbox for Work Request / Work Completion | | See Xilinx PG114 for register map |
+| 0x040000 - 0x04FFFF | | QuadSPI flash | | See Xilinx PG153 for register map |
+| 0x060000 - 0x060FFF | 64 | Input calibration memory addresses block RAM | | |
+| 0x070000 - 0x07FFFF | | AXI Firewall | | See Xilinx PG293 for register map |
+| 0x090000 - 0x09FFFF | | PCIe DMA control | | See Xilinx PG195 for register map |
+| 0x0A0000 - 0x0AFFFF | | Transfer between UltraRAM buffer <-> HBM (HLS registers) | | |
+| 0x0C0000 - 0x0FFFFF | | Xilinx Card Management Solution Subsystem management subsystem | | See Xilinx PG348 for register map |
+| 0x100000 - 0x1FFFFF | 16 | Internal packet generator frame | | |
+| 0x200000 - 0x2FFFFF | | UltraRAM buffer for transfers to/from HBM | | |
+
+### AXI Mailbox
+
+AXI mailbox is used to send work request from host to action, and receive work completions. Messages are always multiple of 128-bit. See Xilinx PG114 on how to operate AXI Mailbox.
+
+Work request has the following structure:
+
+| Bit start | Bit end | Meaning |
+|-----------|---------|----------------------------------------------------|
+| 0 | 31 | Work request ID (handle) |
+| 32 | 95 | Address (Virt: OpenCAPI, DMA: PCIe) |
+| 96 | 127 | Includes parity bit, so bits 0-127 are even parity |
+
+Work completion has the following structure:
+
+| Bit start | Bit end | Meaning |
+|-----------|---------|--------------------------------------------------------------------|
+| 0 | 31 | Work request ID (handle) |
+| 32 | 39 | Module number |
+| 40 | 40 | All packets for the module arrived OK |
+| 41 | 41 | Trigger signal high |
+| 42 | 62 | Reserved |
+| 63 | 63 | Parity bit - bits 0-127 are even parity |
+| 64 | 127 | Frame number |
+| 128 | 191 | JF Timestamp |
+| 192 | 255 | Bunch ID |
+| 256 | 287 | Exptime |
+| 288 | 319 | JF debug |
+| 320 | 351 | Reserved |
+| 352 | 383 | Data collection ID (16-bit) |
+| 384 | 511 | Packet mask (1 bit per packet: 0 packet missing, 1 packet arrived) |
diff --git a/receiver/hdl/action_config.v b/fpga/hdl/action_config.v
similarity index 80%
rename from receiver/hdl/action_config.v
rename to fpga/hdl/action_config.v
index 197f9585..d59f65fb 100644
--- a/receiver/hdl/action_config.v
+++ b/fpga/hdl/action_config.v
@@ -1,21 +1,20 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0
+// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1ns/1ps
// parameters imported from source files
`define ACTION_TYPE 32'h52324158
-`define RELEASE_LEVEL 32'h00000000
-`define GIT_SHA1 32'h00000000
-`define MAX_MODULES_FPGA 32'd8
+`define RELEASE_LEVEL 32'h
+`define GIT_SHA1 32'h
+`define MAX_MODULES_FPGA 32'd16
+`define HBM_SIZE_BYTES 32'h20000000
`define ADDR_AP_CTRL 16'h0000
`define ADDR_SET_LED 16'h0008
`define ADDR_GIT_SHA1 16'h000C
-`define ADDR_ACTION_TYPE 32'h0010
-`define ADDR_RELEASE_LEVEL 32'h0014
-`define ADDR_HBM_TEMP 16'h0018
+`define ADDR_ACTION_TYPE 16'h0010
+`define ADDR_RELEASE_LEVEL 16'h0014
`define ADDR_MAX_MODULES_FPGA 16'h0020
`define ADDR_MODS_INT_PKT_GEN 16'h0024
@@ -24,6 +23,7 @@
`define ADDR_STALLS_HBM_LO 16'h0030
`define ADDR_STALLS_HBM_HI 16'h0034
`define ADDR_FIFO_STATUS 16'h0038
+`define ADDR_HBM_SIZE 16'h003C
`define ADDR_PACKETS_PROC_LO 16'h0040
`define ADDR_PACKETS_PROC_HI 16'h0044
@@ -89,14 +89,13 @@ module action_config
output reg [31:0] nframes ,
output reg [7:0] nmodules ,
output reg [3:0] nstorage_cells ,
+ output reg [31:0] hbm_size_bytes ,
output reg data_collection_start ,
output reg data_collection_cancel ,
input data_collection_idle ,
- input [6:0] hbm_temperature ,
- input hbm_temp_trip ,
- input apb_complete_0 ,
+ input host_writer_idle ,
input calib_data_fifo_empty ,
input calib_data_fifo_full ,
input calib_addr_fifo_empty ,
@@ -104,10 +103,14 @@ module action_config
input udp_fifo_empty ,
input udp_fifo_full ,
- input host_mem_data_fifo_empty ,
- input host_mem_data_fifo_full ,
- input host_mem_cmd_fifo_empty ,
- input host_mem_cmd_fifo_full ,
+ input c2h_data_fifo_empty ,
+ input c2h_data_fifo_full ,
+ input c2h_cmd_fifo_empty ,
+ input c2h_cmd_fifo_full ,
+ input h2c_data_fifo_empty ,
+ input h2c_data_fifo_full ,
+ input h2c_cmd_fifo_empty ,
+ input h2c_cmd_fifo_full ,
input work_req_fifo_empty ,
input work_req_fifo_full ,
input work_compl_fifo_empty ,
@@ -116,7 +119,10 @@ module action_config
input last_data_fifo_full ,
input last_addr_fifo_empty ,
input last_addr_fifo_full ,
-
+ input frame_generator_fifo_empty ,
+ input frame_generator_fifo_full ,
+ input eth_in_fifo_empty ,
+ input eth_in_fifo_full ,
input mailbox_interrupt_0 ,
input mailbox_interrupt_1 ,
@@ -140,16 +146,8 @@ module action_config
input [31:0] udp_err_len ,
input udp_err_len_valid ,
- input [3:0] host_writer_err ,
- input host_writer_err_valid ,
- input eth_stat_rx_status ,
- input eth_stat_rx_aligned ,
- input eth_busy ,
- input eth_stat_rx_packet_bad_fcs ,
- input mm2s_error ,
- input s2mm_error ,
- output qsfp_led_busy ,
- output qsfp_led_conn ,
+ input [7:0] host_writer_err ,
+ input host_writer_err_valid ,
output reg clear_counters
);
//------------------------Parameter----------------------
@@ -178,33 +176,8 @@ localparam
wire [ADDR_BITS-1:0] raddr;
// JFJoch signals
- (* ASYNC_REG = "TRUE" *) reg [6:0] reg_hbm_temperature_1;
- (* ASYNC_REG = "TRUE" *) reg [6:0] reg_hbm_temperature_2;
-
- (* ASYNC_REG = "TRUE" *) reg reg_hbm_temp_trip_1;
- (* ASYNC_REG = "TRUE" *) reg reg_hbm_temp_trip_2;
-
- (* ASYNC_REG = "TRUE" *) reg reg_apb_complete_0_1;
- (* ASYNC_REG = "TRUE" *) reg reg_apb_complete_0_2;
-
- (* ASYNC_REG = "TRUE" *) reg reg_eth_busy_1;
- (* ASYNC_REG = "TRUE" *) reg reg_eth_busy_2;
-
- (* ASYNC_REG = "TRUE" *) reg reg_eth_stat_rx_status_1;
- (* ASYNC_REG = "TRUE" *) reg reg_eth_stat_rx_aligned_1;
-
- (* ASYNC_REG = "TRUE" *) reg reg_eth_stat_rx_status_2;
- (* ASYNC_REG = "TRUE" *) reg reg_eth_stat_rx_aligned_2;
-
- (* ASYNC_REG = "TRUE" *) reg reg_eth_stat_rx_packet_bad_fcs_1;
- (* ASYNC_REG = "TRUE" *) reg reg_eth_stat_rx_packet_bad_fcs_2;
- reg reg_eth_stat_rx_packet_bad_fcs_ever;
reg [31:0] reg_ctrl;
- reg [6:0] reg_hbm_temperature;
- reg reg_hbm_temp_trip;
- reg reg_hbm_temp_trip_ever;
-
reg [63:0] reg_stalls_hbm;
reg [63:0] reg_stalls_host;
reg [63:0] reg_packets_processed;
@@ -217,7 +190,7 @@ localparam
reg [31:0] reg_udp_err_eth;
reg [31:0] reg_fifo_status;
- reg [3:0] reg_host_writer_err;
+ reg [7:0] reg_host_writer_err;
reg reg_data_collection_idle;
//------------------------Instantiation------------------
@@ -347,9 +320,6 @@ always @(posedge clk) begin
`ADDR_MODS_INT_PKT_GEN: begin
rdata <= 32'd1;
end
- `ADDR_HBM_TEMP: begin
- rdata <= reg_hbm_temperature;
- end
`ADDR_STALLS_HBM_HI: begin
rdata <= reg_stalls_hbm[63:32];
end
@@ -398,6 +368,9 @@ always @(posedge clk) begin
`ADDR_PACKETS_ERR_ETH: begin
rdata <= reg_udp_err_eth;
end
+ `ADDR_HBM_SIZE: begin
+ rdata <= hbm_size_bytes;
+ end
`ADDR_FIFO_STATUS: begin
rdata <= reg_fifo_status;
end
@@ -414,6 +387,17 @@ initial data_collection_start = 1'b0;
initial data_collection_cancel = 1'b0;
initial reg_ctrl = 32'b0;
+initial hbm_size_bytes = `HBM_SIZE_BYTES;
+
+always @(posedge clk) begin
+ if (!resetn)
+ hbm_size_bytes = `HBM_SIZE_BYTES;
+ else if (reg_data_collection_idle) begin
+ if (w_hs && waddr == `ADDR_HBM_SIZE)
+ hbm_size_bytes <= (s_axi_WDATA[31:0] & wmask) | (hbm_size_bytes & !wmask);
+ end
+end
+
always @(posedge clk) begin
if (!resetn)
reg_ctrl <= 32'b0;
@@ -422,17 +406,8 @@ always @(posedge clk) begin
reg_ctrl[1] <= reg_data_collection_idle;
reg_ctrl[2] <= data_collection_cancel;
reg_ctrl[3] <= clear_counters;
+ reg_ctrl[4] <= host_writer_idle;
reg_ctrl[7] <= DESIGN_NUMBER;
- reg_ctrl[8] <= reg_eth_stat_rx_status_2;
- reg_ctrl[9] <= reg_eth_stat_rx_aligned_2;
- if (mm2s_error)
- reg_ctrl[10] <= 1;
- if (s2mm_error)
- reg_ctrl[11] <= 1;
- reg_ctrl[12] <= reg_hbm_temp_trip;
- reg_ctrl[13] <= reg_hbm_temp_trip_ever;
- reg_ctrl[14] <= reg_apb_complete_0_2;
- reg_ctrl[15] <= reg_eth_stat_rx_packet_bad_fcs_ever;
reg_ctrl[16] <= mailbox_interrupt_0;
reg_ctrl[17] <= mailbox_interrupt_1;
reg_ctrl[31:24] <= reg_host_writer_err;
@@ -542,31 +517,6 @@ always @(posedge clk) begin
end
end
-always @ (posedge clk) begin
- reg_eth_stat_rx_status_1 <= eth_stat_rx_status;
- reg_eth_stat_rx_status_2 <= reg_eth_stat_rx_status_1;
-
- reg_eth_stat_rx_aligned_1 <= eth_stat_rx_aligned;
- reg_eth_stat_rx_aligned_2 <= reg_eth_stat_rx_aligned_1;
-
- reg_eth_stat_rx_packet_bad_fcs_1 <= eth_stat_rx_packet_bad_fcs;
- reg_eth_stat_rx_packet_bad_fcs_2 <= reg_eth_stat_rx_packet_bad_fcs_1;
-
- reg_eth_busy_1 <= eth_busy;
- reg_eth_busy_2 <= reg_eth_busy_1;
-
- reg_apb_complete_0_1 <= apb_complete_0;
- reg_apb_complete_0_2 <= reg_apb_complete_0_1;
-
- reg_hbm_temperature_1 <= hbm_temperature;
- reg_hbm_temperature_2 <= reg_hbm_temperature_1;
- reg_hbm_temperature <= reg_hbm_temperature_2;
-
- reg_hbm_temp_trip_1 <= hbm_temp_trip;
- reg_hbm_temp_trip_2 <= reg_hbm_temp_trip_1;
- reg_hbm_temp_trip <= reg_hbm_temp_trip_2;
-end
-
always @ (posedge clk) begin
if (!resetn)
begin
@@ -604,22 +554,6 @@ always @ (posedge clk) begin
end
end
-// HBM temperature trip is only cleared on card restart to protect the card
-always @ (posedge clk) begin
- if (!resetn)
- reg_hbm_temp_trip_ever <= 0;
- else if (reg_hbm_temp_trip_2)
- reg_hbm_temp_trip_ever <= 1;
-end
-
-// Ethernet RX packet bad FCS is kept from last reset
-always @ (posedge clk) begin
- if (!resetn)
- reg_eth_stat_rx_packet_bad_fcs_ever <= 0;
- else if (reg_eth_stat_rx_packet_bad_fcs_2)
- reg_eth_stat_rx_packet_bad_fcs_ever <= 1;
-end
-
// FIFO status
always @(posedge clk) begin
if (!resetn)
@@ -632,10 +566,10 @@ always @(posedge clk) begin
reg_fifo_status[3] <= calib_addr_fifo_full;
reg_fifo_status[6] <= udp_fifo_empty;
reg_fifo_status[7] <= udp_fifo_full;
- reg_fifo_status[8] <= host_mem_data_fifo_empty;
- reg_fifo_status[9] <= host_mem_data_fifo_full;
- reg_fifo_status[10] <= host_mem_cmd_fifo_empty;
- reg_fifo_status[11] <= host_mem_cmd_fifo_full;
+ reg_fifo_status[8] <= c2h_data_fifo_empty;
+ reg_fifo_status[9] <= c2h_data_fifo_full;
+ reg_fifo_status[10] <= c2h_cmd_fifo_empty;
+ reg_fifo_status[11] <= c2h_cmd_fifo_full;
reg_fifo_status[12] <= work_req_fifo_empty;
reg_fifo_status[13] <= work_req_fifo_full;
reg_fifo_status[14] <= work_compl_fifo_empty;
@@ -644,10 +578,15 @@ always @(posedge clk) begin
reg_fifo_status[17] <= last_data_fifo_full;
reg_fifo_status[18] <= last_addr_fifo_empty;
reg_fifo_status[19] <= last_addr_fifo_full;
+ reg_fifo_status[20] <= h2c_data_fifo_empty;
+ reg_fifo_status[21] <= h2c_data_fifo_full;
+ reg_fifo_status[22] <= h2c_cmd_fifo_empty;
+ reg_fifo_status[23] <= h2c_cmd_fifo_full;
+ reg_fifo_status[24] <= frame_generator_fifo_full;
+ reg_fifo_status[25] <= frame_generator_fifo_empty;
+ reg_fifo_status[26] <= eth_in_fifo_full;
+ reg_fifo_status[27] <= eth_in_fifo_empty;
end
end
-assign qsfp_led_conn = !reg_eth_stat_rx_status_2;
-assign qsfp_led_busy = !reg_eth_busy_2;
-
endmodule
diff --git a/receiver/hdl/action_wrapper.v b/fpga/hdl/action_wrapper.v
similarity index 99%
rename from receiver/hdl/action_wrapper.v
rename to fpga/hdl/action_wrapper.v
index 7d0c118e..955e8419 100644
--- a/receiver/hdl/action_wrapper.v
+++ b/fpga/hdl/action_wrapper.v
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0
+// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1 ps / 1 ps
diff --git a/receiver/hdl/check_datamover_error.v b/fpga/hdl/check_datamover_error.v
similarity index 92%
rename from receiver/hdl/check_datamover_error.v
rename to fpga/hdl/check_datamover_error.v
index 5d98db12..11b17860 100644
--- a/receiver/hdl/check_datamover_error.v
+++ b/fpga/hdl/check_datamover_error.v
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0
+// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1ns / 1ps
diff --git a/receiver/hdl/check_eth_busy.v b/fpga/hdl/check_eth_busy.v
similarity index 96%
rename from receiver/hdl/check_eth_busy.v
rename to fpga/hdl/check_eth_busy.v
index 9f908e6f..0f9abaa5 100644
--- a/receiver/hdl/check_eth_busy.v
+++ b/fpga/hdl/check_eth_busy.v
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0
+// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1ns / 1ps
diff --git a/receiver/hdl/gen_xdma_descriptor.v b/fpga/hdl/gen_xdma_descriptor.v
similarity index 95%
rename from receiver/hdl/gen_xdma_descriptor.v
rename to fpga/hdl/gen_xdma_descriptor.v
index 14221dba..1ade4b72 100644
--- a/receiver/hdl/gen_xdma_descriptor.v
+++ b/fpga/hdl/gen_xdma_descriptor.v
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0
+// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1ns / 1ps
diff --git a/receiver/hdl/refclk300to100.v b/fpga/hdl/refclk300to100.v
similarity index 84%
rename from receiver/hdl/refclk300to100.v
rename to fpga/hdl/refclk300to100.v
index 7a850bce..7fc8a907 100644
--- a/receiver/hdl/refclk300to100.v
+++ b/fpga/hdl/refclk300to100.v
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0
+// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1ns / 1ps
diff --git a/receiver/hdl/resetn_sync.v b/fpga/hdl/resetn_sync.v
similarity index 88%
rename from receiver/hdl/resetn_sync.v
rename to fpga/hdl/resetn_sync.v
index 920363a1..9825a723 100644
--- a/receiver/hdl/resetn_sync.v
+++ b/fpga/hdl/resetn_sync.v
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0
+// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1ns / 1ps
diff --git a/receiver/hls/CMakeLists.txt b/fpga/hls/CMakeLists.txt
similarity index 88%
rename from receiver/hls/CMakeLists.txt
rename to fpga/hls/CMakeLists.txt
index 098f9084..72a190e5 100644
--- a/receiver/hls/CMakeLists.txt
+++ b/fpga/hls/CMakeLists.txt
@@ -5,14 +5,15 @@ ADD_LIBRARY( HLSSimulation STATIC
hls_jfjoch.h
../../common/Definitions.h
load_calibration.cpp
- internal_packet_generator.cpp
host_writer.cpp
ethernet.cpp
ipv4.cpp
icmp.cpp arp.cpp
ip_header_checksum.h
udp.cpp
- sls_detector.cpp)
+ sls_detector.cpp
+ frame_generator.cpp
+ stream_merge.cpp)
TARGET_INCLUDE_DIRECTORIES(HLSSimulation PUBLIC ../include)
TARGET_LINK_LIBRARIES(HLSSimulation CommonFunctions)
@@ -34,31 +35,31 @@ ENDFUNCTION(MAKE_HLS_MODULE)
MAKE_HLS_MODULE(data_collection_fsm.cpp data_collection_fsm)
MAKE_HLS_MODULE(timer.cpp timer_host)
-MAKE_HLS_MODULE(timer.cpp timer_hbm)
MAKE_HLS_MODULE(jf_conversion.cpp jf_conversion)
MAKE_HLS_MODULE(load_calibration.cpp load_calibration)
MAKE_HLS_MODULE(host_writer.cpp host_writer)
-MAKE_HLS_MODULE(internal_packet_generator.cpp internal_packet_generator)
MAKE_HLS_MODULE(icmp.cpp icmp)
MAKE_HLS_MODULE(ipv4.cpp ipv4)
MAKE_HLS_MODULE(ethernet.cpp ethernet)
MAKE_HLS_MODULE(arp.cpp arp)
MAKE_HLS_MODULE(udp.cpp udp)
MAKE_HLS_MODULE(sls_detector.cpp sls_detector)
+MAKE_HLS_MODULE(frame_generator.cpp frame_generator)
+MAKE_HLS_MODULE(stream_merge.cpp stream_merge)
SET (HLS_IPS psi_ch_hls_data_collection_fsm_1_0.zip
psi_ch_hls_timer_host_1_0.zip
- psi_ch_hls_timer_hbm_1_0.zip
psi_ch_hls_jf_conversion_1_0.zip
psi_ch_hls_load_calibration_1_0.zip
- psi_ch_hls_internal_packet_generator_1_0.zip
psi_ch_hls_ethernet_1_0.zip
psi_ch_hls_ipv4_1_0.zip
psi_ch_hls_arp_1_0.zip
psi_ch_hls_udp_1_0.zip
psi_ch_hls_sls_detector_1_0.zip
psi_ch_hls_icmp_1_0.zip
- psi_ch_hls_host_writer_1_0.zip)
+ psi_ch_hls_host_writer_1_0.zip
+ psi_ch_hls_frame_generator_1_0.zip
+ psi_ch_hls_stream_merge_1_0.zip)
SET (HLS_IPS ${HLS_IPS} PARENT_SCOPE)
ADD_CUSTOM_TARGET(hls DEPENDS ${HLS_IPS})
diff --git a/receiver/hls/arp.cpp b/fpga/hls/arp.cpp
similarity index 97%
rename from receiver/hls/arp.cpp
rename to fpga/hls/arp.cpp
index 70dbd9b5..9abaa612 100644
--- a/receiver/hls/arp.cpp
+++ b/fpga/hls/arp.cpp
@@ -1,5 +1,5 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
+
#include "hls_jfjoch.h"
diff --git a/receiver/hls/data_collection_fsm.cpp b/fpga/hls/data_collection_fsm.cpp
similarity index 85%
rename from receiver/hls/data_collection_fsm.cpp
rename to fpga/hls/data_collection_fsm.cpp
index db921757..a4688336 100644
--- a/receiver/hls/data_collection_fsm.cpp
+++ b/fpga/hls/data_collection_fsm.cpp
@@ -1,13 +1,12 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
+
-#include
#include "hls_jfjoch.h"
void data_collection_fsm(AXI_STREAM ð_in,
STREAM_512 &data_out,
- hls::stream > &addr_in,
- hls::stream > &addr_out,
+ hls::stream &addr_in,
+ hls::stream &addr_out,
volatile ap_uint<1> &in_run,
volatile ap_uint<1> &in_cancel,
volatile ap_uint<1> &out_idle,
@@ -15,7 +14,8 @@ void data_collection_fsm(AXI_STREAM ð_in,
ap_uint<32> one_over_energy,
ap_uint<32> nframes,
ap_uint<8> nmodules,
- ap_uint<4> nstorage_cells) {
+ ap_uint<4> nstorage_cells,
+ ap_uint<32> hbm_size_bytes) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE axis register both port=eth_in
@@ -31,12 +31,13 @@ void data_collection_fsm(AXI_STREAM ð_in,
#pragma HLS INTERFACE ap_none register port=nframes
#pragma HLS INTERFACE ap_none register port=nmodules
#pragma HLS INTERFACE ap_none register port=nstorage_cells
+#pragma HLS INTERFACE ap_none register port=hbm_size_bytes
#pragma HLS PIPELINE II=1 style=flp
packet_512_t packet_in;
packet_512_t packet_out;
- ap_uint addr;
+ axis_addr addr;
enum rcv_state_t {RCV_WAIT_FOR_START = 0, RCV_WAIT_FOR_START_LOW = 1, RCV_START = 2, RCV_INIT = 3, RCV_GOOD = 4,
RCV_FLUSH = 5, RCV_LAST = 6, RCV_FLUSH_IDLE = 7, RCV_IGNORE = 8};
@@ -76,21 +77,18 @@ void data_collection_fsm(AXI_STREAM ð_in,
ACT_REG_NFRAMES(packet_out.data) = nframes;
ACT_REG_NMODULES(packet_out.data) = nmodules;
ACT_REG_NSTORAGE_CELLS(packet_out.data) = nstorage_cells + 1;
+ ACT_REG_HBM_SIZE_256b(packet_out.data) = hbm_size_bytes / 32;
+
packet_out.user = 0;
packet_out.last = 0;
packet_out.dest = 0;
packet_out.id = 1;
data_out << packet_out;
- addr = 0;
- addr(63, 0) = mode;
- addr(79,64) = nmodules;
+ addr.last = 0;
addr_out << addr;
- if (mode & MODE_INTERNAL_PACKET_GEN)
- rcv_state = RCV_LAST;
- else
- rcv_state = RCV_INIT;
+ rcv_state = RCV_INIT;
break;
case RCV_INIT:
out_idle = 0;
@@ -99,7 +97,7 @@ void data_collection_fsm(AXI_STREAM ð_in,
else if (!addr_in.empty()) {
addr_in >> addr;
- if (addr_frame_number(addr) >= nframes + DELAY_FRAMES_STOP_AND_QUIT)
+ if (addr.frame_number >= nframes + DELAY_FRAMES_STOP_AND_QUIT)
rcv_state = RCV_FLUSH;
else {
addr_out << addr;
@@ -130,8 +128,7 @@ void data_collection_fsm(AXI_STREAM ð_in,
break;
case RCV_LAST:
out_idle = 0;
- addr = 0;
- addr_last_flag(addr) = 1;
+ addr.last = 1;
addr_out << addr;
// Finish data collection
diff --git a/receiver/include/datamover_model.h b/fpga/hls/datamover_model.h
similarity index 96%
rename from receiver/include/datamover_model.h
rename to fpga/hls/datamover_model.h
index 603eabff..f01938e5 100644
--- a/receiver/include/datamover_model.h
+++ b/fpga/hls/datamover_model.h
@@ -1,11 +1,10 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_DATAMOVER_MODEL_H
#define JUNGFRAUJOCH_DATAMOVER_MODEL_H
-#include "../hls/hls_jfjoch.h"
#include
+#include "hls_jfjoch.h"
enum class Direction {Input, Output};
@@ -84,4 +83,5 @@ public:
hls::stream >& GetDataStream() { return data; }
~Datamover() { Stop(); }
};
+
#endif //JUNGFRAUJOCH_DATAMOVER_MODEL_H
diff --git a/receiver/hls/ethernet.cpp b/fpga/hls/ethernet.cpp
similarity index 85%
rename from receiver/hls/ethernet.cpp
rename to fpga/hls/ethernet.cpp
index 9030761c..2cb7719a 100644
--- a/receiver/hls/ethernet.cpp
+++ b/fpga/hls/ethernet.cpp
@@ -1,5 +1,5 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
+
#include "hls_jfjoch.h"
@@ -37,10 +37,9 @@ void ethernet(AXI_STREAM ð_in,
if (state == INSPECT_HEADER) {
dest = DEST_IGNORE;
if (fpga_mac_addr != 0) {
- ap_uint < 48 > dest_mac = get_mac_addr(packet_in.data, 0);
- ap_uint < 48 > src_mac = get_mac_addr(packet_in.data, 48);
-
- ap_uint < 16 > ether_type = get_header_field_16(packet_in.data, 12 * 8);
+ ap_uint<48> dest_mac = packet_in.data(47, 0);
+ ap_uint<48> src_mac = packet_in.data(95, 48);
+ ap_uint<16> ether_type = get_header_field_16(packet_in.data, 12 * 8);
if ((dest_mac == fpga_mac_addr) && (ether_type == ETHER_IP)) {
state = FORWARD;
diff --git a/fpga/hls/frame_generator.cpp b/fpga/hls/frame_generator.cpp
new file mode 100644
index 00000000..ce3e8218
--- /dev/null
+++ b/fpga/hls/frame_generator.cpp
@@ -0,0 +1,117 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#include "hls_jfjoch.h"
+#include "ip_header_checksum.h"
+
+void generate_packet(STREAM_512 &data_out,
+ ap_uint<512> *uram,
+ ap_uint<32> frame,
+ ap_uint<8> module,
+ ap_uint<7> eth_packet,
+ ap_uint<48> src_mac_addr,
+ ap_uint<48> dest_mac_addr,
+ ap_uint<32> src_ipv4_addr,
+ ap_uint<32> dest_ipv4_addr,
+ ap_uint<64> bunchid,
+ ap_uint<32> exptime,
+ ap_uint<64> timestamp,
+ ap_uint<32> debug) {
+#pragma HLS PIPELINE II=130
+ ap_uint<720> header = 0;
+
+ header(47 , 0) = dest_mac_addr;
+ header(95 , 48) = src_mac_addr;
+ header(111, 96) = 0x0008; // ETHER_IP = IPv4
+ header(eth_payload_pos+3 , eth_payload_pos ) = 0x5; // header len of 5
+ header(eth_payload_pos+7 , eth_payload_pos+4 ) = 0x4; // IPv4
+ header(eth_payload_pos+31 , eth_payload_pos+16 ) = 0x4C20; // total length = 8268
+ header(eth_payload_pos+79 , eth_payload_pos+72 ) = PROTOCOL_UDP; // UDP
+ header(eth_payload_pos+127, eth_payload_pos+96 ) = src_ipv4_addr;
+ header(eth_payload_pos+159, eth_payload_pos+128) = dest_ipv4_addr;
+ header(eth_payload_pos+95 , eth_payload_pos+80 ) = computeCheckSum20B(header(eth_payload_pos + 159, eth_payload_pos));
+
+ header(ipv4_payload_pos+47, ipv4_payload_pos+32) = 0x3820; // UDP length = 8248
+ header(udp_payload_pos+63, udp_payload_pos) = frame + 1;
+ header(udp_payload_pos+95, udp_payload_pos+64) = exptime;
+ header(udp_payload_pos+127, udp_payload_pos+96) = eth_packet;
+ header(udp_payload_pos+2*64+63, udp_payload_pos+2*64) = bunchid;
+ header(udp_payload_pos+3*64+63, udp_payload_pos+3*64) = timestamp;
+ header(udp_payload_pos+4*64+31, udp_payload_pos+4*64+16) = 2 * module;
+ header(udp_payload_pos+5*64+31, udp_payload_pos+5*64) = debug;
+
+ packet_512_t packet;
+ packet.data = header(511 ,0);
+ packet.last = 0;
+ packet.dest = 0;
+ packet.id = 0;
+ packet.strb = UINT64_MAX;
+ packet.keep = UINT64_MAX;
+ packet.user = 0;
+
+ data_out << packet;
+
+ ap_uint<208> remainder = header(719, 512);
+ for (int i = 0; i < 128; i++) {
+ ap_uint<512> tmp = uram[eth_packet * 128 + i];
+ //tmp(255, 0) = d_hbm_p0[eth_packet * 128 + i];
+ //tmp(511, 256) = d_hbm_p1[eth_packet * 128 + i];
+ packet.data(207, 0) = remainder;
+ packet.data(511, 208) = tmp(303, 0);
+ data_out << packet;
+ remainder = tmp(511, 304);
+ }
+ packet.data(207, 0) = remainder;
+ packet.data(511, 208) = 0;
+ packet.keep(63, 26) = 0;
+ packet.last = 1;
+ data_out << packet;
+}
+
+void frame_generator(STREAM_512 &data_out,
+ ap_uint<512> *uram,
+ ap_uint<32> frames,
+ ap_uint<5> modules,
+ ap_uint<48> src_mac_addr,
+ ap_uint<48> dest_mac_addr,
+ ap_uint<32> src_ipv4_addr,
+ ap_uint<32> dest_ipv4_addr,
+ ap_uint<64> bunchid,
+ ap_uint<32> exptime,
+ ap_uint<32> debug) {
+#pragma HLS INTERFACE mode=s_axilite port=return
+#pragma HLS INTERFACE mode=s_axilite port=frames
+#pragma HLS INTERFACE mode=s_axilite port=modules
+#pragma HLS INTERFACE mode=s_axilite port=bunchid
+#pragma HLS INTERFACE mode=s_axilite port=exptime
+#pragma HLS INTERFACE mode=s_axilite port=debug
+#pragma HLS INTERFACE mode=s_axilite port=dest_mac_addr
+#pragma HLS INTERFACE mode=s_axilite port=dest_ipv4_addr
+#pragma HLS INTERFACE mode=ap_none port=src_mac_addr
+#pragma HLS INTERFACE mode=ap_none port=src_ipv4_addr
+
+#pragma HLS INTERFACE register both axis port=data_out
+#pragma HLS INTERFACE m_axi port=uram bundle=uram depth=512 offset=off \
+ max_read_burst_length=64 max_write_burst_length=2 latency=5 num_write_outstanding=2 num_read_outstanding=2
+//#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \
+// max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
+//#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
+// max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
+
+ for (uint32_t f = 0; f < frames; f++) {
+ for (uint32_t p = 0; p < 128; p++) {
+ for (uint32_t m = 0; m < modules; m++) {
+ generate_packet(data_out,
+ uram,
+ f, m, p,
+ src_mac_addr,
+ dest_mac_addr,
+ src_ipv4_addr,
+ dest_ipv4_addr,
+ bunchid + f,
+ exptime,
+ exptime * f,
+ debug);
+ }
+ }
+ }
+}
diff --git a/receiver/hls/hls_jfjoch.h b/fpga/hls/hls_jfjoch.h
similarity index 68%
rename from receiver/hls/hls_jfjoch.h
rename to fpga/hls/hls_jfjoch.h
index 7ac8519f..d8994d48 100644
--- a/receiver/hls/hls_jfjoch.h
+++ b/fpga/hls/hls_jfjoch.h
@@ -1,5 +1,5 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
+
#ifndef JUNGFRAUJOCH_HLS_JFJOCH_H
#define JUNGFRAUJOCH_HLS_JFJOCH_H
@@ -14,7 +14,7 @@
#include
#else
#include "../include/hls_burst_maxi.h"
-#include
+#include "parallel_stream.h"
#endif
#include "../../common/Definitions.h"
@@ -22,8 +22,6 @@
// Number of modules that can be simultaneously handled by the FPGA
#define MAX_MODULES_FPGA 16
-#define ADDR_STREAM_WIDTH 320
-
typedef ap_ufixed<16,2, AP_RND_CONV> gainG0_t;
typedef ap_ufixed<16,4, AP_RND_CONV> gainG1_t;
typedef ap_ufixed<16,6, AP_RND_CONV> gainG2_t;
@@ -50,48 +48,68 @@ typedef ap_axiu<512,1, 1, 1> packet_512_t;
typedef hls::stream AXI_STREAM;
typedef hls::stream STREAM_512;
-#define addr_frame_number(x) x(63, 0)
-#define addr_eth_packet(x) x(70, 64)
-#define addr_module(x) x(76, 72)
-#define addr_last_flag(x) x[79]
-#define addr_jf_debug(x) x(127, 96)
-#define addr_timestamp(x) x(191,128)
-#define addr_bunch_id(x) x(255,192)
-#define addr_exptime(x) x(256+63, 256)
-
-#define ACT_REG_MODE(x) ((x)(63, 0)) // 64 bit
-#define ACT_REG_ONE_OVER_ENERGY(x) ((x)(95, 64)) // 32 bit
-#define ACT_REG_NFRAMES(x) ((x)(127, 96)) // 32 bit
+#define ACT_REG_MODE(x) ((x)(32 , 0)) // 32 bit
+#define ACT_REG_ONE_OVER_ENERGY(x) ((x)(63 , 32)) // 32 bit
+#define ACT_REG_NFRAMES(x) ((x)(95 , 64)) // 32 bit
#define ACT_REG_NMODULES(x) ((x)(132, 128)) // 5 bit (0..31)
#define ACT_REG_NSTORAGE_CELLS(x) ((x)(148, 144)) // 5 bit
+#define ACT_REG_HBM_SIZE_256b(x) ((x)(191, 160)) // 32 bit
struct axis_datamover_ctrl {
ap_uint<40+64> data;
};
+struct axis_addr {
+ ap_uint<64> frame_number;
+ ap_uint<64> exptime;
+ ap_uint<64> timestamp;
+ ap_uint<64> bunchid;
+ ap_uint<32> debug;
+ ap_uint<5> module;
+ ap_uint<7> eth_packet;
+ ap_uint<1> last;
+};
+
void setup_datamover (hls::stream &datamover_cmd_stream, uint64_t address, size_t bytes_to_write);
void data_collection_fsm(AXI_STREAM ð_in,
STREAM_512 &data_out,
- hls::stream > &addr_in,
- hls::stream > &addr_out,
+ hls::stream &addr_in,
+ hls::stream &addr_out,
volatile ap_uint<1> &in_run,
volatile ap_uint<1> &in_cancel,
volatile ap_uint<1> &out_idle,
ap_uint<32> mode,
ap_uint<32> one_over_energy,
- ap_uint<32> frames_per_trigger,
+ ap_uint<32> nframes,
ap_uint<8> nmodules,
- ap_uint<4> nstorage_cells);
+ ap_uint<4> nstorage_cells,
+ ap_uint<32> hbm_size_bytes);
-void load_calibration(STREAM_512 &data_in, STREAM_512 &data_out,
+void load_calibration(ap_uint<256> *d_hbm_p0,
+ ap_uint<256> *d_hbm_p1,
+ ap_uint<8> modules,
+ ap_uint<5> storage_cells,
+ ap_uint<32> hbm_size_bytes,
hls::stream &datamover_in_cmd,
hls::stream > &host_memory_in,
uint64_t in_mem_location[LOAD_CALIBRATION_BRAM_SIZE]);
+void frame_generator(STREAM_512 &data_out,
+ ap_uint<512> *uram,
+ ap_uint<32> frames,
+ ap_uint<5> modules,
+ ap_uint<48> src_mac_addr,
+ ap_uint<48> dest_mac_addr,
+ ap_uint<32> src_ipv4_addr,
+ ap_uint<32> dest_ipv4_addr,
+ ap_uint<64> bunchid,
+ ap_uint<32> exptime,
+ ap_uint<32> debug);
+
void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out,
- hls::stream > &addr_in,
- hls::stream > &addr_out,
+ hls::stream &addr_in,
+ hls::stream &addr_out,
hls::burst_maxi d_hbm_p0, hls::burst_maxi d_hbm_p1,
hls::burst_maxi d_hbm_p2, hls::burst_maxi d_hbm_p3,
hls::burst_maxi d_hbm_p4, hls::burst_maxi d_hbm_p5,
@@ -100,21 +118,22 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out,
hls::burst_maxi d_hbm_p10, hls::burst_maxi d_hbm_p11);
void host_writer(STREAM_512 &data_in,
- hls::stream > &addr_in,
+ hls::stream &addr_in,
hls::stream > &host_memory_out,
hls::stream &datamover_out_cmd,
hls::stream > &s_axis_work_request,
hls::stream > &m_axis_completion,
volatile uint64_t &packets_processed,
+ volatile ap_uint<1> &idle,
ap_uint<8> &err_reg);
-void timer_hbm(STREAM_512 &in, STREAM_512 &data_out, uint64_t &counter);
-void timer_host(STREAM_512 &data_in, STREAM_512 &data_out, uint64_t &counter);
+void timer_host(STREAM_512 &data_in,
+ STREAM_512 &data_out,
+ volatile uint64_t &counter);
-void internal_packet_generator(STREAM_512 &data_in, STREAM_512 &data_out,
- hls::stream > &addr_in,
- hls::stream > &addr_out,
- volatile ap_uint<1> &in_cancel);
+void stream_merge(AXI_STREAM &input_0,
+ AXI_STREAM &input_1,
+ AXI_STREAM &output);
template ap_uint pack32(ap_int in[32]) {
#pragma HLS INLINE
@@ -144,25 +163,6 @@ inline void setup_datamover (hls::stream &datamover_cmd_str
datamover_cmd_stream << msg;
}
-inline ap_uint addr_packet(ap_uint<8> eth_packet,
- ap_uint<5> module,
- ap_uint<64> frame,
- ap_uint<32> jf_debug,
- ap_uint<64> timestamp,
- ap_uint<64> bunchid,
- ap_uint<32> expttime) {
-#pragma HLS INLINE
- ap_uint retval = 0;
- addr_eth_packet(retval) = eth_packet;
- addr_module(retval) = module;
- addr_frame_number(retval) = frame;
- addr_jf_debug(retval) = jf_debug;
- addr_timestamp(retval) = timestamp;
- addr_bunch_id(retval) = bunchid;
- addr_exptime(retval) = expttime;
- return retval;
-}
-
inline ap_uint<16> get_header_field_16(ap_uint<512> data, size_t position) {
ap_uint<16> tmp = data(position+15, position);
ap_uint<16> retval;
@@ -172,14 +172,6 @@ inline ap_uint<16> get_header_field_16(ap_uint<512> data, size_t position) {
return retval;
}
-inline ap_uint<48> get_mac_addr(ap_uint<512> data, size_t position) {
- return data(position+47,position);
-}
-
-inline ap_uint<32> get_header_field_32_network_order(ap_uint<512> data, size_t position) {
- return data(position+31, position);
-}
-
static const uint8_t ECHO_REQUEST = 0x08;
static const uint8_t ECHO_REPLY = 0x00;
static const uint8_t PROTOCOL_ICMP = 0x01;
@@ -192,7 +184,6 @@ static const uint32_t eth_payload_pos = 14 * 8; // 112 bits
static const uint32_t ipv4_payload_pos = eth_payload_pos + 160; // 112 + 160 = 272 bits
static const uint32_t udp_payload_pos = ipv4_payload_pos + 64; // 112 + 160 + 64 = 336 bits (42 bytes)
-
// Network cores
#define UDP_METADATA_STREAM_WIDTH 48
#define udp_metadata_dest_port(x) x(15, 0)
@@ -231,10 +222,9 @@ void udp(AXI_STREAM ð_in,
void sls_detector(AXI_STREAM &udp_payload_in,
hls::stream > &udp_metadata_in,
AXI_STREAM &data_out,
- hls::stream > &addr_out,
+ hls::stream &addr_out,
uint64_t& counter,
uint32_t& counter_eth_error,
uint32_t& counter_len_error,
volatile ap_uint<1> &in_clear_counters);
-
#endif
diff --git a/receiver/hls/host_writer.cpp b/fpga/hls/host_writer.cpp
similarity index 53%
rename from receiver/hls/host_writer.cpp
rename to fpga/hls/host_writer.cpp
index 13898579..284c7b45 100644
--- a/receiver/hls/host_writer.cpp
+++ b/fpga/hls/host_writer.cpp
@@ -1,5 +1,5 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
+
#include "hls_jfjoch.h"
@@ -10,44 +10,48 @@
#define PACKET_SIZE 8192
inline void write_completion(hls::stream > &m_axis_completion,
- const ap_uint<32> &handle,
- const ap_uint<8> &module,
- const ap_uint<64> &frame_num,
- const ap_uint<256> &packet_mask,
- const ap_uint<16> &packet_count,
- const ap_uint<32> &debug,
- const ap_uint<64> ×tamp,
- const ap_uint<64> &bunchid,
- const ap_uint<32> &exptime) {
+ const ap_uint<32> &handle,
+ const ap_uint<8> &module_number,
+ const ap_uint<64> &frame_num,
+ const ap_uint<128> &packet_mask,
+ const ap_uint<16> &packet_count,
+ const ap_uint<32> &debug,
+ const ap_uint<64> ×tamp,
+ const ap_uint<64> &bunchid,
+ const ap_uint<32> &exptime,
+ const ap_uint<32> &data_collection_id,
+ const ap_uint<1> &flushing) {
#pragma HLS INLINE
ap_uint<1> all_packets_ok = packet_mask.and_reduce();
ap_uint<1> any_packets_received = packet_mask.or_reduce();
ap_uint<8> status = 0;
status[0] = all_packets_ok;
status[1] = any_packets_received;
-
- ap_uint<128> tmp = (handle, packet_count, status, module, frame_num);
+ status[2] = flushing;
+ ap_uint<128> tmp = (handle, packet_count, status, module_number, frame_num);
status[7] = tmp.xor_reduce(); // ensure completion has even parity
- m_axis_completion << handle;
- m_axis_completion << (packet_count, status, module);
- m_axis_completion << frame_num(63, 32);
- m_axis_completion << frame_num(31, 0);
+ if (handle != HANDLE_SKIP_FRAME) {
+ m_axis_completion << handle;
+ m_axis_completion << (packet_count, status, module_number);
+ m_axis_completion << frame_num(63, 32);
+ m_axis_completion << frame_num(31, 0);
- m_axis_completion << timestamp(63,32);
- m_axis_completion << timestamp(31,0);
- m_axis_completion << bunchid(63,32);
- m_axis_completion << bunchid(31,0);
+ m_axis_completion << timestamp(63,32);
+ m_axis_completion << timestamp(31,0);
+ m_axis_completion << bunchid(63,32);
+ m_axis_completion << bunchid(31,0);
- m_axis_completion << exptime;
- m_axis_completion << debug;
- m_axis_completion << 0;
- m_axis_completion << 0;
+ m_axis_completion << exptime;
+ m_axis_completion << debug;
+ m_axis_completion << 0;
+ m_axis_completion << data_collection_id;
- m_axis_completion << packet_mask(127,96);
- m_axis_completion << packet_mask( 95,64);
- m_axis_completion << packet_mask( 63,32);
- m_axis_completion << packet_mask( 31, 0);
+ m_axis_completion << packet_mask(127,96);
+ m_axis_completion << packet_mask( 95,64);
+ m_axis_completion << packet_mask( 63,32);
+ m_axis_completion << packet_mask( 31, 0);
+ }
}
@@ -74,12 +78,13 @@ inline ap_uint<1> read_request(hls::stream > &s_axis_work_request,
}
void host_writer(STREAM_512 &data_in,
- hls::stream > &addr_in,
+ hls::stream &addr_in,
hls::stream > &host_memory_out,
hls::stream &datamover_out_cmd,
hls::stream > &s_axis_work_request,
hls::stream > &m_axis_completion,
volatile uint64_t &packets_processed,
+ volatile ap_uint<1> &idle,
ap_uint<8> &err_reg) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE register both axis port=data_in
@@ -90,15 +95,7 @@ void host_writer(STREAM_512 &data_in,
#pragma HLS INTERFACE register both axis port=s_axis_work_request
#pragma HLS INTERFACE register ap_vld port=packets_processed
#pragma HLS INTERFACE register ap_vld port=err_reg
-
- ap_uint addr;
- addr_in >> addr;
-
- packet_512_t packet_in;
- data_in >> packet_in;
-
- ap_uint<8> internal_err_reg = 0;
- err_reg = internal_err_reg;
+#pragma HLS INTERFACE register ap_none port=idle
ap_uint<128> packet_mask[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=packet_mask core=RAM_1P
@@ -119,6 +116,8 @@ void host_writer(STREAM_512 &data_in,
ap_uint<64> curr_offset[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=curr_offset core=RAM_1P
+ idle = 1;
+
for (int i = 0; i < MAX_MODULES_FPGA*2; i++) {
#pragma HLS UNROLL
curr_frame[i] = UINT64_MAX;
@@ -132,8 +131,32 @@ void host_writer(STREAM_512 &data_in,
jf_bunchid[i] = 0;
}
- write_completion(m_axis_completion, UINT32_MAX - 1, 0, 0, 0, 0, 0, 0, 0, 0);
+ ap_uint<32> req_handle;
+ ap_uint<64> req_host_offset;
+ while (data_in.empty()) {
+#pragma HLS PIPELINE II=4
+ if (!s_axis_work_request.empty())
+ read_request(s_axis_work_request, req_handle, req_host_offset);
+ }
+
+ axis_addr addr;
+ addr_in >> addr;
+
+ packet_512_t packet_in;
+ data_in >> packet_in;
+ ap_uint<5> nmodules = ACT_REG_NMODULES(packet_in.data);
+ ap_uint<32> data_collection_mode = ACT_REG_MODE(packet_in.data);
+ ap_uint<32> data_collection_id = data_collection_mode(31, 16); // upper 16-bit of mode
+
+ ap_uint<1> mode_nonblocking = (data_collection_mode & MODE_NONBLOCKING_ON_WR) ? 1 : 0;
+
+ ap_uint<8> internal_err_reg = 0;
+ err_reg = internal_err_reg;
+
+ write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id, 0);
+
+ idle = 0;
uint64_t total_counter = 0;
packets_processed = 0;
addr_in >> addr;
@@ -144,28 +167,15 @@ void host_writer(STREAM_512 &data_in,
packet_out.dest = 0;
packet_out.id = 0;
packet_out.user = 0;
-
- ap_uint<32> req_handle;
- ap_uint<64> req_host_offset;
Loop_good_packet:
- while (!addr_last_flag(addr)) {
+ while (!addr.last) {
// Process one UDP packet per iteration
#pragma HLS PIPELINE II=128
- ap_uint<64> frame_number = addr_frame_number(addr);
- ap_uint<4> module = addr_module(addr);
- ap_uint<7> eth_packet = addr_eth_packet(addr);
- ap_uint<5> id = module * 2 + (frame_number % 2);
-
- for (int i = 0; i < 128; i++) {
- data_in >> packet_in;
- packet_out.data = packet_in.data;
- packet_out.last = packet_in.last;
- host_memory_out << packet_out;
- }
-
- if (packet_in.last != 1)
- internal_err_reg[1] = 1;
+ ap_uint<64> frame_number = addr.frame_number;
+ ap_uint<4> module_number = addr.module;
+ ap_uint<7> eth_packet = addr.eth_packet;
+ ap_uint<5> id = module_number * 2 + (frame_number % 2);
if (curr_frame[id] != frame_number) {
if (packet_mask[id] != 0) {
@@ -178,26 +188,37 @@ void host_writer(STREAM_512 &data_in,
ap_uint<64> comp_bunchid = jf_bunchid[id];
ap_uint<32> comp_exptime = exptime[id];
- write_completion(m_axis_completion, comp_handle, module,
+ write_completion(m_axis_completion, comp_handle, module_number,
comp_frame, comp_packet_mask, comp_packet_count,
comp_debug, comp_timestamp, comp_bunchid,
- comp_exptime);
+ comp_exptime, data_collection_id, 0);
}
- if (read_request(s_axis_work_request, req_handle, req_host_offset))
- internal_err_reg[2] = 1;
-
- if (req_handle == UINT32_MAX)
- internal_err_reg[4] = 1;
+ if (module_number >= nmodules) {
+ req_handle = HANDLE_SKIP_FRAME;
+ req_host_offset = 0;
+ internal_err_reg[5] = 1;
+ } else if (s_axis_work_request.empty() && mode_nonblocking) {
+ req_handle = HANDLE_SKIP_FRAME;
+ req_host_offset = 0;
+ } else {
+ if (read_request(s_axis_work_request, req_handle, req_host_offset))
+ internal_err_reg[2] = 1;
+ if (req_handle >= HANDLE_SKIP_FRAME) {
+ req_handle = HANDLE_SKIP_FRAME;
+ req_host_offset = 0;
+ internal_err_reg[4] = 1;
+ }
+ }
handle[id] = req_handle;
curr_frame[id] = frame_number;
curr_offset[id] = req_host_offset;
- debug[id] = addr_jf_debug(addr);
- timestamp[id] = addr_timestamp(addr);
- jf_bunchid[id] = addr_bunch_id(addr);
- exptime[id] = addr_exptime(addr);
+ debug[id] = addr.debug;
+ timestamp[id] = addr.timestamp;
+ jf_bunchid[id] = addr.bunchid;
+ exptime[id] = addr.exptime;
packet_mask[id] = ap_uint<128>(1) << eth_packet;
packet_count[id] = 1;
@@ -206,13 +227,31 @@ void host_writer(STREAM_512 &data_in,
packet_mask[id] |= ap_uint<128>(1) << eth_packet;
}
- size_t out_frame_addr = curr_offset[id] + eth_packet * PACKET_SIZE;
+ if (handle[id] != HANDLE_SKIP_FRAME) {
+ for (int i = 0; i < 128; i++) {
+ data_in >> packet_in;
+ packet_out.data = packet_in.data;
+ packet_out.last = packet_in.last;
+ host_memory_out << packet_out;
+ }
- if (out_frame_addr % 128 != 0) internal_err_reg[0] = 1;
- if (curr_offset[id] == 0) internal_err_reg[3] = 1;
- packets_processed = ++total_counter;
+ if (packet_in.last != 1)
+ internal_err_reg[1] = 1;
- setup_datamover(datamover_out_cmd, out_frame_addr, PACKET_SIZE);
+ size_t out_frame_addr = curr_offset[id] + eth_packet * PACKET_SIZE;
+
+ if (out_frame_addr % 128 != 0) internal_err_reg[0] = 1;
+ if (curr_offset[id] == 0) internal_err_reg[3] = 1;
+ total_counter++;
+ packets_processed = total_counter;
+ setup_datamover(datamover_out_cmd, out_frame_addr, PACKET_SIZE);
+ } else {
+ for (int i = 0; i < 128; i++)
+ data_in >> packet_in;
+
+ if (packet_in.last != 1)
+ internal_err_reg[1] = 1;
+ }
addr_in >> addr;
err_reg = internal_err_reg;
}
@@ -222,23 +261,17 @@ void host_writer(STREAM_512 &data_in,
std::this_thread::sleep_for(std::chrono::milliseconds(100));
#endif
- for (ap_uint<8> m = 0; m < MAX_MODULES_FPGA * 2; m++) {
+ for (ap_uint<8> m = 0; m < nmodules * 2; m++) {
#pragma HLS PIPELINE II=16
- if (packet_mask[m] > 0)
+ if (packet_mask[m] != 0)
write_completion(m_axis_completion, handle[m], m / 2, curr_frame[m],
packet_mask[m], packet_count[m],
debug[m], timestamp[m], jf_bunchid[m],
- exptime[m]);
+ exptime[m], data_collection_id, 1);
}
data_in >> packet_in;
- write_completion(m_axis_completion, UINT32_MAX, 0, total_counter, 0, 0, 0, 0, 0, 0);
-
- read_request(s_axis_work_request, req_handle, req_host_offset);
-
- while (req_handle != UINT32_MAX) {
-#pragma HLS PIPELINE II=4
- read_request(s_axis_work_request, req_handle, req_host_offset);
- }
+ write_completion(m_axis_completion, HANDLE_END, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id, 0);
+ idle = 1;
}
diff --git a/receiver/hls/icmp.cpp b/fpga/hls/icmp.cpp
similarity index 93%
rename from receiver/hls/icmp.cpp
rename to fpga/hls/icmp.cpp
index 563fc18a..c3f81161 100755
--- a/receiver/hls/icmp.cpp
+++ b/fpga/hls/icmp.cpp
@@ -34,7 +34,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
************************************************/
// With modifications from Paul Scherrer Insitute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+
#include "hls_jfjoch.h"
#include "ip_header_checksum.h"
@@ -111,8 +111,8 @@ void icmp(AXI_STREAM& eth_in, AXI_STREAM& eth_out, uint64_t& counter,
if (eth_in.read_nb(packet)) {
if (state == INSPECT_HEADER) {
- ap_uint < 48 > dest_mac = get_mac_addr(packet.data, 0);
- ap_uint < 48 > src_mac = get_mac_addr(packet.data, 48);
+ ap_uint<48> dest_mac = packet.data(47, 0);
+ ap_uint<48> src_mac = packet.data(95, 48);
// Swap MAC addresses for reply
packet.data(47, 0) = src_mac;
@@ -127,8 +127,8 @@ void icmp(AXI_STREAM& eth_in, AXI_STREAM& eth_out, uint64_t& counter,
if ((icmp_type == ECHO_REQUEST) && (icmp_code == 0)) {
- ap_uint < 32 > ipv4_src_ip = packet.data(eth_payload_pos + 127, eth_payload_pos + 96);
- ap_uint < 32 > ipv4_dest_ip = packet.data(eth_payload_pos + 159, eth_payload_pos + 128);
+ ap_uint<32> ipv4_src_ip = packet.data(eth_payload_pos + 127, eth_payload_pos + 96);
+ ap_uint<32> ipv4_dest_ip = packet.data(eth_payload_pos + 159, eth_payload_pos + 128);
packet.data(eth_payload_pos + 71, eth_payload_pos + 64) = 128; // IP time to live
packet.data(eth_payload_pos + 95, eth_payload_pos + 80) = 0;
diff --git a/receiver/hls/ip_header_checksum.h b/fpga/hls/ip_header_checksum.h
similarity index 97%
rename from receiver/hls/ip_header_checksum.h
rename to fpga/hls/ip_header_checksum.h
index 53adbf04..e594c8d3 100644
--- a/receiver/hls/ip_header_checksum.h
+++ b/fpga/hls/ip_header_checksum.h
@@ -34,7 +34,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
************************************************/
// With modifications from Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+
#ifndef JUNGFRAUJOCH_IP_HEADER_CHECKSUM_H
#define JUNGFRAUJOCH_IP_HEADER_CHECKSUM_H
diff --git a/receiver/hls/ipv4.cpp b/fpga/hls/ipv4.cpp
similarity index 90%
rename from receiver/hls/ipv4.cpp
rename to fpga/hls/ipv4.cpp
index 281f3b1d..eab00a9e 100644
--- a/receiver/hls/ipv4.cpp
+++ b/fpga/hls/ipv4.cpp
@@ -1,5 +1,5 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
+
#include "hls_jfjoch.h"
#include "ip_header_checksum.h"
@@ -28,7 +28,7 @@ void ipv4(AXI_STREAM ð_in,
ap_uint<4> ip_version = packet_in.data(eth_payload_pos + 8 - 1, eth_payload_pos + 4);
ap_uint<8> ipv4_protocol = packet_in.data(eth_payload_pos + 80 - 1, eth_payload_pos + 72);
- ap_uint<32> ipv4_dest_ip = get_header_field_32_network_order(packet_in.data, eth_payload_pos + 128);
+ ap_uint<32> ipv4_dest_ip = packet_in.data(eth_payload_pos + 128 + 31, eth_payload_pos + 128);
ap_uint<16> ipv4_header_checksum_check = computeCheckSum20B(packet_in.data(eth_payload_pos + 159, eth_payload_pos));
if ((ip_version == 4) && (ipv4_dest_ip == fpga_ipv4_addr) && (ipv4_header_checksum_check == 0)) {
diff --git a/receiver/hls/jf_conversion.cpp b/fpga/hls/jf_conversion.cpp
similarity index 56%
rename from receiver/hls/jf_conversion.cpp
rename to fpga/hls/jf_conversion.cpp
index 263d844f..b24d80ab 100644
--- a/receiver/hls/jf_conversion.cpp
+++ b/fpga/hls/jf_conversion.cpp
@@ -1,5 +1,5 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
+
#include "hls_jfjoch.h"
@@ -100,8 +100,8 @@ ap_uint<512> convert(ap_uint<512> data_in,
}
void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out,
- hls::stream > &addr_in,
- hls::stream > &addr_out,
+ hls::stream &addr_in,
+ hls::stream &addr_out,
hls::burst_maxi d_hbm_p0, hls::burst_maxi d_hbm_p1,
hls::burst_maxi d_hbm_p2, hls::burst_maxi d_hbm_p3,
hls::burst_maxi d_hbm_p4, hls::burst_maxi d_hbm_p5,
@@ -116,33 +116,33 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out,
#pragma HLS INTERFACE register both axis port=addr_out
#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p2 bundle=d_hbm_p2 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p3 bundle=d_hbm_p3 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p4 bundle=d_hbm_p4 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p5 bundle=d_hbm_p5 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p6 bundle=d_hbm_p6 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p7 bundle=d_hbm_p7 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p8 bundle=d_hbm_p8 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p9 bundle=d_hbm_p9 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p10 bundle=d_hbm_p10 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
#pragma HLS INTERFACE m_axi port=d_hbm_p11 bundle=d_hbm_p11 depth=512 offset=off \
- max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9
+ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9
packet_512_t packet_in;
- ap_uint addr;
+ axis_addr addr;
addr_in >> addr;
addr_out << addr;
@@ -152,6 +152,19 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out,
ap_uint<5> modules = ACT_REG_NMODULES(packet_in.data);
ap_uint<32> in_one_over_energy = ACT_REG_ONE_OVER_ENERGY(packet_in.data);
ap_uint<5> storage_cells = ACT_REG_NSTORAGE_CELLS(packet_in.data);
+ ap_uint<32> hbm_size_256b = ACT_REG_HBM_SIZE_256b(packet_in.data);
+ ap_uint<32> offset_hbm_0 = 0 * hbm_size_256b;
+ ap_uint<32> offset_hbm_1 = 1 * hbm_size_256b;
+ ap_uint<32> offset_hbm_2 = 2 * hbm_size_256b;
+ ap_uint<32> offset_hbm_3 = 3 * hbm_size_256b;
+ ap_uint<32> offset_hbm_4 = 4 * hbm_size_256b;
+ ap_uint<32> offset_hbm_5 = 5 * hbm_size_256b;
+ ap_uint<32> offset_hbm_6 = 6 * hbm_size_256b;
+ ap_uint<32> offset_hbm_7 = 7 * hbm_size_256b;
+ ap_uint<32> offset_hbm_8 = 8 * hbm_size_256b;
+ ap_uint<32> offset_hbm_9 = 9 * hbm_size_256b;
+ ap_uint<32> offset_hbm_10 = 10 * hbm_size_256b;
+ ap_uint<32> offset_hbm_11 = 11 * hbm_size_256b;
one_over_energy_t one_over_energy;
for (int i = 0; i < 32; i++)
@@ -160,141 +173,35 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out,
data_out << packet_in;
if (conversion) {
- // Load calibration into HBM
- save_gainG0:
- for (int i = 0; i < modules * (RAW_MODULE_SIZE * 2 / 64); i++) {
-#pragma HLS PIPELINE II=1
- data_in >> packet_in;
- if (i % HBM_BURST == 0) {
- d_hbm_p0.write_request(i, HBM_BURST);
- d_hbm_p1.write_request(i, HBM_BURST);
- }
- d_hbm_p0.write(packet_in.data(255, 0));
- d_hbm_p1.write(packet_in.data(511, 256));
- if (i % HBM_BURST == HBM_BURST - 1) {
- d_hbm_p0.write_response();
- d_hbm_p1.write_response();
- }
- }
-
- save_gainG1:
- for (int i = 0; i < modules * (RAW_MODULE_SIZE * 2 / 64); i++) {
-#pragma HLS PIPELINE II=1
- data_in >> packet_in;
- if (i % HBM_BURST == 0) {
- d_hbm_p2.write_request(i, HBM_BURST);
- d_hbm_p3.write_request(i, HBM_BURST);
- }
- d_hbm_p2.write(packet_in.data(255, 0));
- d_hbm_p3.write(packet_in.data(511, 256));
- if (i % HBM_BURST == HBM_BURST - 1) {
- d_hbm_p2.write_response();
- d_hbm_p3.write_response();
- }
- }
-
- save_gainG2:
- for (int i = 0; i < modules * (RAW_MODULE_SIZE * 2 / 64); i++) {
-#pragma HLS PIPELINE II=1
- data_in >> packet_in;
- if (i % HBM_BURST == 0) {
- d_hbm_p4.write_request(i, HBM_BURST);
- d_hbm_p5.write_request(i, HBM_BURST);
- }
- d_hbm_p4.write(packet_in.data(255, 0));
- d_hbm_p5.write(packet_in.data(511, 256));
- if (i % HBM_BURST == HBM_BURST - 1) {
- d_hbm_p4.write_response();
- d_hbm_p5.write_response();
- }
- }
-
- save_pedeG0:
- for (int i = 0; i < modules * storage_cells * (RAW_MODULE_SIZE * 2 / 64); i++) {
-#pragma HLS PIPELINE II=1
- data_in >> packet_in;
- if (i % HBM_BURST == 0) {
- d_hbm_p6.write_request(i, HBM_BURST);
- d_hbm_p7.write_request(i, HBM_BURST);
- }
- d_hbm_p6.write(packet_in.data(255, 0));
- d_hbm_p7.write(packet_in.data(511, 256));
- if (i % HBM_BURST == HBM_BURST - 1) {
- d_hbm_p6.write_response();
- d_hbm_p7.write_response();
- }
- }
-
- save_pedeG1:
- for (int i = 0; i < modules * storage_cells * (RAW_MODULE_SIZE * 2 / 64); i++) {
-#pragma HLS PIPELINE II=1
- data_in >> packet_in;
- if (i % HBM_BURST == 0) {
- d_hbm_p8.write_request(i, HBM_BURST);
- d_hbm_p9.write_request(i, HBM_BURST);
- }
- d_hbm_p8.write(packet_in.data(255, 0));
- d_hbm_p9.write(packet_in.data(511, 256));
- if (i % HBM_BURST == HBM_BURST - 1) {
- d_hbm_p8.write_response();
- d_hbm_p9.write_response();
- }
- }
-
- save_pedeG2:
- for (int i = 0; i < modules * storage_cells * (RAW_MODULE_SIZE * 2 / 64); i++) {
-#pragma HLS PIPELINE II=1
- data_in >> packet_in;
- if (i % HBM_BURST == 0) {
- d_hbm_p10.write_request(i, HBM_BURST);
- d_hbm_p11.write_request(i, HBM_BURST);
- }
- d_hbm_p10.write(packet_in.data(255, 0));
- d_hbm_p11.write(packet_in.data(511, 256));
- if (i % HBM_BURST == HBM_BURST - 1) {
- d_hbm_p10.write_response();
- d_hbm_p11.write_response();
- }
- }
-
ap_uint<7> counter = 0;
addr_in >> addr;
pixel_conversion:
- while (!addr_last_flag(addr)) {
+ while (!addr.last) {
#pragma HLS PIPELINE II=1
//ap_uint<17> offset = packet_in.user(16,0);
if (counter % 16 == 0) {
- ap_uint<17> gain_offset = (addr_module(addr), addr_eth_packet(addr), counter);
- ap_uint<12> pedestal_location = addr_module(addr);
+ ap_uint<19> gain_offset = (addr.module, addr.eth_packet, counter);
+ ap_uint<12> pedestal_location = addr.module;
- if (storage_cells == 2) {
- ap_uint<4> storage_cell_id = (addr_frame_number(addr) - 1) % 2;
- pedestal_location += modules * storage_cell_id;
- } else if (storage_cells == 4) {
- ap_uint<4> storage_cell_id = (addr_frame_number(addr) - 1) % 4;
- pedestal_location += modules * storage_cell_id;
- } else if (storage_cells == 8) {
- ap_uint<4> storage_cell_id = (addr_frame_number(addr) - 1) % 8;
- pedestal_location += modules * storage_cell_id;
- } else if (storage_cells == 16) {
- ap_uint<4> storage_cell_id = (addr_frame_number(addr) - 1) % 16;
+ if (storage_cells > 1) {
+ ap_uint<4> storage_cell_id = (addr.frame_number - 1) % storage_cells;
pedestal_location += modules * storage_cell_id;
}
- ap_uint<26> pedestal_offset = (pedestal_location, addr_eth_packet(addr), counter);
+ ap_uint<26> pedestal_offset = (pedestal_location, addr.eth_packet, counter);
- d_hbm_p0.read_request(gain_offset, 16);
- d_hbm_p1.read_request(gain_offset, 16);
- d_hbm_p2.read_request(gain_offset, 16);
- d_hbm_p3.read_request(gain_offset, 16);
- d_hbm_p4.read_request(gain_offset, 16);
- d_hbm_p5.read_request(gain_offset, 16);
- d_hbm_p6.read_request(pedestal_offset, 16);
- d_hbm_p7.read_request(pedestal_offset, 16);
- d_hbm_p8.read_request(pedestal_offset, 16);
- d_hbm_p9.read_request(pedestal_offset, 16);
- d_hbm_p10.read_request(pedestal_offset, 16);
- d_hbm_p11.read_request(pedestal_offset, 16);
+ d_hbm_p0.read_request(offset_hbm_0 + gain_offset, 16);
+ d_hbm_p1.read_request(offset_hbm_1 + gain_offset, 16);
+ d_hbm_p2.read_request(offset_hbm_2 + gain_offset, 16);
+ d_hbm_p3.read_request(offset_hbm_3 + gain_offset, 16);
+ d_hbm_p4.read_request(offset_hbm_4 + gain_offset, 16);
+ d_hbm_p5.read_request(offset_hbm_5 + gain_offset, 16);
+ d_hbm_p6.read_request(offset_hbm_6 + pedestal_offset, 16);
+ d_hbm_p7.read_request(offset_hbm_7 + pedestal_offset, 16);
+ d_hbm_p8.read_request(offset_hbm_8 + pedestal_offset, 16);
+ d_hbm_p9.read_request(offset_hbm_9 + pedestal_offset, 16);
+ d_hbm_p10.read_request(offset_hbm_10 + pedestal_offset, 16);
+ d_hbm_p11.read_request(offset_hbm_11 + pedestal_offset, 16);
}
ap_uint<256> packed_gainG0_1 = d_hbm_p0.read();
ap_uint<256> packed_gainG0_2 = d_hbm_p1.read();
@@ -330,7 +237,7 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out,
} else {
addr_in >> addr;
forward_packets:
- while (!addr_last_flag(addr)) {
+ while (!addr.last) {
#pragma HLS PIPELINE II=1
data_in >> packet_in;
data_out << packet_in;
diff --git a/fpga/hls/load_calibration.cpp b/fpga/hls/load_calibration.cpp
new file mode 100644
index 00000000..5b7dbb13
--- /dev/null
+++ b/fpga/hls/load_calibration.cpp
@@ -0,0 +1,74 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+
+#include "hls_jfjoch.h"
+
+// Loads calibration from host memory based on 64-bit memory addresses loaded in in_mem_location
+// Expected structure in in_mem_location array:
+//
+// * gain factors for module m at location: 2 + gain level * NMODULES + m
+// * pedestal factors for module m and storage cell s at location: 2 + 3 * NMODULES + (gain level * 16 + s ) * NMODULES + m
+
+void read_module(ap_uint<256> *d_hbm_p0,
+ ap_uint<256> *d_hbm_p1,
+ hls::stream > &host_memory_in,
+ size_t offset_hbm_0,
+ size_t offset_hbm_1) {
+#pragma HLS INLINE OFF
+ for (int i = 0; i < RAW_MODULE_SIZE * sizeof(int16_t) / 64; i++) {
+#pragma HLS PIPELINE II=1
+ ap_axiu<512, 1, 1, 1> data_packet;
+ host_memory_in >> data_packet;
+
+ d_hbm_p0[offset_hbm_0 + i] = data_packet.data(255, 0);
+ d_hbm_p1[offset_hbm_1 + i] = data_packet.data(511, 256);
+ }
+}
+
+void load_calibration(ap_uint<256> *d_hbm_p0,
+ ap_uint<256> *d_hbm_p1,
+ ap_uint<8> modules,
+ ap_uint<5> storage_cells,
+ ap_uint<32> hbm_size_bytes,
+ hls::stream &datamover_in_cmd,
+ hls::stream > &host_memory_in,
+ uint64_t in_mem_location[(3 * 16 + 3) * MAX_MODULES_FPGA]) {
+#pragma HLS INTERFACE mode=s_axilite port=return
+#pragma HLS INTERFACE mode=s_axilite port=in_mem_location
+#pragma HLS INTERFACE register both axis port=datamover_in_cmd
+#pragma HLS INTERFACE register both axis port=host_memory_in
+
+#pragma HLS INTERFACE mode=s_axilite port=modules
+#pragma HLS INTERFACE mode=s_axilite port=storage_cells
+#pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes
+
+#pragma HLS INTERFACE mode=m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \
+ max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
+#pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
+ max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
+
+ if (storage_cells > 16)
+ return;
+ if (modules > MAX_MODULES_FPGA)
+ return;
+
+ for (int c = 0; c < 3; c++) {
+ for (int m = 0; m < modules; m++) {
+#pragma HLS PIPELINE OFF
+ setup_datamover(datamover_in_cmd, in_mem_location[c * modules + m], RAW_MODULE_SIZE * sizeof(int16_t));
+ size_t offset_hbm_0 = (2 * c) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
+ size_t offset_hbm_1 = (2 * c + 1) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
+ read_module(d_hbm_p0, d_hbm_p1, host_memory_in, offset_hbm_0, offset_hbm_1);
+ }
+ }
+
+ for (int c = 0; c < 3; c++) {
+ for (int m = 0; m < modules * storage_cells; m++) {
+#pragma HLS PIPELINE OFF
+ setup_datamover(datamover_in_cmd, in_mem_location[3 * modules + c * modules * storage_cells + m], RAW_MODULE_SIZE * sizeof(int16_t));
+ size_t offset_hbm_0 = (6 + 2 * c) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
+ size_t offset_hbm_1 = (6 + 2 * c + 1) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
+ read_module(d_hbm_p0, d_hbm_p1, host_memory_in, offset_hbm_0, offset_hbm_1);
+ }
+ }
+}
diff --git a/receiver/include/parallel_stream.h b/fpga/hls/parallel_stream.h
similarity index 96%
rename from receiver/include/parallel_stream.h
rename to fpga/hls/parallel_stream.h
index edfbb741..ac50b37b 100644
--- a/receiver/include/parallel_stream.h
+++ b/fpga/hls/parallel_stream.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_PARALLEL_STREAM_H
#define JUNGFRAUJOCH_PARALLEL_STREAM_H
diff --git a/receiver/hls/sls_detector.cpp b/fpga/hls/sls_detector.cpp
similarity index 80%
rename from receiver/hls/sls_detector.cpp
rename to fpga/hls/sls_detector.cpp
index 74783036..3707d8a7 100644
--- a/receiver/hls/sls_detector.cpp
+++ b/fpga/hls/sls_detector.cpp
@@ -1,12 +1,12 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
+
#include "hls_jfjoch.h"
void sls_detector(AXI_STREAM &udp_payload_in,
hls::stream > &udp_metadata_in,
AXI_STREAM &data_out,
- hls::stream > &addr_out,
+ hls::stream &addr_out,
uint64_t& counter,
uint32_t& counter_eth_error,
uint32_t& counter_len_error,
@@ -65,19 +65,22 @@ void sls_detector(AXI_STREAM &udp_payload_in,
&& (udp_metadata_len_err(udp_metadata) == 0)) {
ap_uint<16> column = packet_in.data(4 * 64 + 31, 4 * 64 + 16);
-
- ap_uint<64> frame_number = packet_in.data(63, 0);
- ap_uint<32> jf_debug = packet_in.data(5 * 64 + 31, 5 * 64);
- ap_uint<64> timestamp = packet_in.data(3 * 64 + 63, 3 * 64);
- ap_uint<64> bunchid = packet_in.data(2 * 64 + 63, 2 * 64);
- ap_uint<5> module = (column % 32) / 2;
ap_uint<1> module_part = column[0];
- ap_uint<7> eth_packet = (packet_in.data(127, 96) % 128) | (module_part * 64);
- ap_uint<32> exptime = packet_in.data(95, 64);
+
beat_counter = 0;
reminder = packet_in.data(511, 384);
- addr_out << addr_packet(eth_packet, module, frame_number, jf_debug, timestamp, bunchid,exptime);
+ axis_addr addr;
+ addr.frame_number = packet_in.data(63, 0);
+ addr.debug = packet_in.data(5 * 64 + 31, 5 * 64);
+ addr.timestamp = packet_in.data(3 * 64 + 63, 3 * 64);
+ addr.bunchid = packet_in.data(2 * 64 + 63, 2 * 64);
+ addr.module = (column % 32) / 2;
+ addr.eth_packet = (packet_in.data(127, 96) % 128) | (module_part * 64);
+ addr.exptime = packet_in.data(95, 64);
+ addr.last = 0;
+ addr_out << addr;
+
state = FORWARD;
internal_counter++;
} else {
diff --git a/fpga/hls/stream_merge.cpp b/fpga/hls/stream_merge.cpp
new file mode 100644
index 00000000..688b90b3
--- /dev/null
+++ b/fpga/hls/stream_merge.cpp
@@ -0,0 +1,45 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#include "hls_jfjoch.h"
+
+void stream_merge(AXI_STREAM &input_0,
+ AXI_STREAM &input_1,
+ AXI_STREAM &output) {
+#pragma HLS INTERFACE ap_ctrl_none port=return
+#pragma HLS INTERFACE axis register both port=input_0
+#pragma HLS INTERFACE axis register both port=input_1
+#pragma HLS INTERFACE axis register both port=output
+
+#pragma HLS PIPELINE II=1 style=flp
+ enum state {ARBITRATE, FORWARD};
+ static state state = ARBITRATE;
+ static ap_uint<1> select_input = 0;
+
+ packet_512_t packet_in;
+#pragma HLS RESET variable=state
+ switch (state) {
+ case ARBITRATE:
+ if (input_0.read_nb(packet_in)) {
+ select_input = 0;
+ if (!packet_in.last)
+ state = FORWARD;
+ output.write(packet_in);
+ } else if (input_1.read_nb(packet_in)) {
+ select_input = 1;
+ if (!packet_in.last)
+ state = FORWARD;
+ output.write(packet_in);
+ }
+ break;
+ case FORWARD:
+ if (select_input == 0) {
+ input_0.read(packet_in);
+ } else
+ input_1.read(packet_in);
+ output.write(packet_in);
+
+ if (packet_in.last)
+ state = ARBITRATE;
+ break;
+ }
+}
diff --git a/fpga/hls/timer.cpp b/fpga/hls/timer.cpp
new file mode 100644
index 00000000..e8051a99
--- /dev/null
+++ b/fpga/hls/timer.cpp
@@ -0,0 +1,31 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+
+#include "hls_jfjoch.h"
+
+void timer_host(STREAM_512 &data_in, STREAM_512 &data_out, volatile uint64_t &counter) {
+#pragma HLS INTERFACE register both axis port=data_in
+#pragma HLS INTERFACE register both axis port=data_out
+#pragma HLS INTERFACE register ap_vld port=counter
+#pragma HLS INTERFACE ap_ctrl_none port=return
+ packet_512_t packet_in;
+
+ data_in >> packet_in;
+ uint64_t counter_internal = 0;
+ counter = 0;
+ data_out << packet_in;
+
+ data_in >> packet_in;
+ while (!packet_in.user) {
+#pragma HLS PIPELINE II=1
+ if (data_out.full()) {
+ if (counter_internal < UINT64_MAX)
+ counter_internal++;
+ } else {
+ data_out << packet_in;
+ data_in >> packet_in;
+ }
+ counter = counter_internal;
+ }
+ data_out << packet_in;
+}
diff --git a/receiver/hls/udp.cpp b/fpga/hls/udp.cpp
similarity index 96%
rename from receiver/hls/udp.cpp
rename to fpga/hls/udp.cpp
index 32250aac..9f84389c 100644
--- a/receiver/hls/udp.cpp
+++ b/fpga/hls/udp.cpp
@@ -1,5 +1,5 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
+
#include "hls_jfjoch.h"
diff --git a/receiver/include/LICENSE.HLS_Headers b/fpga/include/LICENSE.HLS_Headers
similarity index 100%
rename from receiver/include/LICENSE.HLS_Headers
rename to fpga/include/LICENSE.HLS_Headers
diff --git a/receiver/include/ap_common.h b/fpga/include/ap_common.h
similarity index 100%
rename from receiver/include/ap_common.h
rename to fpga/include/ap_common.h
diff --git a/receiver/include/ap_decl.h b/fpga/include/ap_decl.h
similarity index 100%
rename from receiver/include/ap_decl.h
rename to fpga/include/ap_decl.h
diff --git a/receiver/include/ap_fixed.h b/fpga/include/ap_fixed.h
similarity index 100%
rename from receiver/include/ap_fixed.h
rename to fpga/include/ap_fixed.h
diff --git a/receiver/include/ap_fixed_base.h b/fpga/include/ap_fixed_base.h
similarity index 100%
rename from receiver/include/ap_fixed_base.h
rename to fpga/include/ap_fixed_base.h
diff --git a/receiver/include/ap_fixed_ref.h b/fpga/include/ap_fixed_ref.h
similarity index 100%
rename from receiver/include/ap_fixed_ref.h
rename to fpga/include/ap_fixed_ref.h
diff --git a/receiver/include/ap_fixed_special.h b/fpga/include/ap_fixed_special.h
similarity index 100%
rename from receiver/include/ap_fixed_special.h
rename to fpga/include/ap_fixed_special.h
diff --git a/receiver/include/ap_int.h b/fpga/include/ap_int.h
similarity index 100%
rename from receiver/include/ap_int.h
rename to fpga/include/ap_int.h
diff --git a/receiver/include/ap_int_base.h b/fpga/include/ap_int_base.h
similarity index 100%
rename from receiver/include/ap_int_base.h
rename to fpga/include/ap_int_base.h
diff --git a/receiver/include/ap_int_ref.h b/fpga/include/ap_int_ref.h
similarity index 100%
rename from receiver/include/ap_int_ref.h
rename to fpga/include/ap_int_ref.h
diff --git a/receiver/include/ap_int_special.h b/fpga/include/ap_int_special.h
similarity index 100%
rename from receiver/include/ap_int_special.h
rename to fpga/include/ap_int_special.h
diff --git a/receiver/include/ap_shift_reg.h b/fpga/include/ap_shift_reg.h
similarity index 100%
rename from receiver/include/ap_shift_reg.h
rename to fpga/include/ap_shift_reg.h
diff --git a/receiver/include/etc/ap_private.h b/fpga/include/etc/ap_private.h
similarity index 100%
rename from receiver/include/etc/ap_private.h
rename to fpga/include/etc/ap_private.h
diff --git a/receiver/include/hls_burst_maxi.h b/fpga/include/hls_burst_maxi.h
similarity index 86%
rename from receiver/include/hls_burst_maxi.h
rename to fpga/include/hls_burst_maxi.h
index 627b965b..9d8541fb 100644
--- a/receiver/include/hls_burst_maxi.h
+++ b/fpga/include/hls_burst_maxi.h
@@ -1,4 +1,9 @@
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+// Modified by Filip Leonarski (Paul Scherrer Institute
+// to allow for multiple parallel bursts to the same pointer
+// (via independent HBM channels)
+
#ifndef X_HLS_BURST_MAXI_SIM_H
#define X_HLS_BURST_MAXI_SIM_H
@@ -27,9 +32,6 @@ struct MAXIAccessRecord {
std::list> WriteRespQ;
};
-// A global map between pointer and MAXAccessRecord.
-std::map MAXIPointer2AccessRecordMap __attribute__((weak));
-
template
class burst_maxi {
public:
@@ -38,7 +40,6 @@ public:
assert(bitwidth != 0 && !(bitwidth & (bitwidth - 1)) &&
"Error: bit width of hls::burst_maxi is not poower-of-2.");
// Reset the MAXI access record to this pointer
- MAXIAccessRecord &R = MAXIPointer2AccessRecordMap[p];
R.read_disp = 0;
R.write_disp = 0;
R.ReadQ.clear();
@@ -48,7 +49,6 @@ public:
void read_request(size_t offset, unsigned len) {
assert(len > 0);
- MAXIAccessRecord &R = MAXIPointer2AccessRecordMap[Ptr];
R.ReadQ.push_back(std::make_pair(offset, len));
std::list> CurrentWriteQ = R.WriteQ;
CurrentWriteQ.insert(CurrentWriteQ.end(),
@@ -62,8 +62,7 @@ public:
}
T read() {
- MAXIAccessRecord &R = MAXIPointer2AccessRecordMap[Ptr];
- assert(!R.ReadQ.empty() && "Error: MAXI read without request.");
+ assert(!R.ReadQ.empty() && "Error: MAXI read without request.");
auto Pair = R.ReadQ.front();
T V = Ptr[Pair.first + (R.read_disp++)];
if (R.read_disp == Pair.second) {
@@ -75,7 +74,6 @@ public:
void write_request(size_t offset, unsigned len) {
assert(len > 0);
- MAXIAccessRecord &R = MAXIPointer2AccessRecordMap[Ptr];
for (auto Pair : R.ReadQ) {
if (overlap(offset, len, Pair.first, Pair.second)) {
std::cerr << "Error: MAXI write request(offset = " << offset << ", len = " << len << ") overlaps with previous read request(offset = " << Pair.first << ", len = " << Pair.second << ")." << std::endl;
@@ -86,8 +84,7 @@ public:
}
void write(const T &val, ap_int byte_enable_mask = -1) {
- MAXIAccessRecord &R = MAXIPointer2AccessRecordMap[Ptr];
- assert(!R.WriteQ.empty() && "Error: MAXI write without request.");
+ assert(!R.WriteQ.empty() && "Error: MAXI write without request.");
auto Pair = R.WriteQ.front();
T *DstP = &Ptr[Pair.first + R.write_disp++];
T Src = val;
@@ -104,13 +101,13 @@ public:
}
void write_response() {
- MAXIAccessRecord &R = MAXIPointer2AccessRecordMap[Ptr];
assert(!R.WriteRespQ.empty() && "Error: bad MAXI write response. Possible: 1) no corresponding write request; 2) some data still not written.");
R.WriteRespQ.pop_front();
}
private:
T *Ptr;
+ MAXIAccessRecord R;
bool overlap(size_t a, unsigned a_len, size_t b, unsigned b_len) {
return a <= b ? a + a_len > b : b + b_len > a;
}
diff --git a/receiver/host/ActionConfig.h b/fpga/pcie_driver/ActionConfig.h
similarity index 83%
rename from receiver/host/ActionConfig.h
rename to fpga/pcie_driver/ActionConfig.h
index 422cb3ef..f248ed5f 100644
--- a/receiver/host/ActionConfig.h
+++ b/fpga/pcie_driver/ActionConfig.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_ACTIONCONFIG_H
#define JUNGFRAUJOCH_ACTIONCONFIG_H
@@ -29,14 +28,14 @@ struct ActionStatus {
uint32_t git_sha1;
uint32_t action_type;
uint32_t release_level;
- uint32_t hbm_temperature;
- uint32_t hbm_max_temperature;
+ uint32_t reserved_3;
+ uint32_t reserved_1;
uint32_t max_modules;
uint32_t modules_internal_packet_generator;
uint64_t pipeline_stalls_host;
uint64_t pipeline_stalls_hbm;
uint32_t fifo_status;
- uint32_t reserved_1;
+ uint32_t hbm_size_bytes;
uint64_t packets_processed;
uint64_t packets_eth;
uint64_t packets_icmp;
@@ -69,6 +68,17 @@ struct ActionEnvParams {
bool ethernet_aligned;
};
+
+struct FrameGeneratorConfig {
+ uint32_t frames;
+ uint32_t modules;
+ uint64_t dest_mac_addr;
+ uint32_t dest_ipv4_addr;
+ uint64_t bunchid;
+ uint32_t exptime;
+ uint32_t debug;
+};
+
#pragma pack(pop)
#endif //JUNGFRAUJOCH_ACTIONCONFIG_H
diff --git a/receiver/pcie_driver/CMakeLists.txt b/fpga/pcie_driver/CMakeLists.txt
similarity index 100%
rename from receiver/pcie_driver/CMakeLists.txt
rename to fpga/pcie_driver/CMakeLists.txt
diff --git a/receiver/pcie_driver/Makefile b/fpga/pcie_driver/Makefile
similarity index 100%
rename from receiver/pcie_driver/Makefile
rename to fpga/pcie_driver/Makefile
diff --git a/receiver/pcie_driver/jfjoch_drv.c b/fpga/pcie_driver/jfjoch_drv.c
similarity index 94%
rename from receiver/pcie_driver/jfjoch_drv.c
rename to fpga/pcie_driver/jfjoch_drv.c
index 21e6fbd9..6d89ff70 100644
--- a/receiver/pcie_driver/jfjoch_drv.c
+++ b/fpga/pcie_driver/jfjoch_drv.c
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include
#include
@@ -82,10 +81,6 @@ static int jfjoch_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id
drvdata->git_sha1 = status.git_sha1;
drvdata->max_modules = status.max_modules;
- err = jfjoch_setup_calibration(pdev);
- if (err)
- goto deregister_misc;
-
jfjoch_setup_cms(drvdata);
jfjoch_setup_network(drvdata);
@@ -114,7 +109,6 @@ void jfjoch_reset(struct jfjoch_drvdata *drvdata) {
pci_reset_function(drvdata->pdev);
jfjoch_setup_cms(drvdata);
- jfjoch_setup_calibration(drvdata->pdev);
dev_info(drvdata->miscdev.this_device, "Jungfraujoch FPGA restarted");
}
diff --git a/receiver/pcie_driver/jfjoch_drv.h b/fpga/pcie_driver/jfjoch_drv.h
similarity index 67%
rename from receiver/pcie_driver/jfjoch_drv.h
rename to fpga/pcie_driver/jfjoch_drv.h
index 3827847d..508b84cb 100644
--- a/receiver/pcie_driver/jfjoch_drv.h
+++ b/fpga/pcie_driver/jfjoch_drv.h
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_JFJOCH_DRV_H
#define JUNGFRAUJOCH_JFJOCH_DRV_H
@@ -11,7 +10,7 @@
#include
#include
-#include "../host/ActionConfig.h"
+#include "ActionConfig.h"
// From Xilinx XDMA
/* obtain the 32 most significant (high) bits of a 32-bit or 64-bit address */
@@ -35,12 +34,33 @@
// Offset for BAR #0 for action configuration
-#define ACTION_CONFIG_OFFSET (0x10000)
-#define MAILBOX_OFFSET (0x30000)
-#define CALIB_BRAM_OFFSET (0x60000)
-#define CMS_OFFSET (0xC0000)
-#define CMAC_OFFSET (0x20000)
-#define PCIE_OFFSET (0x90000)
+#define ACTION_CONFIG_OFFSET (0x010000)
+#define MAILBOX_OFFSET (0x030000)
+#define LOAD_CALIBRATION_OFFSET (0x060000)
+#define CMS_OFFSET (0x0C0000)
+#define CMAC_OFFSET (0x020000)
+#define PCIE_OFFSET (0x090000)
+#define INT_PKT_GEN_OFFSET (0x100000)
+#define FRAME_GEN_OFFSET (0x080000)
+
+#define ADDR_LOAD_CALIBRATION_CTRL (LOAD_CALIBRATION_OFFSET | 0x000000)
+#define ADDR_LOAD_CALIBRATION_MOD (LOAD_CALIBRATION_OFFSET | 0x000010)
+#define ADDR_LOAD_CALIBRATION_SC (LOAD_CALIBRATION_OFFSET | 0x000018)
+#define ADDR_LOAD_CALIBRATION_MEM (LOAD_CALIBRATION_OFFSET | 0x002000)
+
+#define ADDR_FRAME_GEN_CTRL (FRAME_GEN_OFFSET | 0x000000)
+#define ADDR_FRAME_GEN_FRAMES (FRAME_GEN_OFFSET | 0x000010)
+#define ADDR_FRAME_GEN_MODULES (FRAME_GEN_OFFSET | 0x000018)
+#define ADDR_FRAME_GEN_DEST_MAC_LO (FRAME_GEN_OFFSET | 0x000020)
+#define ADDR_FRAME_GEN_DEST_MAC_HI (FRAME_GEN_OFFSET | 0x000024)
+#define ADDR_FRAME_GEN_DEST_IPV4_ADDR (FRAME_GEN_OFFSET | 0x00002C)
+#define ADDR_FRAME_GEN_BUNCHID_LO (FRAME_GEN_OFFSET | 0x000034)
+#define ADDR_FRAME_GEN_BUNCHID_HI (FRAME_GEN_OFFSET | 0x000038)
+#define ADDR_FRAME_GEN_EXPTIME (FRAME_GEN_OFFSET | 0x000040)
+#define ADDR_FRAME_GEN_DEBUG (FRAME_GEN_OFFSET | 0x000048)
+
+#define JFJOCH_DMA_SETTINGS (XDMA_CTRL_RUN_STOP | XDMA_CTRL_IE_DESC_ALIGN_MISMATCH | XDMA_CTRL_IE_DESC_ERROR | XDMA_CTRL_IE_READ_ERROR \
+ | XDMA_CTRL_IE_WRITE_ERROR | XDMA_CTRL_IE_DESC_COMPLETED | XDMA_CTRL_STM_MODE_WB)
#define ADDR_CMS_CONTROL_REG 0x028018
#define ADDR_CMS_MB_RESETN_REG 0x020000
@@ -52,6 +72,8 @@
#define ADDR_CMS_HBM_TEMP1_INS_REG 0x028268 // in C
#define ADDR_CMS_HBM_TEMP2_INS_REG 0x0282BC // in C
+#define INT_PKT_GEN_FRAME_SIZE_BYTES (512U*1024U*2UL)
+
struct jfjoch_buf {
dma_addr_t dma_address;
void *kernel_address;
@@ -83,7 +105,6 @@ int jfjoch_cdev_mmap(struct file *file, struct vm_area_struct *vma);
int jfjoch_cdev_release(struct inode *inode, struct file *file);
int jfjoch_cdev_open(struct inode *inode, struct file *file);
-int jfjoch_setup_calibration(struct pci_dev *pdev);
void jfjoch_setup_cms(struct jfjoch_drvdata *drvdata);
void jfjoch_setup_network(struct jfjoch_drvdata *drvdata);
@@ -100,6 +121,10 @@ void jfjoch_set_mac_addr(struct jfjoch_drvdata *drvdata, u64 *mac_addr);
void jfjoch_get_mac_addr(struct jfjoch_drvdata *drvdata, u64 *mac_addr);
void jfjoch_set_ipv4_addr(struct jfjoch_drvdata *drvdata, const u32 *addr);
void jfjoch_get_ipv4_addr(struct jfjoch_drvdata *drvdata, u32 *addr);
+void jfjoch_load_int_pkt_gen(struct jfjoch_drvdata *drvdata, char* output);
+void jfjoch_save_int_pkt_gen(struct jfjoch_drvdata *drvdata, const char* input);
+int jfjoch_load_calibration(struct jfjoch_drvdata *drvdata, struct ActionConfig *config);
+int jfjoch_run_frame_gen(struct jfjoch_drvdata *drvdata, struct FrameGeneratorConfig *config);
u64 jfjoch_read_mac_addr(struct jfjoch_drvdata *drvdata);
diff --git a/receiver/pcie_driver/jfjoch_function.c b/fpga/pcie_driver/jfjoch_function.c
similarity index 73%
rename from receiver/pcie_driver/jfjoch_function.c
rename to fpga/pcie_driver/jfjoch_function.c
index e546eeb0..29c82cbc 100644
--- a/receiver/pcie_driver/jfjoch_function.c
+++ b/fpga/pcie_driver/jfjoch_function.c
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "jfjoch_drv.h"
#include "../../common/Definitions.h"
@@ -13,31 +12,19 @@ DEFINE_MUTEX(set_mac_mutex);
DEFINE_MUTEX(send_wr_mutex);
DEFINE_MUTEX(read_wc_mutex);
-u32 parity(uint32_t values[4]) {
- return (hweight32(values[0]) + hweight32(values[1]) + hweight32(values[2])) % 2;
-}
-
void jfjoch_start(struct jfjoch_drvdata *drvdata) {
- u32 run_val = XDMA_CTRL_RUN_STOP | XDMA_CTRL_IE_DESC_ALIGN_MISMATCH | XDMA_CTRL_IE_DESC_ERROR | XDMA_CTRL_IE_READ_ERROR
- | XDMA_CTRL_IE_WRITE_ERROR | XDMA_CTRL_IE_DESC_COMPLETED
- | XDMA_CTRL_STM_MODE_WB; // Disable stream writeback
-
// Set PCIe beats counters
- iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
- iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
-
iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0xC0);
iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0xC0);
// Start DMA
- // RUN + enable logging of certain error conditions ==> H2C channel 0 control register
- iowrite32(run_val, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
- // RUN ==> C2H channel 0 control register
- iowrite32(run_val, drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x04);
+ // Run C2H
+ iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x04);
- // Set Mailbox FIFOs, so interrupt threshold is 4 messages
- iowrite32(251, drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_SIT);
- iowrite32(11, drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_RIT);
+ // Set Mailbox FIFOs, so interrupt threshold is 16 messages
+ // => This way it ensures that one can always execute read/write operation on the FIFO
+ iowrite32(255-16, drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_SIT);
+ iowrite32(15 , drvdata->bar0 + MAILBOX_OFFSET + ADDR_MAILBOX_RIT);
// Write Start value to action config register
iowrite32(0x1, drvdata->bar0 + ACTION_CONFIG_OFFSET);
@@ -47,8 +34,6 @@ void jfjoch_end(struct jfjoch_drvdata *drvdata) {
// Write cancel register
iowrite32(0x4, drvdata->bar0 + ACTION_CONFIG_OFFSET);
- // RUN ==> H2C channel 0 control register
- iowrite32(0, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
// RUN ==> C2H channel 0 control register
iowrite32(0, drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x04);
}
@@ -88,6 +73,14 @@ int jfjoch_send_wr(struct jfjoch_drvdata *drvdata, u32 handle) {
return 0;
}
+void jfjoch_load_int_pkt_gen(struct jfjoch_drvdata *drvdata, char* output) {
+ memcpy_fromio(output, drvdata->bar0 + INT_PKT_GEN_OFFSET, INT_PKT_GEN_FRAME_SIZE_BYTES);
+}
+
+void jfjoch_save_int_pkt_gen(struct jfjoch_drvdata *drvdata, const char* input) {
+ memcpy_toio(drvdata->bar0 + INT_PKT_GEN_OFFSET, input, INT_PKT_GEN_FRAME_SIZE_BYTES);
+}
+
int jfjoch_read_wc(struct jfjoch_drvdata *drvdata, u32 *output) {
u32 rta;
int i;
@@ -283,10 +276,78 @@ void jfjoch_get_env_data(struct jfjoch_drvdata *drvdata, struct ActionEnvParams
env_params->hbm_0_temp_C = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_HBM_TEMP1_INS_REG);
env_params->hbm_1_temp_C = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_HBM_TEMP2_INS_REG);
+ // Somehow it is better to ask twice
+ env_params->ethernet_aligned = ioread32(drvdata->bar0 + CMAC_OFFSET + 0x0204) & 0x2;
env_params->ethernet_aligned = ioread32(drvdata->bar0 + CMAC_OFFSET + 0x0204) & 0x2;
}
void jfjoch_clr_net_counters(struct jfjoch_drvdata *drvdata) {
iowrite32(1 << 3, drvdata->bar0 + ACTION_CONFIG_OFFSET);
iowrite32(0, drvdata->bar0 + ACTION_CONFIG_OFFSET);
+}
+
+int jfjoch_load_calibration(struct jfjoch_drvdata *drvdata, struct ActionConfig *config) {
+ struct device *const dev = &drvdata->pdev->dev;
+ u32 i;
+ u32 cell_count = config->nmodules * (3 + 3 * config->nstorage_cells);
+
+ if (cell_count > drvdata->nbuf) {
+ dev_err(dev, "Not enough buffers to support this card\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < cell_count; i++) {
+ u64 addr = drvdata->bufs[i].dma_address;
+ iowrite32(PCI_DMA_L(addr), drvdata->bar0 + ADDR_LOAD_CALIBRATION_MEM + i * 2 * 4);
+ iowrite32(PCI_DMA_H(addr), drvdata->bar0 + ADDR_LOAD_CALIBRATION_MEM + (i * 2 + 1) * 4);
+ }
+
+ // Start DMA
+ // Clear counters and RUN H2C
+ iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
+ iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
+ iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
+
+ iowrite32(config->nmodules, drvdata->bar0 + ADDR_LOAD_CALIBRATION_MOD);
+ iowrite32(config->nstorage_cells, drvdata->bar0 + ADDR_LOAD_CALIBRATION_SC);
+ iowrite32(0x1, drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL);
+
+ i = 0;
+ while (i < 1000) {
+ if (ioread32(drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL) & (1 << 1))
+ break;
+ msleep(10);
+ i++;
+ }
+
+ // STOP H2C channel
+ iowrite32(0, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
+
+ if (i == 1000) {
+ dev_err(dev, "Load calibration didn't finish in 10 seconds\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+int jfjoch_run_frame_gen(struct jfjoch_drvdata *drvdata, struct FrameGeneratorConfig *config) {
+ struct device *const dev = &drvdata->pdev->dev;
+
+ if (ioread32(drvdata->bar0 + ADDR_FRAME_GEN_CTRL) & 0x1) {
+ dev_err(dev, "Frame generator busy\n");
+ return -EBUSY;
+ }
+
+ iowrite32(config->frames, drvdata->bar0 + ADDR_FRAME_GEN_FRAMES);
+ iowrite32(config->modules, drvdata->bar0 + ADDR_FRAME_GEN_MODULES);
+ iowrite32(config->dest_ipv4_addr, drvdata->bar0 + ADDR_FRAME_GEN_DEST_IPV4_ADDR);
+ iowrite32(config->dest_mac_addr & 0xFFFFFFFF, drvdata->bar0 + ADDR_FRAME_GEN_DEST_MAC_LO);
+ iowrite32(config->dest_mac_addr >> 32, drvdata->bar0 + ADDR_FRAME_GEN_DEST_MAC_HI);
+ iowrite32(config->bunchid & 0xFFFFFFFF, drvdata->bar0 + ADDR_FRAME_GEN_BUNCHID_LO);
+ iowrite32(config->bunchid >> 32, drvdata->bar0 + ADDR_FRAME_GEN_BUNCHID_HI);
+ iowrite32(config->exptime, drvdata->bar0 + ADDR_FRAME_GEN_EXPTIME);
+ iowrite32(config->debug, drvdata->bar0 + ADDR_FRAME_GEN_DEBUG);
+ iowrite32(0x1, drvdata->bar0 + ADDR_FRAME_GEN_CTRL);
+ return 0;
}
\ No newline at end of file
diff --git a/receiver/pcie_driver/jfjoch_ioctl.c b/fpga/pcie_driver/jfjoch_ioctl.c
similarity index 73%
rename from receiver/pcie_driver/jfjoch_ioctl.c
rename to fpga/pcie_driver/jfjoch_ioctl.c
index ac899287..13411599 100644
--- a/receiver/pcie_driver/jfjoch_ioctl.c
+++ b/fpga/pcie_driver/jfjoch_ioctl.c
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "jfjoch_drv.h"
#include "jfjoch_ioctl.h"
@@ -9,8 +8,10 @@ long jfjoch_cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) {
struct ActionStatus status;
struct ActionConfig config;
struct ActionEnvParams env_params;
+ struct FrameGeneratorConfig frame_generator_config;
u32 exchange[16];
int err;
+ void *tmp = NULL;
switch (cmd) {
case IOCTL_JFJOCH_START:
@@ -37,6 +38,10 @@ long jfjoch_cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) {
return -EFAULT;
jfjoch_set_config(drvdata, &config);
return 0;
+ case IOCTL_JFJOCH_LOAD_CALIB:
+ if (copy_from_user(&config, (char *) arg, sizeof(struct ActionConfig)) != 0)
+ return -EFAULT;
+ return jfjoch_load_calibration(drvdata, &config);
case IOCTL_JFJOCH_GET_ENV_DATA:
jfjoch_get_env_data(drvdata, &env_params);
if (copy_to_user((char *) arg, &env_params, sizeof(struct ActionEnvParams)) != 0)
@@ -96,6 +101,32 @@ long jfjoch_cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) {
case IOCTL_JFJOCH_DEFAULT_MAC:
jfjoch_read_mac_addr(drvdata);
return 0;
+ case IOCTL_JFJOCH_RUN_FRAME_GEN:
+ if (copy_from_user(&frame_generator_config, (char *) arg, sizeof(struct FrameGeneratorConfig)) != 0)
+ return -EFAULT;
+ return jfjoch_run_frame_gen(drvdata, &frame_generator_config);
+ case IOCTL_JFJOCH_SET_INT_PKT:
+ tmp = vmalloc(INT_PKT_GEN_FRAME_SIZE_BYTES);
+ if (tmp == NULL)
+ return -ENOMEM;
+ if (copy_from_user(tmp, (char *) arg, INT_PKT_GEN_FRAME_SIZE_BYTES) != 0) {
+ vfree(tmp);
+ return -EFAULT;
+ }
+ jfjoch_save_int_pkt_gen(drvdata, tmp);
+ vfree(tmp);
+ return 0;
+ case IOCTL_JFJOCH_GET_INT_PKT:
+ tmp = vmalloc(INT_PKT_GEN_FRAME_SIZE_BYTES);
+ if (tmp == NULL)
+ return -ENOMEM;
+ jfjoch_load_int_pkt_gen(drvdata, tmp);
+ if (copy_to_user((char *) arg, tmp, INT_PKT_GEN_FRAME_SIZE_BYTES) != 0) {
+ vfree(tmp);
+ return -EFAULT;
+ }
+ vfree(tmp);
+ return 0;
default:
return -ENOTTY;
}
diff --git a/receiver/pcie_driver/jfjoch_ioctl.h b/fpga/pcie_driver/jfjoch_ioctl.h
similarity index 80%
rename from receiver/pcie_driver/jfjoch_ioctl.h
rename to fpga/pcie_driver/jfjoch_ioctl.h
index 3667db83..4d15f461 100644
--- a/receiver/pcie_driver/jfjoch_ioctl.h
+++ b/fpga/pcie_driver/jfjoch_ioctl.h
@@ -1,10 +1,9 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#ifndef JUNGFRAUJOCH_JFJOCH_IOCTL_H
#define JUNGFRAUJOCH_JFJOCH_IOCTL_H
-#include "../host/ActionConfig.h"
+#include "ActionConfig.h"
#ifdef __KERNEL__
#include
@@ -33,5 +32,9 @@
#define IOCTL_JFJOCH_DEFAULT_MAC _IO (IOCTL_JFJOCH_MAGIC, 16)
#define IOCTL_JFJOCH_SET_IPV4 _IOW(IOCTL_JFJOCH_MAGIC, 17, uint32_t)
#define IOCTL_JFJOCH_GET_IPV4 _IOR(IOCTL_JFJOCH_MAGIC, 18, uint32_t)
+#define IOCTL_JFJOCH_SET_INT_PKT _IOW(IOCTL_JFJOCH_MAGIC, 19, char *)
+#define IOCTL_JFJOCH_GET_INT_PKT _IOR(IOCTL_JFJOCH_MAGIC, 20, char *)
+#define IOCTL_JFJOCH_LOAD_CALIB _IOW(IOCTL_JFJOCH_MAGIC, 21, struct ActionConfig)
+#define IOCTL_JFJOCH_RUN_FRAME_GEN _IOW(IOCTL_JFJOCH_MAGIC, 22, struct FrameGeneratorConfig)
#endif //JUNGFRAUJOCH_JFJOCH_IOCTL_H
diff --git a/receiver/pcie_driver/jfjoch_memory.c b/fpga/pcie_driver/jfjoch_memory.c
similarity index 79%
rename from receiver/pcie_driver/jfjoch_memory.c
rename to fpga/pcie_driver/jfjoch_memory.c
index b6f2e1c2..ffbec00c 100644
--- a/receiver/pcie_driver/jfjoch_memory.c
+++ b/fpga/pcie_driver/jfjoch_memory.c
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "jfjoch_drv.h"
#include "../../common/Definitions.h"
@@ -53,25 +52,6 @@ void jfjoch_free_phys_continous_buf(struct pci_dev *pdev) {
kfree(drvdata->bufs);
}
-int jfjoch_setup_calibration(struct pci_dev *pdev) {
- struct jfjoch_drvdata *drvdata = pci_get_drvdata(pdev);
- u32 i;
- u32 cell_count = drvdata->max_modules * (3 + 3 * 16) + 1;
-
- if ((cell_count > nbuffer) || (cell_count >= LOAD_CALIBRATION_BRAM_SIZE)) {
- dev_err(&pdev->dev, "Not enough buffers to support this card\n");
- return -EINVAL;
- }
-
- for (i = 0; i < cell_count; i++) {
- u64 addr = drvdata->bufs[i].dma_address;
- iowrite32(PCI_DMA_L(addr), drvdata->bar0 + CALIB_BRAM_OFFSET + i * 2 * 4);
- iowrite32(PCI_DMA_H(addr), drvdata->bar0 + CALIB_BRAM_OFFSET + (i * 2 + 1) * 4);
- }
-
- return 0;
-}
-
int jfjoch_cdev_mmap(struct file *file, struct vm_area_struct *vma) {
unsigned long offset, buffer_number, len;
diff --git a/receiver/pcie_driver/jfjoch_miscdev.c b/fpga/pcie_driver/jfjoch_miscdev.c
similarity index 83%
rename from receiver/pcie_driver/jfjoch_miscdev.c
rename to fpga/pcie_driver/jfjoch_miscdev.c
index d1840eb5..2ccb1e5e 100644
--- a/receiver/pcie_driver/jfjoch_miscdev.c
+++ b/fpga/pcie_driver/jfjoch_miscdev.c
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "jfjoch_drv.h"
#include
@@ -33,5 +32,7 @@ int jfjoch_cdev_open(struct inode *inode, struct file *file) {
}
int jfjoch_cdev_release(struct inode *inode, struct file *file) {
+ struct jfjoch_drvdata *drvdata = container_of(file->private_data, struct jfjoch_drvdata, miscdev);
+ jfjoch_cancel(drvdata);
return 0;
}
diff --git a/receiver/pcie_driver/jfjoch_pcie_setup.c b/fpga/pcie_driver/jfjoch_pcie_setup.c
similarity index 95%
rename from receiver/pcie_driver/jfjoch_pcie_setup.c
rename to fpga/pcie_driver/jfjoch_pcie_setup.c
index 5725347e..fa57e396 100644
--- a/receiver/pcie_driver/jfjoch_pcie_setup.c
+++ b/fpga/pcie_driver/jfjoch_pcie_setup.c
@@ -1,5 +1,4 @@
-// Copyright (2019-2022) Paul Scherrer Institute
-// SPDX-License-Identifier: GPL-3.0-or-later
+// Copyright (2019-2023) Paul Scherrer Institute
#include "jfjoch_drv.h"
#include "../../common/Definitions.h"
diff --git a/receiver/scripts/bd_pcie.tcl b/fpga/scripts/bd_pcie.tcl
similarity index 55%
rename from receiver/scripts/bd_pcie.tcl
rename to fpga/scripts/bd_pcie.tcl
index 224faf87..dff19983 100644
--- a/receiver/scripts/bd_pcie.tcl
+++ b/fpga/scripts/bd_pcie.tcl
@@ -1,5 +1,4 @@
-## Copyright (2019-2022) Paul Scherrer Institute
-## SPDX-License-Identifier: CERN-OHL-S-2.0
+## Copyright (2019-2023) Paul Scherrer Institute
################################################################
# This is a generated script based on design: jfjoch_pcie
@@ -143,20 +142,20 @@ xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:axi_protocol_converter:2.1\
xilinx.com:ip:axi_register_slice:2.1\
xilinx.com:ip:hbm:1.0\
-xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:axi_bram_ctrl:4.1\
xilinx.com:ip:axis_data_fifo:2.0\
xilinx.com:ip:axis_register_slice:1.1\
-xilinx.com:ip:blk_mem_gen:8.4\
psi.ch:hls:data_collection_fsm:1.0\
+psi.ch:hls:frame_generator:1.0\
psi.ch:hls:host_writer:1.0\
-psi.ch:hls:internal_packet_generator:1.0\
+xilinx.com:ip:blk_mem_gen:8.4\
psi.ch:hls:jf_conversion:1.0\
psi.ch:hls:load_calibration:1.0\
xilinx.com:ip:mailbox:2.1\
-psi.ch:hls:timer_hbm:1.0\
+psi.ch:hls:stream_merge:1.0\
psi.ch:hls:timer_host:1.0\
xilinx.com:ip:cmac_usplus:3.1\
+xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:axi_firewall:1.2\
xilinx.com:ip:axis_clock_converter:1.1\
xilinx.com:ip:util_ds_buf:2.2\
@@ -224,99 +223,6 @@ if { $bCheckIPsPassed != 1 } {
# DESIGN PROCs
##################################################################
-
-# Hierarchical cell: gain_uram_0
-proc create_hier_cell_gain_uram_0 { parentCell nameHier } {
-
- variable script_folder
-
- if { $parentCell eq "" || $nameHier eq "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_gain_uram_0() - Empty argument(s)!"}
- return
- }
-
- # Get object for parentCell
- set parentObj [get_bd_cells $parentCell]
- if { $parentObj == "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
- return
- }
-
- # Make sure parentObj is hier blk
- set parentType [get_property TYPE $parentObj]
- if { $parentType ne "hier" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
- return
- }
-
- # Save current instance; Restore later
- set oldCurInst [current_bd_instance .]
-
- # Set parent object as current
- current_bd_instance $parentObj
-
- # Create cell and set as current instance
- set hier_obj [create_bd_cell -type hier $nameHier]
- current_bd_instance $hier_obj
-
- # Create interface pins
- create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
-
-
- # Create pins
- create_bd_pin -dir I axi_aresetn
- create_bd_pin -dir I axi_clk
-
- # Create instance: axi_bram_ctrl_0, and set properties
- set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
- set_property -dict [ list \
- CONFIG.DATA_WIDTH {256} \
- CONFIG.READ_LATENCY {3} \
- ] $axi_bram_ctrl_0
-
- # Create instance: axi_register_slice_0, and set properties
- set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
- set_property -dict [ list \
- CONFIG.REG_AR {15} \
- CONFIG.REG_AW {15} \
- CONFIG.REG_B {15} \
- CONFIG.REG_R {15} \
- CONFIG.REG_W {15} \
- CONFIG.USE_AUTOPIPELINING {1} \
- ] $axi_register_slice_0
-
- # Create instance: blk_mem_gen_0, and set properties
- set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
- set_property -dict [ list \
- CONFIG.Assume_Synchronous_Clk {true} \
- CONFIG.EN_SAFETY_CKT {false} \
- CONFIG.Enable_B {Use_ENB_Pin} \
- CONFIG.Memory_Type {True_Dual_Port_RAM} \
- CONFIG.Operating_Mode_A {NO_CHANGE} \
- CONFIG.Operating_Mode_B {NO_CHANGE} \
- CONFIG.PRIM_type_to_Implement {URAM} \
- CONFIG.Port_B_Clock {100} \
- CONFIG.Port_B_Enable_Rate {100} \
- CONFIG.Port_B_Write_Rate {50} \
- CONFIG.READ_LATENCY_A {3} \
- CONFIG.READ_LATENCY_B {3} \
- CONFIG.Use_RSTB_Pin {true} \
- ] $blk_mem_gen_0
-
- # Create interface connections
- connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
- connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTB]
- connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
- connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins axi_register_slice_0/S_AXI]
-
- # Create port connections
- connect_bd_net -net axi_aresetn_1 [get_bd_pins axi_aresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_register_slice_0/aresetn]
- connect_bd_net -net axi_clk_1 [get_bd_pins axi_clk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_register_slice_0/aclk]
-
- # Restore current instance
- current_bd_instance $oldCurInst
-}
-
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
@@ -354,10 +260,6 @@ proc create_root_design { parentCell } {
set pcie0_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie0_ref ]
- set pcie1_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie1_mgt ]
-
- set pcie1_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie1_ref ]
-
set qsfp0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp0 ]
set qsfp0_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp0_ref ]
@@ -365,13 +267,6 @@ proc create_root_design { parentCell } {
CONFIG.FREQ_HZ {161132812} \
] $qsfp0_ref
- set qsfp1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp1 ]
-
- set qsfp1_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp1_ref ]
- set_property -dict [ list \
- CONFIG.FREQ_HZ {161132812} \
- ] $qsfp1_ref
-
set ref100 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ref100 ]
set_property -dict [ list \
CONFIG.FREQ_HZ {100000000} \
@@ -385,8 +280,6 @@ proc create_root_design { parentCell } {
set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
set qsfp0_led_busy [ create_bd_port -dir O -from 0 -to 0 qsfp0_led_busy ]
set qsfp0_led_conn [ create_bd_port -dir O -from 0 -to 0 qsfp0_led_conn ]
- set qsfp1_led_busy [ create_bd_port -dir O -from 0 -to 0 qsfp1_led_busy ]
- set qsfp1_led_conn [ create_bd_port -dir O -from 0 -to 0 qsfp1_led_conn ]
set satellite_gpio_0 [ create_bd_port -dir I -from 3 -to 0 -type intr satellite_gpio_0 ]
set_property -dict [ list \
CONFIG.PortWidth {4} \
@@ -400,13 +293,6 @@ proc create_root_design { parentCell } {
CONFIG.C_NUM_SW_INTR {2} \
] $axi_intc_0
- # Create instance: axi_intc_1, and set properties
- set axi_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_1 ]
- set_property -dict [ list \
- CONFIG.C_IRQ_CONNECTION {1} \
- CONFIG.C_NUM_SW_INTR {2} \
- ] $axi_intc_1
-
# Create instance: axi_quad_spi_0, and set properties
set axi_quad_spi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_0 ]
set_property -dict [ list \
@@ -444,72 +330,33 @@ proc create_root_design { parentCell } {
# Create instance: cms_subsystem_0, and set properties
set cms_subsystem_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem:4.0 cms_subsystem_0 ]
- # Create instance: gain_uram_0
- create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_0
-
- # Create instance: gain_uram_1
- create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_1
-
- # Create instance: gain_uram_2
- create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_2
-
- # Create instance: gain_uram_3
- create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_3
-
- # Create instance: gain_uram_4
- create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_4
-
- # Create instance: gain_uram_5
- create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_5
-
# Create instance: hbm_infrastructure
create_hier_cell_hbm_infrastructure [current_bd_instance .] hbm_infrastructure
# Create instance: jungfraujoch_0
create_hier_cell_jungfraujoch [current_bd_instance .] jungfraujoch_0
- # Create instance: jungfraujoch_1
- create_hier_cell_jungfraujoch [current_bd_instance .] jungfraujoch_1
-
# Create instance: mac_100g
create_hier_cell_mac_100g [current_bd_instance .] mac_100g
- # Create instance: mac_100g_1
- create_hier_cell_mac_100g [current_bd_instance .] mac_100g_1
-
# Create instance: one, and set properties
set one [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one ]
# Create instance: pcie_dma_0
create_hier_cell_pcie_dma_0 [current_bd_instance .] pcie_dma_0
- # Create instance: pcie_dma_1
- create_hier_cell_pcie_dma_1 [current_bd_instance .] pcie_dma_1
-
# Create instance: proc_sys_reset_pcie_0, and set properties
set proc_sys_reset_pcie_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_pcie_0 ]
set_property -dict [ list \
CONFIG.C_EXT_RST_WIDTH {1} \
] $proc_sys_reset_pcie_0
- # Create instance: proc_sys_reset_pcie_1, and set properties
- set proc_sys_reset_pcie_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_pcie_1 ]
- set_property -dict [ list \
- CONFIG.C_EXT_RST_WIDTH {1} \
- ] $proc_sys_reset_pcie_1
-
# Create instance: proc_sys_reset_refclk, and set properties
set proc_sys_reset_refclk [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_refclk ]
set_property -dict [ list \
CONFIG.C_EXT_RST_WIDTH {1} \
] $proc_sys_reset_refclk
- # Create instance: proc_sys_reset_refclk1, and set properties
- set proc_sys_reset_refclk1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_refclk1 ]
- set_property -dict [ list \
- CONFIG.C_EXT_RST_WIDTH {1} \
- ] $proc_sys_reset_refclk1
-
# Create instance: smartconnect_0, and set properties
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
set_property -dict [ list \
@@ -518,20 +365,6 @@ proc create_root_design { parentCell } {
CONFIG.NUM_SI {1} \
] $smartconnect_0
- # Create instance: smartconnect_1, and set properties
- set smartconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_1 ]
- set_property -dict [ list \
- CONFIG.NUM_CLKS {4} \
- CONFIG.NUM_MI {5} \
- CONFIG.NUM_SI {1} \
- ] $smartconnect_1
-
- # Create instance: smartconnect_2, and set properties
- set smartconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_2 ]
- set_property -dict [ list \
- CONFIG.NUM_CLKS {3} \
- ] $smartconnect_2
-
# Create instance: xlconcat_irq, and set properties
set xlconcat_irq [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_irq ]
@@ -559,82 +392,42 @@ proc create_root_design { parentCell } {
connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_data [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_data] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_data]
connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_cmd]
connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_h2c_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_h2c_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_h2c_cmd]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axis_c2h_data [get_bd_intf_pins jungfraujoch_1/m_axis_c2h_data] [get_bd_intf_pins pcie_dma_1/s_axis_c2h_data]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axis_c2h_datamover_cmd [get_bd_intf_pins jungfraujoch_1/m_axis_c2h_datamover_cmd] [get_bd_intf_pins pcie_dma_1/s_axis_c2h_cmd]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axis_h2c_datamover_cmd [get_bd_intf_pins jungfraujoch_1/m_axis_h2c_datamover_cmd] [get_bd_intf_pins pcie_dma_1/s_axis_h2c_cmd]
connect_bd_intf_net -intf_net mac_100g_1_M_AXIS_100G [get_bd_intf_pins jungfraujoch_0/eth_in] [get_bd_intf_pins mac_100g/m_axis_eth_in]
- connect_bd_intf_net -intf_net mac_100g_1_m_axis_eth_in [get_bd_intf_pins jungfraujoch_1/eth_in] [get_bd_intf_pins mac_100g_1/m_axis_eth_in]
connect_bd_intf_net -intf_net mac_100g_1_qsfp0 [get_bd_intf_ports qsfp0] [get_bd_intf_pins mac_100g/qsfp]
- connect_bd_intf_net -intf_net mac_100g_1_qsfp1 [get_bd_intf_ports qsfp1] [get_bd_intf_pins mac_100g_1/qsfp]
connect_bd_intf_net -intf_net pcie0_ref_1 [get_bd_intf_ports pcie0_ref] [get_bd_intf_pins pcie_dma_0/pcie_refclk]
- connect_bd_intf_net -intf_net pcie1_ref_1 [get_bd_intf_ports pcie1_ref] [get_bd_intf_pins pcie_dma_1/pcie_refclk]
connect_bd_intf_net -intf_net pcie_dma_0_M_AXI [get_bd_intf_pins pcie_dma_0/m_axi_ctrl] [get_bd_intf_pins smartconnect_0/S00_AXI]
connect_bd_intf_net -intf_net pcie_dma_0_pcie0_mgt [get_bd_intf_ports pcie0_mgt] [get_bd_intf_pins pcie_dma_0/pcie_mgt]
- connect_bd_intf_net -intf_net pcie_dma_1_m_axi_ctrl [get_bd_intf_pins pcie_dma_1/m_axi_ctrl] [get_bd_intf_pins smartconnect_1/S00_AXI]
- connect_bd_intf_net -intf_net pcie_dma_1_pcie_mgt [get_bd_intf_ports pcie1_mgt] [get_bd_intf_pins pcie_dma_1/pcie_mgt]
connect_bd_intf_net -intf_net qsfp0_ref_1 [get_bd_intf_ports qsfp0_ref] [get_bd_intf_pins mac_100g/qsfp_ref]
- connect_bd_intf_net -intf_net qsfp1_ref_1 [get_bd_intf_ports qsfp1_ref] [get_bd_intf_pins mac_100g_1/qsfp_ref]
connect_bd_intf_net -intf_net ref100_1 [get_bd_intf_ports ref100] [get_bd_intf_pins clk_wiz_0/CLK_IN1_D]
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins jungfraujoch_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net s_axi_2 [get_bd_intf_pins mac_100g/s_axi] [get_bd_intf_pins smartconnect_0/M02_AXI]
- connect_bd_intf_net -intf_net s_axi_3 [get_bd_intf_pins jungfraujoch_1/s_axi] [get_bd_intf_pins smartconnect_1/M00_AXI]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p0 [get_bd_intf_pins gain_uram_0/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p0]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p1 [get_bd_intf_pins gain_uram_1/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p1]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p2 [get_bd_intf_pins gain_uram_2/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p2]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p3 [get_bd_intf_pins gain_uram_3/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p3]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p4 [get_bd_intf_pins gain_uram_4/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p4]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p5 [get_bd_intf_pins gain_uram_5/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p5]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p6 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_12] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p6]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p7 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_13] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p7]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p8 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_14] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p8]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p9 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_15] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p9]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p10 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_16] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p10]
- connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p11 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_17] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p11]
- connect_bd_intf_net -intf_net s_axis_eth_out_1 [get_bd_intf_pins jungfraujoch_1/eth_out] [get_bd_intf_pins mac_100g_1/s_axis_eth_out]
connect_bd_intf_net -intf_net s_axis_h2c_data_1 [get_bd_intf_pins jungfraujoch_0/s_axis_h2c_data] [get_bd_intf_pins pcie_dma_0/m_axis_h2c_data]
- connect_bd_intf_net -intf_net s_axis_h2c_data_2 [get_bd_intf_pins jungfraujoch_1/s_axis_h2c_data] [get_bd_intf_pins pcie_dma_1/m_axis_h2c_data]
- connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins smartconnect_2/S01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins cms_subsystem_0/s_axi_ctrl]
connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_quad_spi_0/AXI_LITE] [get_bd_intf_pins smartconnect_0/M03_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins smartconnect_0/M04_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins pcie_dma_0/s_axi_dma_ctrl] [get_bd_intf_pins smartconnect_0/M05_AXI]
- connect_bd_intf_net -intf_net smartconnect_1_M01_AXI [get_bd_intf_pins mac_100g_1/s_axi] [get_bd_intf_pins smartconnect_1/M01_AXI]
- connect_bd_intf_net -intf_net smartconnect_1_M02_AXI [get_bd_intf_pins pcie_dma_1/s_axi_dma_ctrl] [get_bd_intf_pins smartconnect_1/M02_AXI]
- connect_bd_intf_net -intf_net smartconnect_1_M03_AXI [get_bd_intf_pins smartconnect_1/M03_AXI] [get_bd_intf_pins smartconnect_2/S00_AXI]
- connect_bd_intf_net -intf_net smartconnect_1_M04_AXI [get_bd_intf_pins axi_intc_1/s_axi] [get_bd_intf_pins smartconnect_1/M04_AXI]
- connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins cms_subsystem_0/s_axi_ctrl] [get_bd_intf_pins smartconnect_2/M00_AXI]
# Create port connections
- connect_bd_net -net axi_clk_1 [get_bd_pins pcie_dma_0/axi_aclk] [get_bd_pins proc_sys_reset_pcie_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk3] [get_bd_pins smartconnect_2/aclk1]
+ connect_bd_net -net axi_clk_1 [get_bd_pins pcie_dma_0/axi_aclk] [get_bd_pins proc_sys_reset_pcie_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk3]
connect_bd_net -net axi_quad_spi_0_ip2intc_irpt [get_bd_pins axi_quad_spi_0/ip2intc_irpt] [get_bd_pins xlconcat_irq/In0]
connect_bd_net -net cms_subsystem_0_interrupt_host [get_bd_pins cms_subsystem_0/interrupt_host] [get_bd_pins xlconcat_irq/In1]
- connect_bd_net -net hbm_infrastructure_apb_complete_0 [get_bd_pins hbm_infrastructure/apb_complete_0] [get_bd_pins jungfraujoch_0/apb_complete]
- connect_bd_net -net hbm_infrastructure_apb_complete_1 [get_bd_pins hbm_infrastructure/apb_complete_1] [get_bd_pins jungfraujoch_1/apb_complete]
connect_bd_net -net hbm_infrastructure_hbm_temp_trip_1 [get_bd_ports hbm_cattrip] [get_bd_pins cms_subsystem_0/interrupt_hbm_cattrip] [get_bd_pins hbm_infrastructure/hbm_cattrip]
connect_bd_net -net hbm_infrastructure_hbm_temperature_1 [get_bd_pins cms_subsystem_0/hbm_temp_1] [get_bd_pins hbm_infrastructure/hbm_temperature_0]
- connect_bd_net -net hbm_infrastructure_hbm_temperature_2 [get_bd_pins cms_subsystem_0/hbm_temp_2] [get_bd_pins hbm_infrastructure/hbm_temperature_1]
- connect_bd_net -net mac_100g_1_eth_busy_n [get_bd_ports qsfp1_led_busy] [get_bd_pins mac_100g_1/eth_busy_n]
- connect_bd_net -net mac_100g_1_stat_rx_aligned_n [get_bd_ports qsfp1_led_conn] [get_bd_pins mac_100g_1/stat_rx_aligned_n]
connect_bd_net -net mac_100g_eth_busy_n [get_bd_ports qsfp0_led_busy] [get_bd_pins mac_100g/eth_busy_n]
connect_bd_net -net mac_100g_stat_rx_aligned_n [get_bd_ports qsfp0_led_conn] [get_bd_pins mac_100g/stat_rx_aligned_n]
- connect_bd_net -net net_refclk50 [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_intc_1/s_axi_aclk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins cms_subsystem_0/aclk_ctrl] [get_bd_pins proc_sys_reset_refclk/slowest_sync_clk] [get_bd_pins proc_sys_reset_refclk1/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk2] [get_bd_pins smartconnect_1/aclk1] [get_bd_pins smartconnect_2/aclk]
- connect_bd_net -net net_refclk100 [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins hbm_infrastructure/refclk100] [get_bd_pins mac_100g/refclk100] [get_bd_pins mac_100g_1/refclk100] [get_bd_pins smartconnect_0/aclk1] [get_bd_pins smartconnect_1/aclk2]
- connect_bd_net -net net_refclk200 [get_bd_pins clk_wiz_0/clk_out3] [get_bd_pins gain_uram_0/axi_clk] [get_bd_pins gain_uram_1/axi_clk] [get_bd_pins gain_uram_2/axi_clk] [get_bd_pins gain_uram_3/axi_clk] [get_bd_pins gain_uram_4/axi_clk] [get_bd_pins gain_uram_5/axi_clk] [get_bd_pins hbm_infrastructure/axi_clk] [get_bd_pins jungfraujoch_0/axi_clk] [get_bd_pins jungfraujoch_1/axi_clk] [get_bd_pins mac_100g/axiclk] [get_bd_pins mac_100g_1/axiclk] [get_bd_pins pcie_dma_0/refclk200] [get_bd_pins pcie_dma_1/refclk200] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk]
- connect_bd_net -net one_dout [get_bd_pins one/dout] [get_bd_pins cms_subsystem_0/aresetn_ctrl] [get_bd_pins smartconnect_2/aresetn] [get_bd_pins proc_sys_reset_pcie_0/dcm_locked] [get_bd_pins proc_sys_reset_pcie_1/dcm_locked] [get_bd_pins proc_sys_reset_refclk/dcm_locked] [get_bd_pins proc_sys_reset_refclk1/dcm_locked]
+ connect_bd_net -net net_refclk50 [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_intc_1/s_axi_aclk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins cms_subsystem_0/aclk_ctrl] [get_bd_pins proc_sys_reset_refclk/slowest_sync_clk] [get_bd_pins proc_sys_reset_refclk1/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk2]
+ connect_bd_net -net net_refclk100 [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins hbm_infrastructure/refclk100] [get_bd_pins mac_100g/refclk100] [get_bd_pins smartconnect_0/aclk1]
+ connect_bd_net -net net_refclk200 [get_bd_pins clk_wiz_0/clk_out3] [get_bd_pins hbm_infrastructure/axi_clk] [get_bd_pins jungfraujoch_0/axi_clk] [get_bd_pins mac_100g/axiclk] [get_bd_pins pcie_dma_0/refclk200] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net one_dout [get_bd_pins one/dout] [get_bd_pins cms_subsystem_0/aresetn_ctrl] [get_bd_pins proc_sys_reset_pcie_0/dcm_locked] [get_bd_pins proc_sys_reset_refclk/dcm_locked]
connect_bd_net -net pcie_dma_0_axi_aresetn [get_bd_pins pcie_dma_0/axi_aresetn] [get_bd_pins proc_sys_reset_pcie_0/ext_reset_in] [get_bd_pins proc_sys_reset_refclk/ext_reset_in] [get_bd_pins smartconnect_0/aresetn]
- connect_bd_net -net pcie_dma_1_axi_aclk [get_bd_pins pcie_dma_1/axi_aclk] [get_bd_pins proc_sys_reset_pcie_1/slowest_sync_clk] [get_bd_pins smartconnect_1/aclk3] [get_bd_pins smartconnect_2/aclk2]
- connect_bd_net -net pcie_dma_1_axi_aresetn [get_bd_pins pcie_dma_1/axi_aresetn] [get_bd_pins proc_sys_reset_pcie_1/ext_reset_in] [get_bd_pins proc_sys_reset_refclk1/ext_reset_in] [get_bd_pins smartconnect_1/aresetn]
- connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins pcie_dma_0/pcie_perstn] [get_bd_pins pcie_dma_1/pcie_perstn]
+ connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins pcie_dma_0/pcie_perstn]
connect_bd_net -net proc_sys_reset_pcie_0_interconnect_aresetn [get_bd_pins pcie_dma_0/axi_clk_resetn] [get_bd_pins proc_sys_reset_pcie_0/interconnect_aresetn]
- connect_bd_net -net proc_sys_reset_pcie_1_interconnect_aresetn [get_bd_pins pcie_dma_1/axi_clk_resetn] [get_bd_pins proc_sys_reset_pcie_1/interconnect_aresetn]
- connect_bd_net -net proc_sys_reset_refclk1_interconnect_aresetn [get_bd_pins gain_uram_0/axi_aresetn] [get_bd_pins gain_uram_1/axi_aresetn] [get_bd_pins gain_uram_2/axi_aresetn] [get_bd_pins gain_uram_3/axi_aresetn] [get_bd_pins gain_uram_4/axi_aresetn] [get_bd_pins gain_uram_5/axi_aresetn] [get_bd_pins jungfraujoch_1/axi_rst_n] [get_bd_pins mac_100g_1/ap_rst_n] [get_bd_pins pcie_dma_1/refclk200_resetn] [get_bd_pins proc_sys_reset_refclk1/interconnect_aresetn]
- connect_bd_net -net proc_sys_reset_refclk1_peripheral_aresetn [get_bd_pins axi_intc_1/s_axi_aresetn] [get_bd_pins hbm_infrastructure/axi_resetn_1] [get_bd_pins jungfraujoch_1/ap_rst_n] [get_bd_pins mac_100g_1/resetn] [get_bd_pins proc_sys_reset_refclk1/peripheral_aresetn]
connect_bd_net -net proc_sys_reset_refclk_peripheral_aresetn [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_quad_spi_0/s_axi_aresetn] [get_bd_pins hbm_infrastructure/axi_resetn] [get_bd_pins jungfraujoch_0/ap_rst_n] [get_bd_pins mac_100g/ap_rst_n] [get_bd_pins proc_sys_reset_refclk/peripheral_aresetn]
connect_bd_net -net resetn_1 [get_bd_pins jungfraujoch_0/axi_rst_n] [get_bd_pins mac_100g/resetn] [get_bd_pins pcie_dma_0/refclk200_resetn] [get_bd_pins proc_sys_reset_refclk/interconnect_aresetn]
connect_bd_net -net satellite_gpio_0_1 [get_bd_ports satellite_gpio_0] [get_bd_pins cms_subsystem_0/satellite_gpio]
connect_bd_net -net usr_irq_req_1 [get_bd_pins axi_intc_0/irq] [get_bd_pins pcie_dma_0/usr_irq_req]
- connect_bd_net -net usr_irq_req_2 [get_bd_pins axi_intc_1/irq] [get_bd_pins pcie_dma_1/usr_irq_req]
connect_bd_net -net xlconcat_irq_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins axi_intc_1/intr] [get_bd_pins xlconcat_irq/dout]
- connect_bd_net -net zero_dout [get_bd_pins axi_quad_spi_0/usrcclkts] [get_bd_pins jungfraujoch_0/eth_busy] [get_bd_pins jungfraujoch_0/eth_stat_rx_aligned] [get_bd_pins jungfraujoch_0/eth_stat_rx_packet_bad_fcs] [get_bd_pins jungfraujoch_0/eth_stat_rx_status] [get_bd_pins jungfraujoch_0/hbm_temp_trip] [get_bd_pins jungfraujoch_0/hbm_temperature] [get_bd_pins jungfraujoch_0/mm2s_error] [get_bd_pins jungfraujoch_0/s2mm_error] [get_bd_pins jungfraujoch_1/eth_busy] [get_bd_pins jungfraujoch_1/eth_stat_rx_aligned] [get_bd_pins jungfraujoch_1/eth_stat_rx_packet_bad_fcs] [get_bd_pins jungfraujoch_1/eth_stat_rx_status] [get_bd_pins jungfraujoch_1/hbm_temp_trip] [get_bd_pins jungfraujoch_1/hbm_temperature] [get_bd_pins jungfraujoch_1/mm2s_error] [get_bd_pins jungfraujoch_1/s2mm_error] [get_bd_pins zero/dout]
+ connect_bd_net -net zero_dout [get_bd_pins axi_quad_spi_0/usrcclkts] [get_bd_pins zero/dout] [get_bd_pins cms_subsystem_0/hbm_temp_2]
# Create address segments
assign_bd_address -offset 0x00010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/action_config_0/s_axi/reg0] -force
@@ -642,48 +435,21 @@ proc create_root_design { parentCell } {
assign_bd_address -offset 0x00030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/mailbox_0/S0_AXI/Reg] -force
assign_bd_address -offset 0x00040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_quad_spi_0/AXI_LITE/Reg] -force
assign_bd_address -offset 0x00050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force
- assign_bd_address -offset 0x00060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_0/S_AXI/Mem0] -force
+ assign_bd_address -offset 0x00060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/load_calibration_0/s_axi_control/Reg] -force
assign_bd_address -offset 0x00070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/axi_firewall_0/S_AXI_CTL/Control] -force
+ assign_bd_address -offset 0x00080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/frame_generator_0/s_axi_control/Reg] -force
assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/xdma_0/S_AXI_LITE/CTL0] -force
assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force
+ assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_0/S_AXI/Mem0] -force
+ assign_bd_address -offset 0x00000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jungfraujoch_0/frame_generator_0/Data_m_axi_uram] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_1/S_AXI/Mem0] -force
- assign_bd_address -offset 0x00010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_1/action_config_0/s_axi/reg0] -force
- assign_bd_address -offset 0x00020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs mac_100g_1/cmac_usplus_0/s_axi/Reg] -force
- assign_bd_address -offset 0x00030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_1/mailbox_0/S0_AXI/Reg] -force
- assign_bd_address -offset 0x00050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_intc_1/S_AXI/Reg] -force
- assign_bd_address -offset 0x00060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_1/axi_bram_ctrl_0/S_AXI/Mem0] -force
- assign_bd_address -offset 0x00070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_1/axi_firewall_0/S_AXI_CTL/Control] -force
- assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_1/xdma_0/S_AXI_LITE/CTL0] -force
- assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force
-
- assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p0] [get_bd_addr_segs gain_uram_0/axi_bram_ctrl_0/S_AXI/Mem0] -force
- assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p1] [get_bd_addr_segs gain_uram_1/axi_bram_ctrl_0/S_AXI/Mem0] -force
- assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p2] [get_bd_addr_segs gain_uram_2/axi_bram_ctrl_0/S_AXI/Mem0] -force
- assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p3] [get_bd_addr_segs gain_uram_3/axi_bram_ctrl_0/S_AXI/Mem0] -force
- assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p4] [get_bd_addr_segs gain_uram_4/axi_bram_ctrl_0/S_AXI/Mem0] -force
- assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p5] [get_bd_addr_segs gain_uram_5/axi_bram_ctrl_0/S_AXI/Mem0] -force
assign_bd_address
- set_property -dict [ list \
- CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y3} \
- CONFIG.GT_GROUP_SELECT {X0Y24~X0Y27} \
- ] [get_bd_cells mac_100g/cmac_usplus_0]
-
- set_property -dict [ list \
- CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y4} \
- CONFIG.GT_GROUP_SELECT {X0Y28~X0Y31} \
- ] [get_bd_cells mac_100g_1/cmac_usplus_0]
-
set_property -dict [list \
CONFIG.MAX_MODULES_FPGA_PARAM {0x00000010} \
CONFIG.DESIGN_NUMBER {0} \
] [get_bd_cells jungfraujoch_0/action_config_0]
- set_property -dict [list \
- CONFIG.MAX_MODULES_FPGA_PARAM {0x00000004} \
- CONFIG.DESIGN_NUMBER {1} \
- ] [get_bd_cells jungfraujoch_1/action_config_0]
-
# Restore current instance
current_bd_instance $oldCurInst
diff --git a/receiver/scripts/build_pcie_design.tcl b/fpga/scripts/build_pcie_design.tcl
similarity index 96%
rename from receiver/scripts/build_pcie_design.tcl
rename to fpga/scripts/build_pcie_design.tcl
index b53bf9b9..eb490e0d 100644
--- a/receiver/scripts/build_pcie_design.tcl
+++ b/fpga/scripts/build_pcie_design.tcl
@@ -1,5 +1,4 @@
-## Copyright (2019-2022) Paul Scherrer Institute
-## SPDX-License-Identifier: CERN-OHL-S-2.0
+## Copyright (2019-2023) Paul Scherrer Institute
set origin_dir [file dirname [file normalize [info script]]]
diff --git a/receiver/scripts/check_hls.sh b/fpga/scripts/check_hls.sh
similarity index 100%
rename from receiver/scripts/check_hls.sh
rename to fpga/scripts/check_hls.sh
diff --git a/receiver/scripts/hbm_u55c.tcl b/fpga/scripts/hbm_u55c.tcl
similarity index 73%
rename from receiver/scripts/hbm_u55c.tcl
rename to fpga/scripts/hbm_u55c.tcl
index 15442109..7a1463df 100644
--- a/receiver/scripts/hbm_u55c.tcl
+++ b/fpga/scripts/hbm_u55c.tcl
@@ -1,5 +1,4 @@
-## Copyright (2019-2022) Paul Scherrer Institute
-## SPDX-License-Identifier: CERN-OHL-S-2.0
+## Copyright (2019-2023) Paul Scherrer Institute
# Inspired on Apache License based SNAP/OC-Accel design from IBM
@@ -37,16 +36,12 @@ proc create_hier_cell_hbm_infrastructure { parentCell nameHier } {
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
- create_bd_pin -dir O apb_complete_0
- create_bd_pin -dir O apb_complete_1
create_bd_pin -dir I -type clk axi_clk
create_bd_pin -dir I -type rst axi_resetn
- create_bd_pin -dir I -type rst axi_resetn_1
create_bd_pin -dir I -type clk refclk100
create_bd_pin -dir O hbm_cattrip
set hbm_temperature_0 [ create_bd_pin -dir O -from 6 -to 0 hbm_temperature_0 ]
- set hbm_temperature_1 [ create_bd_pin -dir O -from 6 -to 0 hbm_temperature_1 ]
# Create instance: hbm, and set properties
set hbm [ create_bd_cell -type ip -vlnv xilinx.com:ip:hbm:1.0 hbm ]
@@ -59,31 +54,31 @@ proc create_hier_cell_hbm_infrastructure { parentCell nameHier } {
CONFIG.USER_APB_PCLK_0 {100} \
CONFIG.USER_APB_PCLK_PERIOD_0 {10.0} \
CONFIG.USER_AUTO_POPULATE {yes} \
- CONFIG.USER_CLK_SEL_LIST0 {AXI_07_ACLK} \
- CONFIG.USER_CLK_SEL_LIST1 {AXI_19_ACLK} \
+ CONFIG.USER_CLK_SEL_LIST0 {AXI_05_ACLK} \
+ CONFIG.USER_CLK_SEL_LIST1 {AXI_16_ACLK} \
CONFIG.USER_DFI_CLK0_FREQ {450.000} \
CONFIG.USER_HBM_CP_0 {6} \
- CONFIG.USER_HBM_CP_1 {6} \
- CONFIG.USER_HBM_DENSITY {16GB} \
+ CONFIG.USER_HBM_CP_1 {3} \
+ CONFIG.USER_HBM_DENSITY {8GB} \
CONFIG.USER_HBM_FBDIV_0 {36} \
- CONFIG.USER_HBM_FBDIV_1 {36} \
+ CONFIG.USER_HBM_FBDIV_1 {5} \
CONFIG.USER_HBM_HEX_CP_RES_0 {0x0000A600} \
- CONFIG.USER_HBM_HEX_CP_RES_1 {0x0000A600} \
+ CONFIG.USER_HBM_HEX_CP_RES_1 {0x0000B300} \
CONFIG.USER_HBM_HEX_FBDIV_CLKOUTDIV_0 {0x00000902} \
- CONFIG.USER_HBM_HEX_FBDIV_CLKOUTDIV_1 {0x00000902} \
+ CONFIG.USER_HBM_HEX_FBDIV_CLKOUTDIV_1 {0x00000142} \
CONFIG.USER_HBM_HEX_LOCK_FB_REF_DLY_0 {0x00001f1f} \
- CONFIG.USER_HBM_HEX_LOCK_FB_REF_DLY_1 {0x00001f1f} \
+ CONFIG.USER_HBM_HEX_LOCK_FB_REF_DLY_1 {0x00000a0a} \
CONFIG.USER_HBM_LOCK_FB_DLY_0 {31} \
- CONFIG.USER_HBM_LOCK_FB_DLY_1 {31} \
+ CONFIG.USER_HBM_LOCK_FB_DLY_1 {10} \
CONFIG.USER_HBM_LOCK_REF_DLY_0 {31} \
- CONFIG.USER_HBM_LOCK_REF_DLY_1 {31} \
+ CONFIG.USER_HBM_LOCK_REF_DLY_1 {10} \
CONFIG.USER_HBM_REF_CLK_0 {100} \
CONFIG.USER_HBM_REF_CLK_PS_0 {5000.00} \
CONFIG.USER_HBM_REF_CLK_XDC_0 {10.00} \
CONFIG.USER_HBM_REF_OUT_CLK_0 {1800} \
CONFIG.USER_HBM_RES_0 {10} \
- CONFIG.USER_HBM_RES_1 {10} \
- CONFIG.USER_HBM_STACK {2} \
+ CONFIG.USER_HBM_RES_1 {11} \
+ CONFIG.USER_HBM_STACK {1} \
CONFIG.USER_HBM_TCK_0 {900} \
CONFIG.USER_HBM_TCK_0_PERIOD {1.1111111111111112} \
CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {true} \
@@ -222,6 +217,7 @@ proc create_hier_cell_hbm_infrastructure { parentCell nameHier } {
CONFIG.USER_MC9_LOOKAHEAD_SBRF {true} \
CONFIG.USER_MC9_REF_TEMP_COMP {false} \
CONFIG.USER_MC9_TRAFFIC_OPTION {Linear} \
+ CONFIG.USER_MC_ENABLE_08 {FALSE} \
CONFIG.USER_MC_ENABLE_09 {FALSE} \
CONFIG.USER_MC_ENABLE_10 {FALSE} \
CONFIG.USER_MC_ENABLE_11 {FALSE} \
@@ -230,16 +226,20 @@ proc create_hier_cell_hbm_infrastructure { parentCell nameHier } {
CONFIG.USER_MC_ENABLE_14 {FALSE} \
CONFIG.USER_MC_ENABLE_15 {FALSE} \
CONFIG.USER_MC_ENABLE_APB_01 {FALSE} \
- CONFIG.USER_MEMORY_DISPLAY {16384} \
- CONFIG.USER_PHY_ENABLE_08 {TRUE} \
- CONFIG.USER_PHY_ENABLE_09 {TRUE} \
- CONFIG.USER_PHY_ENABLE_10 {TRUE} \
- CONFIG.USER_PHY_ENABLE_11 {TRUE} \
- CONFIG.USER_PHY_ENABLE_12 {TRUE} \
- CONFIG.USER_PHY_ENABLE_13 {TRUE} \
- CONFIG.USER_PHY_ENABLE_14 {TRUE} \
- CONFIG.USER_PHY_ENABLE_15 {TRUE} \
- CONFIG.USER_SWITCH_ENABLE_00 {FALSE} \
+ CONFIG.USER_MEMORY_DISPLAY {8192} \
+ CONFIG.USER_PHY_ENABLE_08 {FALSE} \
+ CONFIG.USER_PHY_ENABLE_09 {FALSE} \
+ CONFIG.USER_PHY_ENABLE_10 {FALSE} \
+ CONFIG.USER_PHY_ENABLE_11 {FALSE} \
+ CONFIG.USER_PHY_ENABLE_12 {FALSE} \
+ CONFIG.USER_PHY_ENABLE_13 {FALSE} \
+ CONFIG.USER_PHY_ENABLE_14 {FALSE} \
+ CONFIG.USER_PHY_ENABLE_15 {FALSE} \
+ CONFIG.USER_SAXI_12 {false} \
+ CONFIG.USER_SAXI_13 {false} \
+ CONFIG.USER_SAXI_14 {false} \
+ CONFIG.USER_SAXI_15 {false} \
+ CONFIG.USER_SWITCH_ENABLE_00 {TRUE} \
CONFIG.USER_SWITCH_ENABLE_01 {FALSE} \
CONFIG.USER_TEMP_POLL_CNT_0 {100000} \
CONFIG.USER_XSDB_INTF_EN {TRUE} \
@@ -256,26 +256,13 @@ proc create_hier_cell_hbm_infrastructure { parentCell nameHier } {
CONFIG.USER_tRREFD_0 {0x8} \
CONFIG.USER_tWR_0 {0x0F} \
CONFIG.USER_tXP_0 {0x07} \
- ] $hbm
-
- # Create instance: util_vector_logic_0, and set properties
- set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
- set_property -dict [ list \
- CONFIG.C_OPERATION {or} \
- CONFIG.C_SIZE {1} \
- CONFIG.LOGO_FILE {data/sym_orgate.png} \
- ] $util_vector_logic_0
+ ] $hbm
connect_bd_net [get_bd_pins hbm_temperature_0] [get_bd_pins hbm/DRAM_0_STAT_TEMP]
- connect_bd_net [get_bd_pins hbm_temperature_1] [get_bd_pins hbm/DRAM_1_STAT_TEMP]
- connect_bd_net -net hbm_DRAM_0_STAT_CATTRIP [get_bd_pins hbm/DRAM_0_STAT_CATTRIP] [get_bd_pins util_vector_logic_0/Op1]
- connect_bd_net -net hbm_DRAM_1_STAT_CATTRIP [get_bd_pins hbm/DRAM_1_STAT_CATTRIP] [get_bd_pins util_vector_logic_0/Op2]
- connect_bd_net -net util_vector_logic_0_Res [get_bd_pins hbm_cattrip] [get_bd_pins util_vector_logic_0/Res]
- connect_bd_net -net hbm_apb_complete_0 [get_bd_pins apb_complete_0] [get_bd_pins hbm/apb_complete_0]
- connect_bd_net -net hbm_apb_complete_1 [get_bd_pins apb_complete_1] [get_bd_pins hbm/apb_complete_1]
+ connect_bd_net -net hbm_DRAM_0_STAT_CATTRIP [get_bd_pins hbm/DRAM_0_STAT_CATTRIP] [get_bd_pins hbm_cattrip]
- connect_bd_net [get_bd_pins axi_resetn] [get_bd_pins hbm/APB_0_PRESET_N] [get_bd_pins hbm/APB_1_PRESET_N]
- connect_bd_net [get_bd_pins refclk100] [get_bd_pins hbm/APB_0_PCLK] [get_bd_pins hbm/APB_1_PCLK] [get_bd_pins hbm/HBM_REF_CLK_0] [get_bd_pins hbm/HBM_REF_CLK_1]
+ connect_bd_net [get_bd_pins axi_resetn] [get_bd_pins hbm/APB_0_PRESET_N]
+ connect_bd_net [get_bd_pins refclk100] [get_bd_pins hbm/APB_0_PCLK] [get_bd_pins hbm/HBM_REF_CLK_0]
for {set i 0} {$i < 12} {incr i} {
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hbm_$i
@@ -291,7 +278,7 @@ proc create_hier_cell_hbm_infrastructure { parentCell nameHier } {
set axi_prot_conv [create_bd_cell -type ip -vlnv {xilinx.com:ip:axi_protocol_converter:*} axi4_to_axi3_$i]
set_property -dict [ list \
- CONFIG.TRANSLATION_MODE {0} \
+ CONFIG.TRANSLATION_MODE {2} \
] $axi_prot_conv
connect_bd_net [get_bd_pins axi_clk] [get_bd_pins axi4_to_axi3_$i/aclk] [get_bd_pins axi_register_slice_$i/aclk]
@@ -311,40 +298,6 @@ proc create_hier_cell_hbm_infrastructure { parentCell nameHier } {
}
}
- for {set i 12} {$i < 18} {incr i} {
- create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hbm_$i
-
- set cell [create_bd_cell -type ip -vlnv {xilinx.com:ip:axi_register_slice:*} axi_register_slice_$i ]
- set_property -dict [ list \
- CONFIG.REG_AW {15} \
- CONFIG.REG_AR {15} \
- CONFIG.REG_W {15} \
- CONFIG.REG_R {15} \
- CONFIG.REG_B {15} \
- ] $cell
-
- set axi_prot_conv [create_bd_cell -type ip -vlnv {xilinx.com:ip:axi_protocol_converter:*} axi4_to_axi3_$i]
- set_property -dict [ list \
- CONFIG.TRANSLATION_MODE {0} \
- ] $axi_prot_conv
-
- connect_bd_net [get_bd_pins axi_clk] [get_bd_pins axi4_to_axi3_$i/aclk] [get_bd_pins axi_register_slice_$i/aclk]
-
- connect_bd_net [get_bd_pins axi_resetn_1] [get_bd_pins axi_register_slice_$i/aresetn]
- connect_bd_net [get_bd_pins axi_resetn_1] [get_bd_pins axi4_to_axi3_$i/aresetn]
- connect_bd_intf_net [get_bd_intf_pins axi4_to_axi3_$i/M_AXI] [get_bd_intf_pins axi_register_slice_$i/S_AXI]
- connect_bd_intf_net [get_bd_intf_pins axi4_to_axi3_$i/S_AXI] [get_bd_intf_pins s_axi_hbm_$i]
- if {$i < 10} {
- connect_bd_net [get_bd_pins axi_resetn_1] [get_bd_pins hbm/AXI_0${i}_ARESET_N]
- connect_bd_net [get_bd_pins axi_clk] [get_bd_pins hbm/AXI_0${i}_ACLK]
- connect_bd_intf_net [get_bd_intf_pins axi_register_slice_$i/M_AXI] [get_bd_intf_pins hbm/SAXI_0${i}*]
- } else {
- connect_bd_net [get_bd_pins axi_resetn_1] [get_bd_pins hbm/AXI_${i}_ARESET_N]
- connect_bd_net [get_bd_pins axi_clk] [get_bd_pins hbm/AXI_${i}_ACLK]
- connect_bd_intf_net [get_bd_intf_pins axi_register_slice_$i/M_AXI] [get_bd_intf_pins hbm/SAXI_${i}*]
- }
- }
-
# Restore current instance
current_bd_instance $oldCurInst
}
diff --git a/receiver/scripts/jfjoch.tcl b/fpga/scripts/jfjoch.tcl
similarity index 64%
rename from receiver/scripts/jfjoch.tcl
rename to fpga/scripts/jfjoch.tcl
index 0b87e910..763aafb0 100644
--- a/receiver/scripts/jfjoch.tcl
+++ b/fpga/scripts/jfjoch.tcl
@@ -1,5 +1,4 @@
-## Copyright (2019-2022) Paul Scherrer Institute
-## SPDX-License-Identifier: CERN-OHL-S-2.0
+## Copyright (2019-2023) Paul Scherrer Institute
# Hierarchical cell: jungfraujoch
proc create_hier_cell_jungfraujoch { parentCell nameHier } {
@@ -7,7 +6,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
- catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_jungfraujoch() - Empty argument(s)!"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_jungfraujoch_0() - Empty argument(s)!"}
return
}
@@ -77,19 +76,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
# Create pins
create_bd_pin -dir I -type rst ap_rst_n
- create_bd_pin -dir I apb_complete
create_bd_pin -dir I -type clk axi_clk
create_bd_pin -dir I -type rst axi_rst_n
- create_bd_pin -dir I eth_busy
- create_bd_pin -dir I eth_stat_rx_aligned
- create_bd_pin -dir I eth_stat_rx_packet_bad_fcs
- create_bd_pin -dir I eth_stat_rx_status
- create_bd_pin -dir I hbm_temp_trip
- create_bd_pin -dir I -from 6 -to 0 hbm_temperature
- create_bd_pin -dir I mm2s_error
- create_bd_pin -dir O qsfp_led_busy
- create_bd_pin -dir O qsfp_led_conn
- create_bd_pin -dir I s2mm_error
# Create instance: action_config_0, and set properties
set block_name action_config
@@ -101,20 +89,36 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
+ set_property -dict [ list \
+ CONFIG.DESIGN_NUMBER {0} \
+ CONFIG.MAX_MODULES_FPGA_PARAM {0x00000010} \
+ ] $action_config_0
- # Create instance: axi_bram_ctrl_0, and set properties
- set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
+ # Create instance: axi_bram_ctrl_internal_packet_generator_0, and set properties
+ set axi_bram_ctrl_internal_packet_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_internal_packet_generator_0 ]
set_property -dict [ list \
- CONFIG.PROTOCOL {AXI4LITE} \
- CONFIG.READ_LATENCY {1} \
+ CONFIG.DATA_WIDTH {512} \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.READ_LATENCY {3} \
CONFIG.SINGLE_PORT_BRAM {1} \
- ] $axi_bram_ctrl_0
+ ] $axi_bram_ctrl_internal_packet_generator_0
+
+ # Create instance: axi_bram_ctrl_internal_packet_generator_1, and set properties
+ set axi_bram_ctrl_internal_packet_generator_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_internal_packet_generator_1 ]
+ set_property -dict [ list \
+ CONFIG.DATA_WIDTH {512} \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.READ_LATENCY {3} \
+ CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_internal_packet_generator_1
# Create instance: axis_addr_fifo_0, and set properties
set axis_addr_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_addr_fifo_0 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {128} \
CONFIG.FIFO_MEMORY_TYPE {block} \
+ CONFIG.HAS_AEMPTY {1} \
+ CONFIG.HAS_AFULL {1} \
] $axis_addr_fifo_0
# Create instance: axis_addr_fifo_1, and set properties
@@ -126,19 +130,10 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
CONFIG.HAS_AFULL {1} \
] $axis_addr_fifo_1
- # Create instance: axis_addr_fifo_2, and set properties
- set axis_addr_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_addr_fifo_2 ]
- set_property -dict [ list \
- CONFIG.FIFO_DEPTH {256} \
- CONFIG.FIFO_MEMORY_TYPE {block} \
- CONFIG.HAS_AEMPTY {1} \
- CONFIG.HAS_AFULL {1} \
- ] $axis_addr_fifo_2
-
# Create instance: axis_data_fifo_0, and set properties
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
set_property -dict [ list \
- CONFIG.FIFO_DEPTH {16384} \
+ CONFIG.FIFO_DEPTH {4096} \
CONFIG.FIFO_MEMORY_TYPE {ultra} \
] $axis_data_fifo_0
@@ -147,6 +142,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
set_property -dict [ list \
CONFIG.FIFO_DEPTH {256} \
CONFIG.FIFO_MEMORY_TYPE {block} \
+ CONFIG.HAS_AEMPTY {1} \
+ CONFIG.HAS_AFULL {1} \
] $axis_data_fifo_1
# Create instance: axis_data_fifo_2, and set properties
@@ -159,27 +156,11 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
# Create instance: axis_data_fifo_3, and set properties
set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
set_property -dict [ list \
- CONFIG.FIFO_DEPTH {256} \
- CONFIG.FIFO_MEMORY_TYPE {block} \
- CONFIG.HAS_AEMPTY {1} \
- CONFIG.HAS_AFULL {1} \
- ] $axis_data_fifo_3
-
- # Create instance: axis_data_fifo_4, and set properties
- set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
- set_property -dict [ list \
- CONFIG.FIFO_DEPTH {256} \
- CONFIG.FIFO_MEMORY_TYPE {block} \
- ] $axis_data_fifo_4
-
- # Create instance: axis_data_fifo_5, and set properties
- set axis_data_fifo_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_5 ]
- set_property -dict [ list \
- CONFIG.FIFO_DEPTH {16384} \
+ CONFIG.FIFO_DEPTH {32768} \
CONFIG.FIFO_MEMORY_TYPE {ultra} \
CONFIG.HAS_AEMPTY {1} \
CONFIG.HAS_AFULL {1} \
- ] $axis_data_fifo_5
+ ] $axis_data_fifo_3
# Create instance: axis_data_fifo_c2h_cmd, and set properties
set axis_data_fifo_c2h_cmd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_c2h_cmd ]
@@ -203,23 +184,33 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
set axis_data_fifo_h2c_cmd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_h2c_cmd ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {64} \
+ CONFIG.HAS_AEMPTY {1} \
+ CONFIG.HAS_AFULL {1} \
] $axis_data_fifo_h2c_cmd
# Create instance: axis_data_fifo_h2c_data, and set properties
set axis_data_fifo_h2c_data [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_h2c_data ]
set_property -dict [ list \
- CONFIG.FIFO_DEPTH {128} \
+ CONFIG.FIFO_DEPTH {256} \
CONFIG.FIFO_MEMORY_TYPE {block} \
CONFIG.HAS_AEMPTY {1} \
CONFIG.HAS_AFULL {1} \
CONFIG.TDATA_NUM_BYTES {64} \
] $axis_data_fifo_h2c_data
- # Create instance: axis_register_slice_addr_0, and set properties
- set axis_register_slice_addr_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_addr_0 ]
+ # Create instance: axis_eth_in_fifo, and set properties
+ set axis_eth_in_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_eth_in_fifo ]
set_property -dict [ list \
- CONFIG.REG_CONFIG {16} \
- ] $axis_register_slice_addr_0
+ CONFIG.HAS_AEMPTY {1} \
+ CONFIG.HAS_AFULL {1} \
+ ] $axis_eth_in_fifo
+
+ # Create instance: axis_frame_generator_fifo_0, and set properties
+ set axis_frame_generator_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_frame_generator_fifo_0 ]
+ set_property -dict [ list \
+ CONFIG.HAS_AEMPTY {1} \
+ CONFIG.HAS_AFULL {1} \
+ ] $axis_frame_generator_fifo_0
# Create instance: axis_register_slice_addr_1, and set properties
set axis_register_slice_addr_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_addr_1 ]
@@ -227,12 +218,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
CONFIG.REG_CONFIG {16} \
] $axis_register_slice_addr_1
- # Create instance: axis_register_slice_data_0, and set properties
- set axis_register_slice_data_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_data_0 ]
- set_property -dict [ list \
- CONFIG.REG_CONFIG {16} \
- ] $axis_register_slice_data_0
-
# Create instance: axis_register_slice_data_1, and set properties
set axis_register_slice_data_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_data_1 ]
set_property -dict [ list \
@@ -275,8 +260,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
# Create instance: axis_work_completion_fifo_0, and set properties
set axis_work_completion_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_work_completion_fifo_0 ]
set_property -dict [ list \
- CONFIG.FIFO_DEPTH {1024} \
- CONFIG.FIFO_MEMORY_TYPE {auto} \
+ CONFIG.FIFO_DEPTH {8192} \
+ CONFIG.FIFO_MEMORY_TYPE {ultra} \
CONFIG.HAS_AEMPTY {1} \
CONFIG.HAS_AFULL {1} \
] $axis_work_completion_fifo_0
@@ -291,28 +276,36 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
CONFIG.HAS_PROG_FULL {0} \
] $axis_work_request_fifo_0
- # Create instance: calibration_addr_bram, and set properties
- set calibration_addr_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 calibration_addr_bram ]
- set_property -dict [ list \
- CONFIG.Assume_Synchronous_Clk {true} \
- CONFIG.Enable_B {Use_ENB_Pin} \
- CONFIG.Memory_Type {True_Dual_Port_RAM} \
- CONFIG.Port_A_Write_Rate {50} \
- CONFIG.Port_B_Clock {100} \
- CONFIG.Port_B_Enable_Rate {100} \
- CONFIG.Port_B_Write_Rate {50} \
- CONFIG.Use_Byte_Write_Enable {true} \
- CONFIG.Use_RSTB_Pin {true} \
- ] $calibration_addr_bram
-
# Create instance: data_collection_fsm_0, and set properties
set data_collection_fsm_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:data_collection_fsm:1.0 data_collection_fsm_0 ]
+ # Create instance: frame_generator_0, and set properties
+ set frame_generator_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:frame_generator:1.0 frame_generator_0 ]
+
# Create instance: host_writer_0, and set properties
set host_writer_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:host_writer:1.0 host_writer_0 ]
- # Create instance: internal_packet_generator_0, and set properties
- set internal_packet_generator_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:internal_packet_generator:1.0 internal_packet_generator_0 ]
+ # Create instance: internal_packet_generator_uram, and set properties
+ set internal_packet_generator_uram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 internal_packet_generator_uram ]
+ set_property -dict [ list \
+ CONFIG.Assume_Synchronous_Clk {true} \
+ CONFIG.EN_SAFETY_CKT {false} \
+ CONFIG.Enable_B {Use_ENB_Pin} \
+ CONFIG.Memory_Type {True_Dual_Port_RAM} \
+ CONFIG.Operating_Mode_A {NO_CHANGE} \
+ CONFIG.Operating_Mode_B {NO_CHANGE} \
+ CONFIG.PRIM_type_to_Implement {URAM} \
+ CONFIG.Port_A_Write_Rate {50} \
+ CONFIG.Port_B_Clock {100} \
+ CONFIG.Port_B_Enable_Rate {100} \
+ CONFIG.Port_B_Write_Rate {50} \
+ CONFIG.READ_LATENCY_A {3} \
+ CONFIG.READ_LATENCY_B {3} \
+ CONFIG.Read_Width_B {512} \
+ CONFIG.Use_Byte_Write_Enable {true} \
+ CONFIG.Use_RSTB_Pin {true} \
+ CONFIG.Write_Width_B {512} \
+ ] $internal_packet_generator_uram
# Create instance: jf_conversion_0, and set properties
set jf_conversion_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:jf_conversion:1.0 jf_conversion_0 ]
@@ -335,39 +328,45 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_CLKS {1} \
- CONFIG.NUM_MI {3} \
+ CONFIG.NUM_MI {5} \
CONFIG.NUM_SI {1} \
] $smartconnect_0
- # Create instance: timer_hbm_0, and set properties
- set timer_hbm_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:timer_hbm:1.0 timer_hbm_0 ]
+ # Create instance: smartconnect_1, and set properties
+ set smartconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_1 ]
- # Create instance: timer_host_0, and set properties
- set timer_host_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:timer_host:1.0 timer_host_0 ]
+ # Create instance: smartconnect_2, and set properties
+ set smartconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_2 ]
+
+ # Create instance: stream_merge_0, and set properties
+ set stream_merge_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:stream_merge:1.0 stream_merge_0 ]
+
+ # Create instance: timer_hbm, and set properties
+ set timer_hbm [ create_bd_cell -type ip -vlnv psi.ch:hls:timer_host:1.0 timer_hbm ]
+
+ # Create instance: timer_host, and set properties
+ set timer_host [ create_bd_cell -type ip -vlnv psi.ch:hls:timer_host:1.0 timer_host ]
# Create interface connections
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins eth_out] [get_bd_intf_pins network_stack/M00_AXIS]
- connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins eth_in] [get_bd_intf_pins network_stack/eth_in]
connect_bd_intf_net -intf_net S_AXIS_1 [get_bd_intf_pins s_axis_h2c_data] [get_bd_intf_pins axis_data_fifo_h2c_data/S_AXIS]
- connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins calibration_addr_bram/BRAM_PORTB]
- connect_bd_intf_net -intf_net axis_addr_fifo_0_M_AXIS [get_bd_intf_pins axis_addr_fifo_0/M_AXIS] [get_bd_intf_pins internal_packet_generator_0/addr_in]
- connect_bd_intf_net -intf_net axis_addr_fifo_2_M_AXIS [get_bd_intf_pins axis_addr_fifo_1/M_AXIS] [get_bd_intf_pins jf_conversion_0/addr_in]
- connect_bd_intf_net -intf_net axis_addr_fifo_3_M_AXIS [get_bd_intf_pins axis_addr_fifo_2/M_AXIS] [get_bd_intf_pins host_writer_0/addr_in]
- connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins load_calibration_0/data_in]
- connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins internal_packet_generator_0/data_in]
- connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins axis_data_fifo_2/M_AXIS] [get_bd_intf_pins timer_hbm_0/data_in]
- connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins axis_data_fifo_3/M_AXIS] [get_bd_intf_pins jf_conversion_0/data_in]
- connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS1 [get_bd_intf_pins axis_data_fifo_4/M_AXIS] [get_bd_intf_pins timer_host_0/data_in]
- connect_bd_intf_net -intf_net axis_data_fifo_8_M_AXIS [get_bd_intf_pins axis_data_fifo_5/M_AXIS] [get_bd_intf_pins host_writer_0/data_in]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_internal_packet_generator_1_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_1/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTB]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_internal_packet_generator_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_0/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTA]
+ connect_bd_intf_net -intf_net axis_addr_fifo_0_M_AXIS [get_bd_intf_pins axis_addr_fifo_0/M_AXIS] [get_bd_intf_pins jf_conversion_0/addr_in]
+ connect_bd_intf_net -intf_net axis_addr_fifo_1_M_AXIS1 [get_bd_intf_pins axis_addr_fifo_1/M_AXIS] [get_bd_intf_pins host_writer_0/addr_in]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins timer_hbm/data_in]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins jf_conversion_0/data_in]
+ connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS1 [get_bd_intf_pins axis_data_fifo_2/M_AXIS] [get_bd_intf_pins timer_host/data_in]
+ connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axis_data_fifo_3/M_AXIS] [get_bd_intf_pins host_writer_0/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_c2h_cmd_M_AXIS [get_bd_intf_pins m_axis_c2h_datamover_cmd] [get_bd_intf_pins axis_data_fifo_c2h_cmd/M_AXIS]
connect_bd_intf_net -intf_net axis_data_fifo_c2h_data_M_AXIS [get_bd_intf_pins m_axis_c2h_data] [get_bd_intf_pins axis_data_fifo_c2h_data/M_AXIS]
connect_bd_intf_net -intf_net axis_data_fifo_h2c_cmd_M_AXIS [get_bd_intf_pins m_axis_h2c_datamover_cmd] [get_bd_intf_pins axis_data_fifo_h2c_cmd/M_AXIS]
connect_bd_intf_net -intf_net axis_data_fifo_h2c_data_M_AXIS [get_bd_intf_pins axis_data_fifo_h2c_data/M_AXIS] [get_bd_intf_pins axis_register_slice_data_in_0/S_AXIS]
- connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_addr_fifo_2/S_AXIS] [get_bd_intf_pins axis_register_slice_addr_1/M_AXIS]
- connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS1 [get_bd_intf_pins axis_register_slice_data_in_0/M_AXIS] [get_bd_intf_pins load_calibration_0/host_memory_in]
- connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_data_fifo_5/S_AXIS] [get_bd_intf_pins axis_register_slice_data_1/M_AXIS]
- connect_bd_intf_net -intf_net axis_register_slice_2_M_AXIS [get_bd_intf_pins axis_addr_fifo_1/S_AXIS] [get_bd_intf_pins axis_register_slice_addr_0/M_AXIS]
- connect_bd_intf_net -intf_net axis_register_slice_data_0_M_AXIS [get_bd_intf_pins axis_data_fifo_2/S_AXIS] [get_bd_intf_pins axis_register_slice_data_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_eth_in_fifo_M_AXIS [get_bd_intf_pins axis_eth_in_fifo/M_AXIS] [get_bd_intf_pins network_stack/eth_in]
+ connect_bd_intf_net -intf_net axis_frame_generator_fifo_0_M_AXIS [get_bd_intf_pins axis_frame_generator_fifo_0/M_AXIS] [get_bd_intf_pins stream_merge_0/input_0]
+ connect_bd_intf_net -intf_net axis_register_slice_addr_1_M_AXIS [get_bd_intf_pins axis_addr_fifo_1/S_AXIS] [get_bd_intf_pins axis_register_slice_addr_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_register_slice_data_1_M_AXIS [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins axis_register_slice_data_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_register_slice_data_in_0_M_AXIS1 [get_bd_intf_pins axis_register_slice_data_in_0/M_AXIS] [get_bd_intf_pins load_calibration_0/host_memory_in]
connect_bd_intf_net -intf_net axis_register_slice_host_mem_M_AXIS [get_bd_intf_pins axis_data_fifo_c2h_data/S_AXIS] [get_bd_intf_pins axis_register_slice_host_mem/M_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_udp_M_AXIS [get_bd_intf_pins axis_register_slice_udp/M_AXIS] [get_bd_intf_pins data_collection_fsm_0/eth_in]
connect_bd_intf_net -intf_net axis_udp_addr_fifo_0_M_AXIS [get_bd_intf_pins axis_udp_addr_fifo_0/M_AXIS] [get_bd_intf_pins data_collection_fsm_0/addr_in]
@@ -376,16 +375,17 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_intf_net -intf_net axis_work_request_fifo_0_M_AXIS [get_bd_intf_pins axis_work_request_fifo_0/M_AXIS] [get_bd_intf_pins host_writer_0/s_axis_work_request]
connect_bd_intf_net -intf_net data_collection_fsm_0_addr_out [get_bd_intf_pins axis_addr_fifo_0/S_AXIS] [get_bd_intf_pins data_collection_fsm_0/addr_out]
connect_bd_intf_net -intf_net data_collection_fsm_0_data_out [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins data_collection_fsm_0/data_out]
+ connect_bd_intf_net -intf_net eth_in_1 [get_bd_intf_pins eth_in] [get_bd_intf_pins stream_merge_0/input_1]
+ connect_bd_intf_net -intf_net frame_generator_0_data_out [get_bd_intf_pins axis_frame_generator_fifo_0/S_AXIS] [get_bd_intf_pins frame_generator_0/data_out]
+ connect_bd_intf_net -intf_net frame_generator_0_m_axi_uram [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_1/S_AXI] [get_bd_intf_pins frame_generator_0/m_axi_uram]
connect_bd_intf_net -intf_net host_writer_0_datamover_out_cmd [get_bd_intf_pins axis_data_fifo_c2h_cmd/S_AXIS] [get_bd_intf_pins host_writer_0/datamover_out_cmd]
connect_bd_intf_net -intf_net host_writer_0_host_memory_out [get_bd_intf_pins axis_register_slice_host_mem/S_AXIS] [get_bd_intf_pins host_writer_0/host_memory_out]
connect_bd_intf_net -intf_net host_writer_0_m_axis_completion [get_bd_intf_pins axis_work_completion_fifo_0/S_AXIS] [get_bd_intf_pins host_writer_0/m_axis_completion]
- connect_bd_intf_net -intf_net internal_packet_generator_0_addr_out [get_bd_intf_pins axis_register_slice_addr_0/S_AXIS] [get_bd_intf_pins internal_packet_generator_0/addr_out]
- connect_bd_intf_net -intf_net internal_packet_generator_0_data_out [get_bd_intf_pins axis_register_slice_data_0/S_AXIS] [get_bd_intf_pins internal_packet_generator_0/data_out]
connect_bd_intf_net -intf_net jf_conversion_0_addr_out [get_bd_intf_pins axis_register_slice_addr_1/S_AXIS] [get_bd_intf_pins jf_conversion_0/addr_out]
- connect_bd_intf_net -intf_net jf_conversion_0_data_out [get_bd_intf_pins axis_data_fifo_4/S_AXIS] [get_bd_intf_pins jf_conversion_0/data_out]
- connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p0 [get_bd_intf_pins m_axi_d_hbm_p0] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p0]
+ connect_bd_intf_net -intf_net jf_conversion_0_data_out [get_bd_intf_pins axis_data_fifo_2/S_AXIS] [get_bd_intf_pins jf_conversion_0/data_out]
+ connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p0 [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/S00_AXI]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p1] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p1]
- connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p2 [get_bd_intf_pins m_axi_d_hbm_p2] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p2]
+ connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p2 [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p2] [get_bd_intf_pins smartconnect_2/S00_AXI]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p3 [get_bd_intf_pins m_axi_d_hbm_p3] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p3]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p4 [get_bd_intf_pins m_axi_d_hbm_p4] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p4]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p5 [get_bd_intf_pins m_axi_d_hbm_p5] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p5]
@@ -395,48 +395,57 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p9 [get_bd_intf_pins m_axi_d_hbm_p9] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p9]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p10 [get_bd_intf_pins m_axi_d_hbm_p10] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p10]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p11 [get_bd_intf_pins m_axi_d_hbm_p11] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p11]
- connect_bd_intf_net -intf_net load_calibration_0_data_out [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins load_calibration_0/data_out]
connect_bd_intf_net -intf_net load_calibration_0_datamover_in_cmd [get_bd_intf_pins axis_data_fifo_h2c_cmd/S_AXIS] [get_bd_intf_pins load_calibration_0/datamover_in_cmd]
- connect_bd_intf_net -intf_net load_calibration_0_in_mem_location_PORTA [get_bd_intf_pins calibration_addr_bram/BRAM_PORTA] [get_bd_intf_pins load_calibration_0/in_mem_location_PORTA]
+ connect_bd_intf_net -intf_net load_calibration_0_m_axi_d_hbm_p0 [get_bd_intf_pins load_calibration_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/S01_AXI]
+ connect_bd_intf_net -intf_net load_calibration_0_m_axi_d_hbm_p1 [get_bd_intf_pins load_calibration_0/m_axi_d_hbm_p1] [get_bd_intf_pins smartconnect_2/S01_AXI]
connect_bd_intf_net -intf_net mailbox_0_M1_AXIS [get_bd_intf_pins axis_work_request_fifo_0/S_AXIS] [get_bd_intf_pins mailbox_0/M1_AXIS]
connect_bd_intf_net -intf_net network_stack_udp_addr_out [get_bd_intf_pins axis_udp_addr_fifo_0/S_AXIS] [get_bd_intf_pins network_stack/udp_addr_out]
connect_bd_intf_net -intf_net network_stack_udp_out [get_bd_intf_pins axis_udp_fifo_0/S_AXIS] [get_bd_intf_pins network_stack/udp_out]
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins smartconnect_0/S00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins action_config_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins mailbox_0/S0_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
- connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
- connect_bd_intf_net -intf_net timer_hbm_0_data_out [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins timer_hbm_0/data_out]
- connect_bd_intf_net -intf_net timer_host_0_data_out [get_bd_intf_pins axis_register_slice_data_1/S_AXIS] [get_bd_intf_pins timer_host_0/data_out]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins load_calibration_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins frame_generator_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M04_AXI]
+ connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p2] [get_bd_intf_pins smartconnect_2/M00_AXI]
+ connect_bd_intf_net -intf_net stream_merge_0_output_r [get_bd_intf_pins axis_eth_in_fifo/S_AXIS] [get_bd_intf_pins stream_merge_0/output_r]
+ connect_bd_intf_net -intf_net timer_hbm_data_out [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins timer_hbm/data_out]
+ connect_bd_intf_net -intf_net timer_host_data_out [get_bd_intf_pins axis_register_slice_data_1/S_AXIS] [get_bd_intf_pins timer_host/data_out]
# Create port connections
connect_bd_net -net action_config_0_clear_counters [get_bd_pins action_config_0/clear_counters] [get_bd_pins network_stack/clear_counters]
- connect_bd_net -net action_config_0_data_collection_cancel [get_bd_pins action_config_0/data_collection_cancel] [get_bd_pins data_collection_fsm_0/in_cancel] [get_bd_pins internal_packet_generator_0/in_cancel]
+ connect_bd_net -net action_config_0_data_collection_cancel [get_bd_pins action_config_0/data_collection_cancel] [get_bd_pins data_collection_fsm_0/in_cancel]
connect_bd_net -net action_config_0_data_collection_fsm_start [get_bd_pins action_config_0/data_collection_start] [get_bd_pins data_collection_fsm_0/in_run] [get_bd_pins network_stack/data_collection_start]
connect_bd_net -net action_config_0_data_collection_mode [get_bd_pins action_config_0/data_collection_mode] [get_bd_pins data_collection_fsm_0/mode]
- connect_bd_net -net action_config_0_fpga_ipv4_addr [get_bd_pins action_config_0/fpga_ipv4_addr] [get_bd_pins network_stack/fpga_ipv4_addr]
- connect_bd_net -net action_config_0_fpga_mac_addr [get_bd_pins action_config_0/fpga_mac_addr] [get_bd_pins network_stack/fpga_mac_addr]
+ connect_bd_net -net action_config_0_fpga_ipv4_addr [get_bd_pins action_config_0/fpga_ipv4_addr] [get_bd_pins frame_generator_0/src_ipv4_addr] [get_bd_pins network_stack/fpga_ipv4_addr]
+ connect_bd_net -net action_config_0_fpga_mac_addr [get_bd_pins action_config_0/fpga_mac_addr] [get_bd_pins frame_generator_0/src_mac_addr] [get_bd_pins network_stack/fpga_mac_addr]
connect_bd_net -net action_config_0_frames_per_trigger [get_bd_pins action_config_0/nframes] [get_bd_pins data_collection_fsm_0/nframes]
+ connect_bd_net -net action_config_0_hbm_size_bytes [get_bd_pins action_config_0/hbm_size_bytes] [get_bd_pins data_collection_fsm_0/hbm_size_bytes] [get_bd_pins load_calibration_0/hbm_size_bytes]
connect_bd_net -net action_config_0_nmodules [get_bd_pins action_config_0/nmodules] [get_bd_pins data_collection_fsm_0/nmodules]
connect_bd_net -net action_config_0_nstorage_cells [get_bd_pins action_config_0/nstorage_cells] [get_bd_pins data_collection_fsm_0/nstorage_cells]
connect_bd_net -net action_config_0_one_over_energy [get_bd_pins action_config_0/one_over_energy] [get_bd_pins data_collection_fsm_0/one_over_energy]
- connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_addr_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_register_slice_addr_0/aclk] [get_bd_pins axis_register_slice_addr_1/aclk] [get_bd_pins axis_register_slice_data_0/aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins internal_packet_generator_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins network_stack/axiclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins timer_hbm_0/ap_clk] [get_bd_pins timer_host_0/ap_clk]
- connect_bd_net -net apb_complete_1 [get_bd_pins apb_complete] [get_bd_pins action_config_0/apb_complete_0]
- connect_bd_net -net axilite_ctrl_infrastructure_qsfp_led_busy [get_bd_pins qsfp_led_busy] [get_bd_pins action_config_0/qsfp_led_busy]
- connect_bd_net -net axilite_ctrl_infrastructure_qsfp_led_conn [get_bd_pins qsfp_led_conn] [get_bd_pins action_config_0/qsfp_led_conn]
- connect_bd_net -net aximm_host_infrastructure_err_encountered [get_bd_pins mm2s_error] [get_bd_pins action_config_0/mm2s_error]
- connect_bd_net -net aximm_host_infrastructure_err_encountered1 [get_bd_pins s2mm_error] [get_bd_pins action_config_0/s2mm_error]
- connect_bd_net -net axis_addr_fifo_2_almost_empty [get_bd_pins action_config_0/calib_addr_fifo_empty] [get_bd_pins axis_addr_fifo_1/almost_empty]
- connect_bd_net -net axis_addr_fifo_2_almost_full [get_bd_pins action_config_0/calib_addr_fifo_full] [get_bd_pins axis_addr_fifo_1/almost_full]
- connect_bd_net -net axis_addr_fifo_4_almost_empty [get_bd_pins action_config_0/last_addr_fifo_empty] [get_bd_pins axis_addr_fifo_2/almost_empty]
- connect_bd_net -net axis_addr_fifo_4_almost_full [get_bd_pins action_config_0/last_addr_fifo_full] [get_bd_pins axis_addr_fifo_2/almost_full]
- connect_bd_net -net axis_data_fifo_10_almost_empty [get_bd_pins action_config_0/last_data_fifo_empty] [get_bd_pins axis_data_fifo_5/almost_empty]
- connect_bd_net -net axis_data_fifo_10_almost_full [get_bd_pins action_config_0/last_data_fifo_full] [get_bd_pins axis_data_fifo_5/almost_full]
- connect_bd_net -net axis_data_fifo_4_almost_empty [get_bd_pins action_config_0/calib_data_fifo_empty] [get_bd_pins axis_data_fifo_3/almost_empty]
- connect_bd_net -net axis_data_fifo_4_almost_full [get_bd_pins action_config_0/calib_data_fifo_full] [get_bd_pins axis_data_fifo_3/almost_full]
- connect_bd_net -net axis_data_fifo_c2h_cmd_almost_empty [get_bd_pins action_config_0/host_mem_cmd_fifo_empty] [get_bd_pins axis_data_fifo_c2h_cmd/almost_empty]
- connect_bd_net -net axis_data_fifo_c2h_cmd_almost_full [get_bd_pins action_config_0/host_mem_cmd_fifo_full] [get_bd_pins axis_data_fifo_c2h_cmd/almost_full]
- connect_bd_net -net axis_data_fifo_c2h_data_almost_empty [get_bd_pins action_config_0/host_mem_data_fifo_empty] [get_bd_pins axis_data_fifo_c2h_data/almost_empty]
- connect_bd_net -net axis_data_fifo_c2h_data_almost_full [get_bd_pins action_config_0/host_mem_data_fifo_full] [get_bd_pins axis_data_fifo_c2h_data/almost_full]
+ connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_register_slice_addr_1/aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins network_stack/axiclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk]
+ connect_bd_net -net axis_addr_fifo_0_almost_empty [get_bd_pins action_config_0/calib_addr_fifo_empty] [get_bd_pins axis_addr_fifo_0/almost_empty]
+ connect_bd_net -net axis_addr_fifo_0_almost_full [get_bd_pins action_config_0/calib_addr_fifo_full] [get_bd_pins axis_addr_fifo_0/almost_full]
+ connect_bd_net -net axis_addr_fifo_4_almost_empty [get_bd_pins action_config_0/last_addr_fifo_empty] [get_bd_pins axis_addr_fifo_1/almost_empty]
+ connect_bd_net -net axis_addr_fifo_4_almost_full [get_bd_pins action_config_0/last_addr_fifo_full] [get_bd_pins axis_addr_fifo_1/almost_full]
+ connect_bd_net -net axis_data_fifo_10_almost_empty [get_bd_pins action_config_0/last_data_fifo_empty] [get_bd_pins axis_data_fifo_3/almost_empty]
+ connect_bd_net -net axis_data_fifo_10_almost_full [get_bd_pins action_config_0/last_data_fifo_full] [get_bd_pins axis_data_fifo_3/almost_full]
+ connect_bd_net -net axis_data_fifo_4_almost_empty [get_bd_pins action_config_0/calib_data_fifo_empty] [get_bd_pins axis_data_fifo_1/almost_empty]
+ connect_bd_net -net axis_data_fifo_4_almost_full [get_bd_pins action_config_0/calib_data_fifo_full] [get_bd_pins axis_data_fifo_1/almost_full]
+ connect_bd_net -net axis_data_fifo_c2h_cmd_almost_empty [get_bd_pins action_config_0/c2h_cmd_fifo_empty] [get_bd_pins axis_data_fifo_c2h_cmd/almost_empty]
+ connect_bd_net -net axis_data_fifo_c2h_cmd_almost_full [get_bd_pins action_config_0/c2h_cmd_fifo_full] [get_bd_pins axis_data_fifo_c2h_cmd/almost_full]
+ connect_bd_net -net axis_data_fifo_c2h_data_almost_empty [get_bd_pins action_config_0/c2h_data_fifo_empty] [get_bd_pins axis_data_fifo_c2h_data/almost_empty]
+ connect_bd_net -net axis_data_fifo_c2h_data_almost_full [get_bd_pins action_config_0/c2h_data_fifo_full] [get_bd_pins axis_data_fifo_c2h_data/almost_full]
+ connect_bd_net -net axis_data_fifo_h2c_cmd_almost_empty [get_bd_pins action_config_0/h2c_cmd_fifo_empty] [get_bd_pins axis_data_fifo_h2c_cmd/almost_empty]
+ connect_bd_net -net axis_data_fifo_h2c_cmd_almost_full [get_bd_pins action_config_0/h2c_cmd_fifo_full] [get_bd_pins axis_data_fifo_h2c_cmd/almost_full]
+ connect_bd_net -net axis_data_fifo_h2c_data_almost_empty [get_bd_pins action_config_0/h2c_data_fifo_empty] [get_bd_pins axis_data_fifo_h2c_data/almost_empty]
+ connect_bd_net -net axis_data_fifo_h2c_data_almost_full [get_bd_pins action_config_0/h2c_data_fifo_full] [get_bd_pins axis_data_fifo_h2c_data/almost_full]
+ connect_bd_net -net axis_eth_in_fifo_almost_empty [get_bd_pins action_config_0/eth_in_fifo_empty] [get_bd_pins axis_eth_in_fifo/almost_empty]
+ connect_bd_net -net axis_eth_in_fifo_almost_full [get_bd_pins action_config_0/eth_in_fifo_full] [get_bd_pins axis_eth_in_fifo/almost_full]
+ connect_bd_net -net axis_frame_generator_fifo_0_almost_empty [get_bd_pins action_config_0/frame_generator_fifo_empty] [get_bd_pins axis_frame_generator_fifo_0/almost_empty]
+ connect_bd_net -net axis_frame_generator_fifo_0_almost_full [get_bd_pins action_config_0/frame_generator_fifo_full] [get_bd_pins axis_frame_generator_fifo_0/almost_full]
connect_bd_net -net axis_udp_fifo_0_almost_empty [get_bd_pins action_config_0/udp_fifo_empty] [get_bd_pins axis_udp_fifo_0/almost_empty]
connect_bd_net -net axis_udp_fifo_0_almost_full [get_bd_pins action_config_0/udp_fifo_full] [get_bd_pins axis_udp_fifo_0/almost_full]
connect_bd_net -net axis_work_completion_fifo_0_almost_empty [get_bd_pins action_config_0/work_compl_fifo_empty] [get_bd_pins axis_work_completion_fifo_0/almost_empty]
@@ -444,14 +453,9 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_net -net axis_work_request_fifo_0_almost_empty [get_bd_pins action_config_0/work_req_fifo_empty] [get_bd_pins axis_work_request_fifo_0/almost_empty]
connect_bd_net -net axis_work_request_fifo_0_almost_full [get_bd_pins action_config_0/work_req_fifo_full] [get_bd_pins axis_work_request_fifo_0/almost_full]
connect_bd_net -net data_collection_fsm_0_out_idle_V [get_bd_pins action_config_0/data_collection_idle] [get_bd_pins data_collection_fsm_0/out_idle]
- connect_bd_net -net eth_busy_1 [get_bd_pins eth_busy] [get_bd_pins action_config_0/eth_busy]
- connect_bd_net -net eth_stat_rx_aligned_1 [get_bd_pins eth_stat_rx_aligned] [get_bd_pins action_config_0/eth_stat_rx_aligned]
- connect_bd_net -net eth_stat_rx_packet_bad_fcs_1 [get_bd_pins eth_stat_rx_packet_bad_fcs] [get_bd_pins action_config_0/eth_stat_rx_packet_bad_fcs]
- connect_bd_net -net eth_stat_rx_status_1 [get_bd_pins eth_stat_rx_status] [get_bd_pins action_config_0/eth_stat_rx_status]
- connect_bd_net -net hbm_temp_trip_1 [get_bd_pins hbm_temp_trip] [get_bd_pins action_config_0/hbm_temp_trip]
- connect_bd_net -net hbm_temperature_1 [get_bd_pins hbm_temperature] [get_bd_pins action_config_0/hbm_temperature]
connect_bd_net -net host_writer_0_err_reg_V [get_bd_pins action_config_0/host_writer_err] [get_bd_pins host_writer_0/err_reg]
connect_bd_net -net host_writer_0_err_reg_V_ap_vld [get_bd_pins action_config_0/host_writer_err_valid] [get_bd_pins host_writer_0/err_reg_ap_vld]
+ connect_bd_net -net host_writer_0_idle [get_bd_pins action_config_0/host_writer_idle] [get_bd_pins host_writer_0/idle]
connect_bd_net -net host_writer_0_packets_processed [get_bd_pins action_config_0/packets_processed] [get_bd_pins host_writer_0/packets_processed]
connect_bd_net -net host_writer_0_packets_processed_ap_vld [get_bd_pins action_config_0/packets_processed_valid] [get_bd_pins host_writer_0/packets_processed_ap_vld]
connect_bd_net -net mailbox_0_Interrupt_0 [get_bd_pins action_config_0/mailbox_interrupt_0] [get_bd_pins mailbox_0/Interrupt_0]
@@ -468,13 +472,13 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_net -net network_stack_packets_sls_ap_vld [get_bd_pins action_config_0/packets_sls_valid] [get_bd_pins network_stack/packets_sls_ap_vld]
connect_bd_net -net network_stack_packets_udp [get_bd_pins action_config_0/packets_udp] [get_bd_pins network_stack/packets_udp]
connect_bd_net -net network_stack_packets_udp_ap_vld [get_bd_pins action_config_0/packets_udp_valid] [get_bd_pins network_stack/packets_udp_ap_vld]
- connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_addr_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_register_slice_addr_0/aresetn] [get_bd_pins axis_register_slice_addr_1/aresetn] [get_bd_pins axis_register_slice_data_0/aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn]
- connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins internal_packet_generator_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins timer_hbm_0/ap_rst_n] [get_bd_pins timer_host_0/ap_rst_n]
- connect_bd_net -net timer_hbm_0_counter [get_bd_pins action_config_0/stalls_hbm] [get_bd_pins timer_hbm_0/counter]
- connect_bd_net -net timer_hbm_0_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm_0/counter_ap_vld]
- connect_bd_net -net timer_host_0_counter [get_bd_pins action_config_0/stalls_host] [get_bd_pins timer_host_0/counter]
- connect_bd_net -net timer_host_0_counter_ap_vld [get_bd_pins action_config_0/stalls_host_valid] [get_bd_pins timer_host_0/counter_ap_vld]
+ connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_eth_in_fifo/s_axis_aresetn] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aresetn] [get_bd_pins axis_register_slice_addr_1/aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn]
+ connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins frame_generator_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins stream_merge_0/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n]
+ connect_bd_net -net timer_hbm_counter [get_bd_pins action_config_0/stalls_hbm] [get_bd_pins timer_hbm/counter]
+ connect_bd_net -net timer_hbm_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm/counter_ap_vld]
+ connect_bd_net -net timer_host_counter [get_bd_pins action_config_0/stalls_host] [get_bd_pins timer_host/counter]
+ connect_bd_net -net timer_host_counter_ap_vld [get_bd_pins action_config_0/stalls_host_valid] [get_bd_pins timer_host/counter_ap_vld]
# Restore current instance
current_bd_instance $oldCurInst
-}
\ No newline at end of file
+}
diff --git a/receiver/scripts/mac_100g_pcie.tcl b/fpga/scripts/mac_100g_pcie.tcl
similarity index 99%
rename from receiver/scripts/mac_100g_pcie.tcl
rename to fpga/scripts/mac_100g_pcie.tcl
index 0a157394..8a6f64c5 100644
--- a/receiver/scripts/mac_100g_pcie.tcl
+++ b/fpga/scripts/mac_100g_pcie.tcl
@@ -1,5 +1,4 @@
-## Copyright (2019-2022) Paul Scherrer Institute
-## SPDX-License-Identifier: CERN-OHL-S-2.0
+## Copyright (2019-2023) Paul Scherrer Institute
# Hierarchical cell: mac_100g
proc create_hier_cell_mac_100g { parentCell nameHier } {
diff --git a/receiver/scripts/network_stack.tcl b/fpga/scripts/network_stack.tcl
similarity index 99%
rename from receiver/scripts/network_stack.tcl
rename to fpga/scripts/network_stack.tcl
index fb5b842a..3fe69d9e 100644
--- a/receiver/scripts/network_stack.tcl
+++ b/fpga/scripts/network_stack.tcl
@@ -1,5 +1,4 @@
-## Copyright (2019-2022) Paul Scherrer Institute
-## SPDX-License-Identifier: CERN-OHL-S-2.0
+## Copyright (2019-2023) Paul Scherrer Institute
# Hierarchical cell: network_stack
proc create_hier_cell_network_stack { parentCell nameHier } {
diff --git a/fpga/scripts/pcie_dma.tcl b/fpga/scripts/pcie_dma.tcl
new file mode 100644
index 00000000..ad976b87
--- /dev/null
+++ b/fpga/scripts/pcie_dma.tcl
@@ -0,0 +1,221 @@
+## Copyright (2019-2023) Paul Scherrer Institute
+
+# Hierarchical cell: pcie_dma_0
+proc create_hier_cell_pcie_dma_0 { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_pcie_dma() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_ctrl
+
+ create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_h2c_data
+
+ create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_mgt
+
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk
+
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_dma_ctrl
+
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_c2h_cmd
+
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_c2h_data
+
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_h2c_cmd
+
+
+ # Create pins
+ create_bd_pin -dir O -type clk axi_aclk
+ create_bd_pin -dir O -type rst axi_aresetn
+ create_bd_pin -dir I -type rst axi_clk_resetn
+ create_bd_pin -dir I -type rst pcie_perstn
+ create_bd_pin -dir I -type clk refclk200
+ create_bd_pin -dir I -type rst refclk200_resetn
+ create_bd_pin -dir I usr_irq_req
+
+ # Create instance: axi_firewall_0, and set properties
+ set axi_firewall_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_firewall:1.2 axi_firewall_0 ]
+
+ # Create instance: axis_clock_converter_c2h_cmd, and set properties
+ set axis_clock_converter_c2h_cmd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_c2h_cmd ]
+ set_property -dict [ list \
+ CONFIG.SYNCHRONIZATION_STAGES {3} \
+ ] $axis_clock_converter_c2h_cmd
+
+ # Create instance: axis_clock_converter_c2h_data, and set properties
+ set axis_clock_converter_c2h_data [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_c2h_data ]
+ set_property -dict [ list \
+ CONFIG.SYNCHRONIZATION_STAGES {3} \
+ ] $axis_clock_converter_c2h_data
+
+ # Create instance: axis_clock_converter_h2c_cmd, and set properties
+ set axis_clock_converter_h2c_cmd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_h2c_cmd ]
+ set_property -dict [ list \
+ CONFIG.SYNCHRONIZATION_STAGES {3} \
+ ] $axis_clock_converter_h2c_cmd
+
+ # Create instance: axis_clock_converter_h2c_data, and set properties
+ set axis_clock_converter_h2c_data [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_h2c_data ]
+ set_property -dict [ list \
+ CONFIG.SYNCHRONIZATION_STAGES {3} \
+ ] $axis_clock_converter_h2c_data
+
+ # Create instance: gen_xdma_descriptor_c2h, and set properties
+ set block_name gen_xdma_descriptor
+ set block_cell_name gen_xdma_descriptor_c2h
+ if { [catch {set gen_xdma_descriptor_c2h [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+ return 1
+ } elseif { $gen_xdma_descriptor_c2h eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+ return 1
+ }
+
+ # Create instance: gen_xdma_descriptor_h2c, and set properties
+ set block_name gen_xdma_descriptor
+ set block_cell_name gen_xdma_descriptor_h2c
+ if { [catch {set gen_xdma_descriptor_h2c [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+ return 1
+ } elseif { $gen_xdma_descriptor_h2c eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+ return 1
+ }
+
+ # Create instance: pcie_clk_buf_inst, and set properties
+ set pcie_clk_buf_inst [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 pcie_clk_buf_inst ]
+ set_property -dict [ list \
+ CONFIG.C_BUF_TYPE {IBUFDSGTE} \
+ ] $pcie_clk_buf_inst
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {2} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xdma_0, and set properties
+ set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
+ set_property -dict [ list \
+ CONFIG.INS_LOSS_NYQ {15} \
+ CONFIG.PF0_DEVICE_ID_mqdma {9048} \
+ CONFIG.PF0_SRIOV_VF_DEVICE_ID {A048} \
+ CONFIG.PF1_SRIOV_VF_DEVICE_ID {A148} \
+ CONFIG.PF2_DEVICE_ID_mqdma {9248} \
+ CONFIG.PF2_SRIOV_VF_DEVICE_ID {A248} \
+ CONFIG.PF3_DEVICE_ID_mqdma {9348} \
+ CONFIG.PF3_SRIOV_VF_DEVICE_ID {A348} \
+ CONFIG.axi_data_width {512_bit} \
+ CONFIG.axi_id_width {2} \
+ CONFIG.axil_master_64bit_en {false} \
+ CONFIG.axilite_master_en {true} \
+ CONFIG.axilite_master_size {16} \
+ CONFIG.axisten_freq {250} \
+ CONFIG.cfg_mgmt_if {false} \
+ CONFIG.copy_pf0 {true} \
+ CONFIG.coreclk_freq {500} \
+ CONFIG.dsc_bypass_rd {0001} \
+ CONFIG.dsc_bypass_wr {0001} \
+ CONFIG.en_gt_selection {true} \
+ CONFIG.ins_loss_profile {Add-in_Card} \
+ CONFIG.mode_selection {Advanced} \
+ CONFIG.pcie_blk_locn {PCIE4C_X1Y1} \
+ CONFIG.pf0_base_class_menu {Processing_accelerators} \
+ CONFIG.pf0_class_code {120000} \
+ CONFIG.pf0_class_code_base {12} \
+ CONFIG.pf0_class_code_interface {00} \
+ CONFIG.pf0_class_code_sub {00} \
+ CONFIG.pf0_device_id {9048} \
+ CONFIG.pf0_msix_cap_pba_bir {BAR_1} \
+ CONFIG.pf0_msix_cap_pba_offset {00008FE0} \
+ CONFIG.pf0_msix_cap_table_bir {BAR_1} \
+ CONFIG.pf0_msix_cap_table_offset {00008000} \
+ CONFIG.pf0_msix_cap_table_size {01F} \
+ CONFIG.pf0_msix_enabled {true} \
+ CONFIG.pf0_sub_class_interface_menu {Unknown} \
+ CONFIG.pf0_subsystem_id {5232} \
+ CONFIG.pf0_subsystem_vendor_id {10EE} \
+ CONFIG.pf1_msix_cap_pba_offset {00000000} \
+ CONFIG.pf1_msix_cap_table_offset {00000000} \
+ CONFIG.pf1_msix_cap_table_size {000} \
+ CONFIG.pl_link_cap_max_link_speed {16.0_GT/s} \
+ CONFIG.pl_link_cap_max_link_width {X8} \
+ CONFIG.plltype {QPLL0} \
+ CONFIG.runbit_fix {false} \
+ CONFIG.select_quad {GTY_Quad_227} \
+ CONFIG.vendor_id {10EE} \
+ CONFIG.xdma_axi_intf_mm {AXI_Stream} \
+ CONFIG.xdma_axilite_slave {true} \
+ CONFIG.xdma_wnum_chnl {1} \
+ ] $xdma_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins s_axis_c2h_cmd] [get_bd_intf_pins axis_clock_converter_c2h_cmd/S_AXIS]
+ connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins m_axi_ctrl] [get_bd_intf_pins axi_firewall_0/M_AXI]
+ connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins pcie_mgt] [get_bd_intf_pins xdma_0/pcie_mgt]
+ connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins s_axis_c2h_data] [get_bd_intf_pins axis_clock_converter_c2h_data/S_AXIS]
+ connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins pcie_refclk] [get_bd_intf_pins pcie_clk_buf_inst/CLK_IN_D]
+ connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins m_axis_h2c_data] [get_bd_intf_pins axis_clock_converter_h2c_data/M_AXIS]
+ connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins s_axis_h2c_cmd] [get_bd_intf_pins axis_clock_converter_h2c_cmd/S_AXIS]
+ connect_bd_intf_net -intf_net axis_clock_converter_c2h_cmd_M_AXIS [get_bd_intf_pins axis_clock_converter_c2h_cmd/M_AXIS] [get_bd_intf_pins gen_xdma_descriptor_c2h/S_AXIS]
+ connect_bd_intf_net -intf_net axis_clock_converter_c2h_data_M_AXIS [get_bd_intf_pins axis_clock_converter_c2h_data/M_AXIS] [get_bd_intf_pins xdma_0/S_AXIS_C2H_0]
+ connect_bd_intf_net -intf_net axis_clock_converter_h2c_cmd_M_AXIS [get_bd_intf_pins axis_clock_converter_h2c_cmd/M_AXIS] [get_bd_intf_pins gen_xdma_descriptor_h2c/S_AXIS]
+ connect_bd_intf_net -intf_net s_axi_dma_ctrl_1 [get_bd_intf_pins s_axi_dma_ctrl] [get_bd_intf_pins xdma_0/S_AXI_LITE]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_firewall_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_firewall_0/S_AXI_CTL] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net xdma_0_M_AXIS_H2C_0 [get_bd_intf_pins axis_clock_converter_h2c_data/S_AXIS] [get_bd_intf_pins xdma_0/M_AXIS_H2C_0]
+ connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE]
+
+ # Create port connections
+ connect_bd_net -net gen_xdma_descriptor_c2h_0_dsc_addr [get_bd_pins gen_xdma_descriptor_c2h/dsc_addr] [get_bd_pins xdma_0/c2h_dsc_byp_dst_addr_0] [get_bd_pins xdma_0/c2h_dsc_byp_src_addr_0]
+ connect_bd_net -net gen_xdma_descriptor_c2h_0_dsc_ctl [get_bd_pins gen_xdma_descriptor_c2h/dsc_ctl] [get_bd_pins xdma_0/c2h_dsc_byp_ctl_0]
+ connect_bd_net -net gen_xdma_descriptor_c2h_0_dsc_len [get_bd_pins gen_xdma_descriptor_c2h/dsc_len] [get_bd_pins xdma_0/c2h_dsc_byp_len_0]
+ connect_bd_net -net gen_xdma_descriptor_c2h_0_dsc_load [get_bd_pins gen_xdma_descriptor_c2h/dsc_load] [get_bd_pins xdma_0/c2h_dsc_byp_load_0]
+ connect_bd_net -net gen_xdma_descriptor_h2c_0_dsc_addr [get_bd_pins gen_xdma_descriptor_h2c/dsc_addr] [get_bd_pins xdma_0/h2c_dsc_byp_dst_addr_0] [get_bd_pins xdma_0/h2c_dsc_byp_src_addr_0]
+ connect_bd_net -net gen_xdma_descriptor_h2c_0_dsc_ctl [get_bd_pins gen_xdma_descriptor_h2c/dsc_ctl] [get_bd_pins xdma_0/h2c_dsc_byp_ctl_0]
+ connect_bd_net -net gen_xdma_descriptor_h2c_0_dsc_len [get_bd_pins gen_xdma_descriptor_h2c/dsc_len] [get_bd_pins xdma_0/h2c_dsc_byp_len_0]
+ connect_bd_net -net gen_xdma_descriptor_h2c_0_dsc_load [get_bd_pins gen_xdma_descriptor_h2c/dsc_load] [get_bd_pins xdma_0/h2c_dsc_byp_load_0]
+ connect_bd_net -net pcie_clk_buf_inst_IBUF_DS_ODIV2 [get_bd_pins pcie_clk_buf_inst/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk]
+ connect_bd_net -net pcie_clk_buf_inst_IBUF_OUT [get_bd_pins pcie_clk_buf_inst/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt]
+ connect_bd_net -net pcie_perstn_1 [get_bd_pins pcie_perstn] [get_bd_pins xdma_0/sys_rst_n]
+ connect_bd_net -net net_refclk200 [get_bd_pins refclk200] [get_bd_pins axis_clock_converter_c2h_cmd/s_axis_aclk] [get_bd_pins axis_clock_converter_c2h_data/s_axis_aclk] [get_bd_pins axis_clock_converter_h2c_cmd/s_axis_aclk] [get_bd_pins axis_clock_converter_h2c_data/m_axis_aclk]
+ connect_bd_net -net net_refclk200_resetn [get_bd_pins refclk200_resetn] [get_bd_pins axis_clock_converter_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_clock_converter_c2h_data/s_axis_aresetn] [get_bd_pins axis_clock_converter_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_clock_converter_h2c_data/m_axis_aresetn]
+ connect_bd_net -net s_axis_aresetn_1 [get_bd_pins axi_clk_resetn] [get_bd_pins axi_firewall_0/aresetn] [get_bd_pins axis_clock_converter_c2h_cmd/m_axis_aresetn] [get_bd_pins axis_clock_converter_c2h_data/m_axis_aresetn] [get_bd_pins axis_clock_converter_h2c_cmd/m_axis_aresetn] [get_bd_pins axis_clock_converter_h2c_data/s_axis_aresetn] [get_bd_pins gen_xdma_descriptor_c2h/resetn] [get_bd_pins gen_xdma_descriptor_h2c/resetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net usr_irq_req_1 [get_bd_pins usr_irq_req] [get_bd_pins xdma_0/usr_irq_req]
+ connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_aclk] [get_bd_pins axi_firewall_0/aclk] [get_bd_pins axis_clock_converter_c2h_cmd/m_axis_aclk] [get_bd_pins axis_clock_converter_c2h_data/m_axis_aclk] [get_bd_pins axis_clock_converter_h2c_cmd/m_axis_aclk] [get_bd_pins axis_clock_converter_h2c_data/s_axis_aclk] [get_bd_pins gen_xdma_descriptor_c2h/clk] [get_bd_pins gen_xdma_descriptor_h2c/clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins xdma_0/axi_aclk]
+ connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_aresetn] [get_bd_pins xdma_0/axi_aresetn]
+ connect_bd_net -net xdma_0_c2h_dsc_byp_ready_0 [get_bd_pins gen_xdma_descriptor_c2h/dsc_ready] [get_bd_pins xdma_0/c2h_dsc_byp_ready_0]
+ connect_bd_net -net xdma_0_h2c_dsc_byp_ready_0 [get_bd_pins gen_xdma_descriptor_h2c/dsc_ready] [get_bd_pins xdma_0/h2c_dsc_byp_ready_0]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
diff --git a/receiver/scripts/setup_action.sh b/fpga/scripts/setup_action.sh
similarity index 91%
rename from receiver/scripts/setup_action.sh
rename to fpga/scripts/setup_action.sh
index 11ce5888..8ad1ba63 100644
--- a/receiver/scripts/setup_action.sh
+++ b/fpga/scripts/setup_action.sh
@@ -26,12 +26,6 @@ clean:
echo -n ""
EOF
-cat < ${SRC_DIR}/oc-accel/snap_env.sh
-export ACTION_ROOT=$PWD/action
-export TIMING_LABLIMIT="-100"
-export OCSE_ROOT=$SRC_DIR/ocse
-EOF
-
cp ${SRC_DIR}/hdl/*.v action/hw/hdl
# Update action type and release level based on Definitions.h
diff --git a/receiver/scripts/synth_and_impl.tcl b/fpga/scripts/synth_and_impl.tcl
similarity index 97%
rename from receiver/scripts/synth_and_impl.tcl
rename to fpga/scripts/synth_and_impl.tcl
index eaa34bb6..f159d4a0 100644
--- a/receiver/scripts/synth_and_impl.tcl
+++ b/fpga/scripts/synth_and_impl.tcl
@@ -1,5 +1,4 @@
-## Copyright (2019-2022) Paul Scherrer Institute
-## SPDX-License-Identifier: CERN-OHL-S-2.0
+## Copyright (2019-2023) Paul Scherrer Institute
##
open_project $::env(VIV_PROJECT_PATH)
diff --git a/receiver/scripts/synth_hls_function.tcl b/fpga/scripts/synth_hls_function.tcl
similarity index 85%
rename from receiver/scripts/synth_hls_function.tcl
rename to fpga/scripts/synth_hls_function.tcl
index c53c2881..c940b88b 100644
--- a/receiver/scripts/synth_hls_function.tcl
+++ b/fpga/scripts/synth_hls_function.tcl
@@ -1,5 +1,4 @@
-## Copyright (2019-2022) Paul Scherrer Institute
-## SPDX-License-Identifier: CERN-OHL-S-2.0
+## Copyright (2019-2023) Paul Scherrer Institute
open_project $env(HLS_TOP_FUNCTION) -reset
diff --git a/receiver/xdc/pcie_timing.xdc b/fpga/xdc/pcie_timing.xdc
similarity index 100%
rename from receiver/xdc/pcie_timing.xdc
rename to fpga/xdc/pcie_timing.xdc
diff --git a/receiver/xdc/pcie_u55c.xdc b/fpga/xdc/pcie_u55c.xdc
similarity index 100%
rename from receiver/xdc/pcie_u55c.xdc
rename to fpga/xdc/pcie_u55c.xdc
diff --git a/frame_serialize/CBORMessages.h b/frame_serialize/CBORMessages.h
new file mode 100644
index 00000000..897aff29
--- /dev/null
+++ b/frame_serialize/CBORMessages.h
@@ -0,0 +1,156 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#ifndef JUNGFRAUJOCH_CBORMESSAGES_H
+#define JUNGFRAUJOCH_CBORMESSAGES_H
+
+#include
+#include
+#include