From c51bfcb95a4d8f8ef04510e7cab83c027e3b8df1 Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Sat, 18 Nov 2023 14:42:08 +0100 Subject: [PATCH] PCIe driver: more verbose --- fpga/pcie_driver/jfjoch_function.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/fpga/pcie_driver/jfjoch_function.c b/fpga/pcie_driver/jfjoch_function.c index f7c5a33a..39251b12 100644 --- a/fpga/pcie_driver/jfjoch_function.c +++ b/fpga/pcie_driver/jfjoch_function.c @@ -136,7 +136,7 @@ void jfjoch_get_ipv4_addr(struct jfjoch_drvdata *drvdata, u32 *addr) { u64 jfjoch_read_mac_addr(struct jfjoch_drvdata *drvdata) { struct device *const dev = &drvdata->pdev->dev; - u32 tmp, host_msg_offset, msg_len; + u32 tmp, host_msg_offset, msg_len, opcode; u32 field_type, field_len; u32 i, j; u8 output[256]; @@ -156,7 +156,7 @@ u64 jfjoch_read_mac_addr(struct jfjoch_drvdata *drvdata) { host_msg_offset = ioread32(drvdata->bar0 + CMS_OFFSET + 0x28300); dev_info(dev, "Host msg offset %x", host_msg_offset); - iowrite32(0x04000000, drvdata->bar0 + CMS_OFFSET + 0x28000 + host_msg_offset); + iowrite32(0x04 << 24, drvdata->bar0 + CMS_OFFSET + 0x28000 + host_msg_offset); iowrite32(1<<5, drvdata->bar0 + CMS_OFFSET + ADDR_CMS_CONTROL_REG); i = 0; @@ -180,16 +180,16 @@ u64 jfjoch_read_mac_addr(struct jfjoch_drvdata *drvdata) { } tmp = ioread32(drvdata->bar0 + CMS_OFFSET + 0x28000 + host_msg_offset); - dev_info(dev, "Mailbox response %x", tmp); + opcode = (tmp >> 24) & 0xFF; + msg_len = tmp & 0xFFF; - if ((tmp & 0xFF000000) != 0x04000000) { - dev_err(dev, "Opcode in return message doesn't match %x", tmp); + dev_info(dev, "Mailbox response %x opcode %x len %x", tmp, opcode, msg_len); + + if (opcode != 0x04) { + dev_err(dev, "Opcode in return message 0x%x doesn't match 0x%x", opcode, 0x04); return 0; } - msg_len = tmp & 0xFFF; - dev_info(dev, "Mailbox response length %x", msg_len); - i = 0; while (i < msg_len) { field_type = ioread8(drvdata->bar0 + CMS_OFFSET + 0x28000 + host_msg_offset + 0x4 + i); @@ -287,7 +287,7 @@ void jfjoch_clr_net_counters(struct jfjoch_drvdata *drvdata) { int jfjoch_load_calibration(struct jfjoch_drvdata *drvdata, struct DataCollectionConfig *config) { struct device *const dev = &drvdata->pdev->dev; - u32 i; + u32 i, tmp; u32 cell_count = config->nmodules * (3 + 3 * config->nstorage_cells); if (cell_count > drvdata->nbuf) { @@ -314,10 +314,12 @@ int jfjoch_load_calibration(struct jfjoch_drvdata *drvdata, struct DataCollectio i = 0; while (i < 1000) { - if (ioread32(drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL) & (1 << 1)) + tmp = ioread32(drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL); + if (tmp & (1 << 1)) break; msleep(10); i++; + dev_info(dev, "Load calibration status 0x%x", tmp); } // STOP H2C channel