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version 1.0.0-rc.24

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leonarski_f
2024-11-17 14:55:09 +01:00
parent aeeae33ad9
commit adc13ff33e
361 changed files with 12513 additions and 3314 deletions
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117
tests/FPGAFrameGeneratorTest.cpp
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@@ -1,12 +1,12 @@
// Copyright (2019-2023) Paul Scherrer Institute
#include <catch2/catch_all.hpp>
#include "../fpga/hls/hls_jfjoch.h"
#include "../fpga/hls_simulation/hls_cores.h"
TEST_CASE("FPGA_FrameGenerator_Cancel") {
STREAM_512 data_out;
std::vector<ap_uint<256>> d_hbm_p0(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256>> d_hbm_p1(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p0(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p1(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
ap_uint<1> cancel = 1;
FrameGeneratorConfig config{
.frames = 256,
@@ -21,14 +21,14 @@ TEST_CASE("FPGA_FrameGenerator_Cancel") {
TEST_CASE("FPGA_FrameGenerator_WrongDetectorType") {
STREAM_512 data_out;
std::vector<ap_uint<256>> d_hbm_p0(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256>> d_hbm_p1(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p0(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p1(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
ap_uint<1> cancel = 1;
FrameGeneratorConfig config{
.frames = 256,
.modules = 8,
.detector_type = 0,
.images_in_memory = 0
.frames = 256,
.modules = 8,
.detector_type = 0,
.images_in_memory = 0
};
REQUIRE(frame_generator(data_out, d_hbm_p0.data(), d_hbm_p1.data(), 16*1024*1024, 0, 0, cancel, config) != 0);
REQUIRE(data_out.size() == 0);
@@ -36,14 +36,14 @@ TEST_CASE("FPGA_FrameGenerator_WrongDetectorType") {
TEST_CASE("FPGA_FrameGenerator_WrongModuleCount") {
STREAM_512 data_out;
std::vector<ap_uint<256>> d_hbm_p0(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256>> d_hbm_p1(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p0(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p1(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
ap_uint<1> cancel = 1;
FrameGeneratorConfig config{
.frames = 256,
.modules = MAX_MODULES_FPGA + 1,
.detector_type = SLS_DETECTOR_TYPE_JUNGFRAU,
.images_in_memory = 0
.frames = 256,
.modules = MAX_MODULES_FPGA + 1,
.detector_type = SLS_DETECTOR_TYPE_JUNGFRAU,
.images_in_memory = 0
};
REQUIRE(frame_generator(data_out, d_hbm_p0.data(), d_hbm_p1.data(), 16*1024*1024, 0, 0, cancel, config) != 0);
REQUIRE(data_out.size() == 0);
@@ -55,14 +55,14 @@ TEST_CASE("FPGA_FrameGenerator_WrongModuleCount") {
TEST_CASE("FPGA_FrameGenerator_TooManyCells") {
STREAM_512 data_out;
std::vector<ap_uint<256>> d_hbm_p0(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256>> d_hbm_p1(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p0(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p1(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
ap_uint<1> cancel = 1;
FrameGeneratorConfig config{
.frames = 256,
.modules = 4,
.detector_type = SLS_DETECTOR_TYPE_JUNGFRAU,
.images_in_memory = 8
.frames = 256,
.modules = 4,
.detector_type = SLS_DETECTOR_TYPE_JUNGFRAU,
.images_in_memory = 8
};
REQUIRE(frame_generator(data_out, d_hbm_p0.data(), d_hbm_p1.data(), 16*1024*1024, 0, 0, cancel, config) == 3);
REQUIRE(data_out.size() == 0);
@@ -70,31 +70,80 @@ TEST_CASE("FPGA_FrameGenerator_TooManyCells") {
TEST_CASE("FPGA_FrameGenerator_Run_JF") {
STREAM_512 data_out;
std::vector<ap_uint<256>> d_hbm_p0(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256>> d_hbm_p1(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p0(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p1(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
ap_uint<1> cancel = 0;
FrameGeneratorConfig config{
.frames = 2,
.modules = 2,
.detector_type = SLS_DETECTOR_TYPE_JUNGFRAU,
.images_in_memory = 0
.frames = 2,
.modules = 2,
.detector_type = SLS_DETECTOR_TYPE_JUNGFRAU,
.images_in_memory = 0
};
REQUIRE(frame_generator(data_out, d_hbm_p0.data(), d_hbm_p1.data(), 16*1024*1024, 0, 0, cancel, config) == 0);
REQUIRE(data_out.size() == (config.frames * config.modules * 128 + 1) * 130);
}
TEST_CASE("FPGA_FrameGenerator_Run_EIGER") {
STREAM_512 data_out;
std::vector<ap_uint<256>> d_hbm_p0(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256>> d_hbm_p1(RAW_MODULE_SIZE/(256/8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p0(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p1(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
ap_uint<1> cancel = 0;
FrameGeneratorConfig config{
.frames = 2,
.modules = 2,
.detector_type = SLS_DETECTOR_TYPE_EIGER,
.images_in_memory = 0
.frames = 2,
.modules = 2,
.detector_type = SLS_DETECTOR_TYPE_EIGER,
.images_in_memory = 0,
.eiger_bit_depth = 16
};
REQUIRE(frame_generator(data_out, d_hbm_p0.data(), d_hbm_p1.data(), 16*1024*1024, 0, 0, cancel, config) == 0);
REQUIRE(data_out.size() == (config.frames * config.modules * 256) * 66 + 130); // Trailing packet is JF type!
}
TEST_CASE("FPGA_FrameGenerator_Run_EIGER_32bit") {
STREAM_512 data_out;
std::vector<ap_uint<256> > d_hbm_p0(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p1(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
ap_uint<1> cancel = 0;
FrameGeneratorConfig config{
.frames = 2,
.modules = 2,
.detector_type = SLS_DETECTOR_TYPE_EIGER,
.images_in_memory = 0,
.eiger_bit_depth = 32
};
REQUIRE(frame_generator(data_out, d_hbm_p0.data(), d_hbm_p1.data(), 16*1024*1024, 0, 0, cancel, config) == 0);
REQUIRE(data_out.size() == (config.frames * config.modules * 512) * 66 + 130); // Trailing packet is JF type!
}
TEST_CASE("FPGA_FrameGenerator_Run_EIGER_8bit") {
STREAM_512 data_out;
std::vector<ap_uint<256> > d_hbm_p0(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p1(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
ap_uint<1> cancel = 0;
FrameGeneratorConfig config{
.frames = 2,
.modules = 2,
.detector_type = SLS_DETECTOR_TYPE_EIGER,
.images_in_memory = 0,
.eiger_bit_depth = 8
};
REQUIRE(frame_generator(data_out, d_hbm_p0.data(), d_hbm_p1.data(), 16*1024*1024, 0, 0, cancel, config) == 0);
REQUIRE(data_out.size() == (config.frames * config.modules * 128) * 66 + 130); // Trailing packet is JF type!
}
TEST_CASE("FPGA_FrameGenerator_Run_EIGER_wrong_depth") {
STREAM_512 data_out;
std::vector<ap_uint<256> > d_hbm_p0(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
std::vector<ap_uint<256> > d_hbm_p1(RAW_MODULE_SIZE / (256 / 8) * 22 * 32);
ap_uint<1> cancel = 0;
FrameGeneratorConfig config{
.frames = 2,
.modules = 2,
.detector_type = SLS_DETECTOR_TYPE_EIGER,
.images_in_memory = 0,
.eiger_bit_depth = 0
};
REQUIRE(frame_generator(data_out, d_hbm_p0.data(), d_hbm_p1.data(), 16*1024*1024, 0, 0, cancel, config) != 0);
REQUIRE(data_out.size() == 0); // Trailing packet is JF type!
}