From a94bdacea92851c9ea8dee89ccd67ab8bcb4227c Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Sun, 17 Sep 2023 21:49:50 +0200 Subject: [PATCH] Revert "FPGA: use 4 HBM interfaces for load and save to HBM" This reverts commit 28a29ea3183a35d8ba0dda0628ac727f8bfe4f17. --- fpga/hls/hls_jfjoch.h | 4 ---- fpga/hls/load_from_hbm.cpp | 27 ++++++++------------------- fpga/hls/save_to_hbm.cpp | 21 ++++++--------------- fpga/scripts/jfjoch.tcl | 32 ++++++-------------------------- receiver/HLSSimulatedDevice.cpp | 8 ++------ 5 files changed, 22 insertions(+), 70 deletions(-) diff --git a/fpga/hls/hls_jfjoch.h b/fpga/hls/hls_jfjoch.h index f1cd7d04..b7c5ce23 100644 --- a/fpga/hls/hls_jfjoch.h +++ b/fpga/hls/hls_jfjoch.h @@ -147,8 +147,6 @@ void load_from_hbm(STREAM_512 &data_in, hls::stream > &m_axis_free_handles, ap_uint<256> *d_hbm_p0, ap_uint<256> *d_hbm_p1, - ap_uint<256> *d_hbm_p2, - ap_uint<256> *d_hbm_p3, ap_uint<32> hbm_size_bytes); void save_to_hbm(STREAM_512 &data_in, @@ -158,8 +156,6 @@ void save_to_hbm(STREAM_512 &data_in, hls::stream> &s_axis_free_handles, ap_uint<256> *d_hbm_p0, ap_uint<256> *d_hbm_p1, - ap_uint<256> *d_hbm_p2, - ap_uint<256> *d_hbm_p3, ap_uint<32> hbm_size_bytes) ; void mask_missing(STREAM_512 &data_in, diff --git a/fpga/hls/load_from_hbm.cpp b/fpga/hls/load_from_hbm.cpp index dab72217..7e366b1c 100644 --- a/fpga/hls/load_from_hbm.cpp +++ b/fpga/hls/load_from_hbm.cpp @@ -10,8 +10,6 @@ void load_from_hbm(STREAM_512 &data_in, hls::stream > &m_axis_free_handles, ap_uint<256> *d_hbm_p0, ap_uint<256> *d_hbm_p1, - ap_uint<256> *d_hbm_p2, - ap_uint<256> *d_hbm_p3, ap_uint<32> hbm_size_bytes) { #pragma HLS INTERFACE ap_ctrl_none port=return #pragma HLS INTERFACE register both axis port=data_in @@ -25,45 +23,36 @@ void load_from_hbm(STREAM_512 &data_in, max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8 #pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8 -#pragma HLS INTERFACE mode=m_axi port=d_hbm_p2 bundle=d_hbm_p2 depth=512 offset=off \ - max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8 -#pragma HLS INTERFACE mode=m_axi port=d_hbm_p3 bundle=d_hbm_p3 depth=512 offset=off \ - max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8 packet_512_t packet; data_in >> packet; data_out << packet; - for (ap_uint<16> i = 0; i < hbm_size_bytes * 4 / (RAW_MODULE_SIZE * sizeof(uint32_t)); i++) + for (ap_uint<16> i = 0; i < hbm_size_bytes / (RAW_MODULE_SIZE * sizeof(uint32_t) / 2); i++) m_axis_free_handles << i; ap_uint<32> offset_hbm_0 = 12 * hbm_size_bytes / 32; - ap_uint<32> offset_hbm_1 = 13 * hbm_size_bytes / 32; - ap_uint<32> offset_hbm_2 = 14 * hbm_size_bytes / 32; - ap_uint<32> offset_hbm_3 = 15 * hbm_size_bytes / 32; + ap_uint<32> offset_hbm_1 = 14 * hbm_size_bytes / 32; axis_completion cmpl; s_axis_completion >> cmpl; while (!cmpl.last) { m_axis_completion << cmpl; - size_t offset = (cmpl.handle * RAW_MODULE_SIZE * sizeof(uint16_t)) / 128; - for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 128; i++) { -#pragma HLS PIPELINE II=2 + size_t offset = ((cmpl.handle / 2) * RAW_MODULE_SIZE * sizeof(uint16_t)) / 64; + if (cmpl.handle % 2 == 1) + offset += hbm_size_bytes / 32; + for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) { +#pragma HLS PIPELINE II=1 packet_512_t packet_out; packet_out.data(255, 0) = d_hbm_p0[offset_hbm_0 + offset + i]; packet_out.data(511, 256) = d_hbm_p1[offset_hbm_1 + offset + i]; - packet_out.last = 0; + packet_out.last = (i == RAW_MODULE_SIZE * sizeof(uint16_t) / 64 - 1); packet_out.id = 0; packet_out.dest = 0; packet_out.keep = UINT64_MAX; packet_out.strb = UINT64_MAX; packet_out.user = 0; data_out << packet_out; - - packet_out.data(255, 0) = d_hbm_p2[offset_hbm_2 + offset + i]; - packet_out.data(511, 256) = d_hbm_p3[offset_hbm_3 + offset + i]; - packet_out.last = (i == RAW_MODULE_SIZE * sizeof(uint16_t) / 128 - 1); - data_out << packet_out; } m_axis_free_handles << cmpl.handle; s_axis_completion >> cmpl; diff --git a/fpga/hls/save_to_hbm.cpp b/fpga/hls/save_to_hbm.cpp index 49b5a33d..05cd0469 100644 --- a/fpga/hls/save_to_hbm.cpp +++ b/fpga/hls/save_to_hbm.cpp @@ -10,8 +10,6 @@ void save_to_hbm(STREAM_512 &data_in, hls::stream> &s_axis_free_handles, ap_uint<256> *d_hbm_p0, ap_uint<256> *d_hbm_p1, - ap_uint<256> *d_hbm_p2, - ap_uint<256> *d_hbm_p3, ap_uint<32> hbm_size_bytes) { #pragma HLS INTERFACE ap_ctrl_none port=return #pragma HLS INTERFACE register both axis port=data_in @@ -25,10 +23,6 @@ void save_to_hbm(STREAM_512 &data_in, max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 #pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 -#pragma HLS INTERFACE mode=m_axi port=d_hbm_p2 bundle=d_hbm_p2 depth=512 offset=off \ - max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 -#pragma HLS INTERFACE mode=m_axi port=d_hbm_p3 bundle=d_hbm_p3 depth=512 offset=off \ - max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 axis_completion cmpl[MAX_MODULES_FPGA*2]; @@ -47,16 +41,14 @@ void save_to_hbm(STREAM_512 &data_in, data_out << packet_in; ap_uint<32> offset_hbm_0 = 12 * hbm_size_bytes / 32; - ap_uint<32> offset_hbm_1 = 13 * hbm_size_bytes / 32; - ap_uint<32> offset_hbm_2 = 14 * hbm_size_bytes / 32; - ap_uint<32> offset_hbm_3 = 15 * hbm_size_bytes / 32; + ap_uint<32> offset_hbm_1 = 14 * hbm_size_bytes / 32; addr_in >> addr; Loop_good_packet: while (!addr.last) { // Process one UDP packet per iteration -#pragma HLS PIPELINE II=128 style=flp +#pragma HLS PIPELINE II=128 ap_uint<64> frame_number = addr.frame_number; ap_uint<5> module_number = addr.module; ap_uint<7> eth_packet = addr.eth_packet; @@ -84,15 +76,14 @@ void save_to_hbm(STREAM_512 &data_in, cmpl[id].packet_count++; } - size_t offset = (cmpl[id].handle * RAW_MODULE_SIZE * sizeof(uint16_t) + eth_packet * 8192) / 128; + size_t offset = ((cmpl[id].handle / 2) * RAW_MODULE_SIZE * sizeof(uint16_t) + eth_packet * 8192) / 64; + if (cmpl[id].handle % 2 == 1) + offset += hbm_size_bytes / 32; - for (int i = 0; i < 64; i++) { + for (int i = 0; i < 128; i++) { data_in >> packet_in; d_hbm_p0[offset_hbm_0 + offset + i] = packet_in.data(255, 0); d_hbm_p1[offset_hbm_1 + offset + i] = packet_in.data(511, 256); - data_in >> packet_in; - d_hbm_p2[offset_hbm_2 + offset + i] = packet_in.data(255, 0); - d_hbm_p3[offset_hbm_3 + offset + i] = packet_in.data(511, 256); } addr_in >> addr; diff --git a/fpga/scripts/jfjoch.tcl b/fpga/scripts/jfjoch.tcl index 5fda08ea..32e048f3 100644 --- a/fpga/scripts/jfjoch.tcl +++ b/fpga/scripts/jfjoch.tcl @@ -409,18 +409,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { # Create instance: smartconnect_2, and set properties set smartconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_2 ] - # Create instance: smartconnect_3, and set properties - set smartconnect_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_3 ] - - # Create instance: smartconnect_4, and set properties - set smartconnect_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_4 ] - - # Create instance: smartconnect_5, and set properties - set smartconnect_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_5 ] - - # Create instance: smartconnect_6, and set properties - set smartconnect_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_6 ] - # Create instance: stream_merge_0, and set properties set stream_merge_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:stream_merge:1.0 stream_merge_0 ] @@ -491,10 +479,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_intf_net -intf_net load_calibration_0_m_axi_d_hbm_p0 [get_bd_intf_pins load_calibration_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/S01_AXI] connect_bd_intf_net -intf_net load_calibration_0_m_axi_d_hbm_p1 [get_bd_intf_pins load_calibration_0/m_axi_d_hbm_p1] [get_bd_intf_pins smartconnect_2/S01_AXI] connect_bd_intf_net -intf_net load_from_hbm_0_data_out [get_bd_intf_pins axis_data_fifo_4/S_AXIS] [get_bd_intf_pins load_from_hbm_0/data_out] - connect_bd_intf_net -intf_net load_from_hbm_0_m_axi_d_hbm_p0 [get_bd_intf_pins load_from_hbm_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_3/S01_AXI] - connect_bd_intf_net -intf_net load_from_hbm_0_m_axi_d_hbm_p1 [get_bd_intf_pins load_from_hbm_0/m_axi_d_hbm_p1] [get_bd_intf_pins smartconnect_4/S01_AXI] - connect_bd_intf_net -intf_net load_from_hbm_0_m_axi_d_hbm_p2 [get_bd_intf_pins load_from_hbm_0/m_axi_d_hbm_p2] [get_bd_intf_pins smartconnect_5/S01_AXI] - connect_bd_intf_net -intf_net load_from_hbm_0_m_axi_d_hbm_p3 [get_bd_intf_pins load_from_hbm_0/m_axi_d_hbm_p3] [get_bd_intf_pins smartconnect_6/S01_AXI] + connect_bd_intf_net -intf_net load_from_hbm_0_m_axi_d_hbm_p0 [get_bd_intf_pins m_axi_d_hbm_p12] [get_bd_intf_pins load_from_hbm_0/m_axi_d_hbm_p0] + connect_bd_intf_net -intf_net load_from_hbm_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p14] [get_bd_intf_pins load_from_hbm_0/m_axi_d_hbm_p1] connect_bd_intf_net -intf_net load_from_hbm_0_m_axis_completion [get_bd_intf_pins axis_compl_fifo_1/S_AXIS] [get_bd_intf_pins load_from_hbm_0/m_axis_completion] connect_bd_intf_net -intf_net load_from_hbm_0_m_axis_free_handles [get_bd_intf_pins axis_hbm_handles_fifo/S_AXIS] [get_bd_intf_pins load_from_hbm_0/m_axis_free_handles] connect_bd_intf_net -intf_net mailbox_0_M1_AXIS [get_bd_intf_pins axis_work_request_fifo_0/S_AXIS] [get_bd_intf_pins mailbox_0/M1_AXIS] @@ -504,10 +490,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_intf_net -intf_net network_stack_udp_out [get_bd_intf_pins axis_udp_fifo_0/S_AXIS] [get_bd_intf_pins network_stack/udp_out] connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins smartconnect_0/S00_AXI] connect_bd_intf_net -intf_net save_to_hbm_0_data_out [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins save_to_hbm_0/data_out] - connect_bd_intf_net -intf_net save_to_hbm_0_m_axi_d_hbm_p0 [get_bd_intf_pins save_to_hbm_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_3/S00_AXI] - connect_bd_intf_net -intf_net save_to_hbm_0_m_axi_d_hbm_p1 [get_bd_intf_pins save_to_hbm_0/m_axi_d_hbm_p1] [get_bd_intf_pins smartconnect_4/S00_AXI] - connect_bd_intf_net -intf_net save_to_hbm_0_m_axi_d_hbm_p2 [get_bd_intf_pins save_to_hbm_0/m_axi_d_hbm_p2] [get_bd_intf_pins smartconnect_5/S00_AXI] - connect_bd_intf_net -intf_net save_to_hbm_0_m_axi_d_hbm_p3 [get_bd_intf_pins save_to_hbm_0/m_axi_d_hbm_p3] [get_bd_intf_pins smartconnect_6/S00_AXI] + connect_bd_intf_net -intf_net save_to_hbm_0_m_axi_d_hbm_p0 [get_bd_intf_pins m_axi_d_hbm_p13] [get_bd_intf_pins save_to_hbm_0/m_axi_d_hbm_p0] + connect_bd_intf_net -intf_net save_to_hbm_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p15] [get_bd_intf_pins save_to_hbm_0/m_axi_d_hbm_p1] connect_bd_intf_net -intf_net save_to_hbm_0_m_axis_completion [get_bd_intf_pins axis_compl_fifo_0/S_AXIS] [get_bd_intf_pins save_to_hbm_0/m_axis_completion] connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins action_config_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI] connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins mailbox_0/S0_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI] @@ -516,10 +500,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins frame_generator_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M04_AXI] connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/M00_AXI] connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p2] [get_bd_intf_pins smartconnect_2/M00_AXI] - connect_bd_intf_net -intf_net smartconnect_3_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p12] [get_bd_intf_pins smartconnect_3/M00_AXI] - connect_bd_intf_net -intf_net smartconnect_4_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p13] [get_bd_intf_pins smartconnect_4/M00_AXI] - connect_bd_intf_net -intf_net smartconnect_5_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p14] [get_bd_intf_pins smartconnect_5/M00_AXI] - connect_bd_intf_net -intf_net smartconnect_6_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p15] [get_bd_intf_pins smartconnect_6/M00_AXI] connect_bd_intf_net -intf_net stream_merge_0_output_r [get_bd_intf_pins axis_eth_in_fifo/S_AXIS] [get_bd_intf_pins stream_merge_0/output_r] connect_bd_intf_net -intf_net timer_hbm_data_out [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins timer_hbm/data_out] connect_bd_intf_net -intf_net timer_host_data_out [get_bd_intf_pins axis_data_fifo_6/S_AXIS] [get_bd_intf_pins timer_host/data_out] @@ -536,7 +516,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net action_config_0_nmodules [get_bd_pins action_config_0/nmodules] [get_bd_pins data_collection_fsm_0/nmodules] connect_bd_net -net action_config_0_nstorage_cells [get_bd_pins action_config_0/nstorage_cells] [get_bd_pins data_collection_fsm_0/nstorage_cells] connect_bd_net -net action_config_0_one_over_energy [get_bd_pins action_config_0/one_over_energy] [get_bd_pins data_collection_fsm_0/one_over_energy] - connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_hbm_handles_fifo/s_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins load_from_hbm_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins smartconnect_3/aclk] [get_bd_pins smartconnect_4/aclk] [get_bd_pins smartconnect_5/aclk] [get_bd_pins smartconnect_6/aclk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk] + connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_hbm_handles_fifo/s_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins load_from_hbm_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk] connect_bd_net -net axis_addr_fifo_0_almost_empty [get_bd_pins action_config_0/calib_addr_fifo_empty] [get_bd_pins axis_addr_fifo_0/almost_empty] connect_bd_net -net axis_addr_fifo_0_almost_full [get_bd_pins action_config_0/calib_addr_fifo_full] [get_bd_pins axis_addr_fifo_0/almost_full] connect_bd_net -net axis_addr_fifo_4_almost_empty [get_bd_pins action_config_0/last_addr_fifo_empty] [get_bd_pins axis_addr_fifo_1/almost_empty] @@ -583,7 +563,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net network_stack_packets_sls_ap_vld [get_bd_pins action_config_0/packets_sls_valid] [get_bd_pins network_stack/packets_sls_ap_vld] connect_bd_net -net network_stack_packets_udp [get_bd_pins action_config_0/packets_udp] [get_bd_pins network_stack/packets_udp] connect_bd_net -net network_stack_packets_udp_ap_vld [get_bd_pins action_config_0/packets_udp_valid] [get_bd_pins network_stack/packets_udp_ap_vld] - connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_0/s_axis_aresetn] [get_bd_pins axis_compl_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_eth_in_fifo/s_axis_aresetn] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aresetn] [get_bd_pins axis_hbm_handles_fifo/s_axis_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn] [get_bd_pins smartconnect_3/aresetn] [get_bd_pins smartconnect_4/aresetn] [get_bd_pins smartconnect_5/aresetn] [get_bd_pins smartconnect_6/aresetn] + connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_0/s_axis_aresetn] [get_bd_pins axis_compl_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_eth_in_fifo/s_axis_aresetn] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aresetn] [get_bd_pins axis_hbm_handles_fifo/s_axis_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn] connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins frame_generator_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins load_from_hbm_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins save_to_hbm_0/ap_rst_n] [get_bd_pins stream_merge_0/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n] connect_bd_net -net timer_hbm_counter [get_bd_pins action_config_0/stalls_hbm] [get_bd_pins timer_hbm/counter] connect_bd_net -net timer_hbm_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm/counter_ap_vld] diff --git a/receiver/HLSSimulatedDevice.cpp b/receiver/HLSSimulatedDevice.cpp index d1aa75c8..989ee4e6 100644 --- a/receiver/HLSSimulatedDevice.cpp +++ b/receiver/HLSSimulatedDevice.cpp @@ -311,12 +311,8 @@ void HLSSimulatedDevice::HLSMainThread() { hls::stream> handles; // 3. Cache images in HBM - hls_cores.emplace_back([&] { save_to_hbm(converted_0, converted_1, addr2, compl0, handles, - hbm.data(), hbm.data(), hbm.data(), hbm.data(), - hbm_if_size);}); - hls_cores.emplace_back([&] { load_from_hbm(converted_1, converted_2, compl0, compl1, handles, - hbm.data(), hbm.data(), hbm.data(), hbm.data(), - hbm_if_size);}); + hls_cores.emplace_back([&] { save_to_hbm(converted_0, converted_1, addr2, compl0, handles, hbm.data(), hbm.data(), hbm_if_size);}); + hls_cores.emplace_back([&] { load_from_hbm(converted_1, converted_2, compl0, compl1, handles, hbm.data(), hbm.data(), hbm_if_size);}); // 4. Mask missing pixels hls_cores.emplace_back([&] { mask_missing(converted_2, converted_3, compl1, compl2);});