From a43fa2a296eaaba8bda487d8d2665ac2c07bd4a5 Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Mon, 26 Jun 2023 09:27:47 +0200 Subject: [PATCH] ProtoBuf: Don't use maps, as these don't preserve order of elements --- grpc/jfjoch.proto | 16 +++- python/jfjoch_pb2.py | 142 ++++++++++++++-------------- receiver/FPGAAcquisitionDevice.cpp | 33 ++++--- receiver/JFJochReceiver.cpp | 16 ++-- receiver/jfjoch_pcie_status.cpp | 18 ++-- tests/JFJochFullIntegrationTest.cpp | 22 +++-- 6 files changed, 136 insertions(+), 111 deletions(-) diff --git a/grpc/jfjoch.proto b/grpc/jfjoch.proto index 6e5e8cd5..6ace8760 100644 --- a/grpc/jfjoch.proto +++ b/grpc/jfjoch.proto @@ -25,7 +25,7 @@ enum DetectorMode { PEDESTAL_G2 = 4; }; -enum FPGAFIFOStatus { +enum FPGAFIFOStatusEnum { EMPTY = 0; FULL = 1; PARTIAL = 2; @@ -288,8 +288,13 @@ message PlotRequest { uint64 binning = 2; } +message RadialIntegrationProfile { + string title = 1; + Plot plot = 2; +} + message RadialIntegrationProfiles { - map plots = 1; + repeated RadialIntegrationProfile profiles = 1; } // Writer @@ -351,6 +356,11 @@ message DetectorStatus { string server_version = 3; } +message FPGAFIFOStatus { + string name = 1; + FPGAFIFOStatusEnum value = 2; +} + message FPGAStatus { uint64 packets_ether = 2; uint64 packets_udp = 3; @@ -363,7 +373,7 @@ message FPGAStatus { uint64 stalls_host = 10; bool ethernet_rx_aligned = 11; uint32 full_status_register = 13; - map fifo_status = 14; + repeated FPGAFIFOStatus fifo_status = 14; uint64 max_modules = 15; uint32 git_sha1 = 16; uint32 mailbox_err_reg = 17; diff --git a/python/jfjoch_pb2.py b/python/jfjoch_pb2.py index 1b825c58..6ed73a93 100644 --- a/python/jfjoch_pb2.py +++ b/python/jfjoch_pb2.py @@ -13,29 +13,25 @@ _sym_db = _symbol_database.Default() -DESCRIPTOR = _descriptor_pool.Default().AddSerializedFile(b'\n\x0cjfjoch.proto\x12\x0eJFJochProtoBuf\"\x07\n\x05\x45mpty\"W\n\x08UnitCell\x12\t\n\x01\x61\x18\x01 \x01(\x02\x12\t\n\x01\x62\x18\x02 \x01(\x02\x12\t\n\x01\x63\x18\x03 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_GRPC_JFJOCHRECEIVER._serialized_start=9483 + _GRPC_JFJOCHRECEIVER._serialized_end=10250 + _GRPC_JFJOCHWRITER._serialized_start=10253 + _GRPC_JFJOCHWRITER._serialized_end=10455 + _GRPC_JFJOCHDETECTOR._serialized_start=10458 + _GRPC_JFJOCHDETECTOR._serialized_end=10844 + _GRPC_JFJOCHBROKER._serialized_start=10847 + _GRPC_JFJOCHBROKER._serialized_end=12536 # @@protoc_insertion_point(module_scope) diff --git a/receiver/FPGAAcquisitionDevice.cpp b/receiver/FPGAAcquisitionDevice.cpp index b05abb72..eac7e96f 100644 --- a/receiver/FPGAAcquisitionDevice.cpp +++ b/receiver/FPGAAcquisitionDevice.cpp @@ -156,12 +156,19 @@ ActionConfig FPGAAcquisitionDevice::ReadActionRegister() { return cfg; } -inline JFJochProtoBuf::FPGAFIFOStatus FIFO_check(uint32_t fifo_register, uint16_t pos_empty, uint16_t pos_full) { +inline void FIFO_check(JFJochProtoBuf::FPGAStatus &fpga_status, + const std::string &name, + uint32_t fifo_register, + uint16_t pos_empty, + uint16_t pos_full) { + auto fifo_status = fpga_status.add_fifo_status(); + fifo_status->set_name(name); + if (std::bitset<32>(fifo_register).test(pos_empty)) - return JFJochProtoBuf::FPGAFIFOStatus::EMPTY; + fifo_status->set_value(JFJochProtoBuf::FPGAFIFOStatusEnum::EMPTY); if (std::bitset<32>(fifo_register).test(pos_full)) - return JFJochProtoBuf::FPGAFIFOStatus::FULL; - return JFJochProtoBuf::FPGAFIFOStatus::PARTIAL; + fifo_status->set_value(JFJochProtoBuf::FPGAFIFOStatusEnum::FULL); + fifo_status->set_value(JFJochProtoBuf::FPGAFIFOStatusEnum::PARTIAL); } JFJochProtoBuf::FPGAStatus FPGAAcquisitionDevice::GetStatus() const { @@ -182,15 +189,15 @@ JFJochProtoBuf::FPGAStatus FPGAAcquisitionDevice::GetStatus() const { ret.set_max_modules(status.max_modules); ret.set_git_sha1(status.git_sha1); - (*ret.mutable_fifo_status())["Conversion input (data)"] = FIFO_check(status.fifo_status, 0, 1); - (*ret.mutable_fifo_status())["Conversion input (cmd)"] = FIFO_check(status.fifo_status, 2, 3); - (*ret.mutable_fifo_status())["UDP"] = FIFO_check(status.fifo_status, 6, 7); - (*ret.mutable_fifo_status())["Work Request"] = FIFO_check(status.fifo_status, 12, 13); - (*ret.mutable_fifo_status())["Work Completion"] = FIFO_check(status.fifo_status, 14, 15); - (*ret.mutable_fifo_status())["Host mem (data)"] = FIFO_check(status.fifo_status, 8, 9); - (*ret.mutable_fifo_status())["Host mem (cmd)"] = FIFO_check(status.fifo_status, 10, 11); - (*ret.mutable_fifo_status())["Data FIFO #8"] = FIFO_check(status.fifo_status, 16, 17); - (*ret.mutable_fifo_status())["Addr FIFO #3"] = FIFO_check(status.fifo_status, 18, 19); + FIFO_check(ret, "Conversion input (data)", status.fifo_status, 0, 1); + FIFO_check(ret, "Conversion input (cmd)", status.fifo_status, 2, 3); + FIFO_check(ret, "UDP", status.fifo_status, 6, 7); + FIFO_check(ret, "Work Request", status.fifo_status, 12, 13); + FIFO_check(ret, "Work Completion", status.fifo_status, 14, 15); + FIFO_check(ret, "Host mem (data)", status.fifo_status, 8, 9); + FIFO_check(ret, "Host mem (cmd)", status.fifo_status, 10, 11); + FIFO_check(ret, "Data FIFO #8", status.fifo_status, 16, 17); + FIFO_check(ret, "Addr FIFO #3", status.fifo_status, 18, 19); ret.set_fpga_idle(HW_IsIdle()); diff --git a/receiver/JFJochReceiver.cpp b/receiver/JFJochReceiver.cpp index f9a53769..bda0b76b 100644 --- a/receiver/JFJochReceiver.cpp +++ b/receiver/JFJochReceiver.cpp @@ -703,13 +703,17 @@ JFJochProtoBuf::Plot JFJochReceiver::GetPlots(const JFJochProtoBuf::PlotRequest JFJochProtoBuf::RadialIntegrationProfiles JFJochReceiver::GetRadialIntegrationProfiles() { JFJochProtoBuf::RadialIntegrationProfiles ret; - auto &map = *ret.mutable_plots(); + if (rad_int_profile) { + auto p = ret.add_profiles(); + p->set_title("dataset"); + rad_int_profile->GetPlot(*p->mutable_plot()); + } - if (rad_int_profile) - rad_int_profile->GetPlot(map["dataset"]); - - for (int i = 0; i < rad_int_profile_per_file.size(); i++) - rad_int_profile_per_file[i]->GetPlot(map["file" + std::to_string(i)]); + for (int i = 0; i < rad_int_profile_per_file.size(); i++) { + auto p = ret.add_profiles(); + p->set_title("file" + std::to_string(i)); + rad_int_profile_per_file[i]->GetPlot(*p->mutable_plot()); + } return ret; } diff --git a/receiver/jfjoch_pcie_status.cpp b/receiver/jfjoch_pcie_status.cpp index aa99937d..0973b57c 100644 --- a/receiver/jfjoch_pcie_status.cpp +++ b/receiver/jfjoch_pcie_status.cpp @@ -51,19 +51,21 @@ int main(int argc, char **argv) { std::cout << "Frames int. pkt. gen. " << std::dec << cfg.nframes << std::endl; std::cout << std::endl; std::cout << "FPGA FIFO status: " << std::endl; - for (const auto &[x,y]: status.fifo_status()) { - std::string s = x; + for (const auto &i: status.fifo_status()) { + std::string s = i.name(); s.resize(28, ' '); - switch (y) { - case JFJochProtoBuf::FPGAFIFOStatus::PARTIAL: - s += "Partial"; - break; - case JFJochProtoBuf::FPGAFIFOStatus::EMPTY: + switch (i.value()) { + case JFJochProtoBuf::FPGAFIFOStatusEnum::EMPTY: s += "Empty"; break; - case JFJochProtoBuf::FPGAFIFOStatus::FULL: + case JFJochProtoBuf::FPGAFIFOStatusEnum::FULL: s += "Full"; break; + case JFJochProtoBuf::FPGAFIFOStatusEnum::PARTIAL: + s += "Partial"; + break; + default: + break; } std::cout << s << std::endl; } diff --git a/tests/JFJochFullIntegrationTest.cpp b/tests/JFJochFullIntegrationTest.cpp index d84ba047..950658a1 100644 --- a/tests/JFJochFullIntegrationTest.cpp +++ b/tests/JFJochFullIntegrationTest.cpp @@ -1493,14 +1493,20 @@ TEST_CASE("JFJochIntegrationTest_ZMQ_lysozyme_rad_int", "[JFJochReceiver]") { logger.Info("Stopped measurement"); auto rad_int = state_machine.GetRadialIntegrationProfiles(); - REQUIRE(rad_int.plots_size() == 4+1); - auto &plot_map = rad_int.plots(); - REQUIRE(plot_map.at("file0").x_size() == 3); - REQUIRE(plot_map.at("file0").y_size() == 3); - REQUIRE(plot_map.at("file3").x_size() == 3); - REQUIRE(plot_map.at("file3").y_size() == 3); - REQUIRE(plot_map.at("file3").x(0) == Approx(1.0)); - REQUIRE(plot_map.at("dataset").x_size() == 3); + REQUIRE(rad_int.profiles_size() == 4+1); + auto &plot_map = rad_int.profiles(); + + CHECK(plot_map[1].title() == "file0"); + CHECK(plot_map[1].plot().x_size() == 3); + CHECK(plot_map[1].plot().y_size() == 3); + + CHECK(plot_map[4].title() == "file3"); + REQUIRE(plot_map[4].plot().x_size() == 3); + CHECK(plot_map[4].plot().x(0) == Approx(1.0)); + CHECK(plot_map[4].plot().y_size() == 3); + + CHECK(plot_map[0].title() == "dataset"); + CHECK(plot_map[0].plot().x_size() == 3); fpga_receiver_server->Shutdown(); writer_server->Shutdown();