version 1.0.0-rc.15

tests/FPGAIntegrationTest.cpp

@@ -10,6 +10,7 @@
 using namespace std::literals::chrono_literals;
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
     const uint16_t nmodules = 4;
 
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -42,6 +43,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_custom_frame", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 32;
     const size_t nframes = 2;
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -82,6 +85,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_custom_frame", "[FPGA][Ful
 }
 
 TEST_CASE("HLS_C_Simulation_check_raw", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
     std::vector<uint16_t> raw_frames(RAW_MODULE_SIZE);
 
     LoadBinaryFile("../../tests/test_data/mod5_raw0.bin", raw_frames.data(), RAW_MODULE_SIZE);
@@ -116,6 +120,7 @@ TEST_CASE("HLS_C_Simulation_check_raw", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_cancel", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
 
     const uint16_t nmodules = 4;
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -140,6 +145,8 @@ TEST_CASE("HLS_C_Simulation_check_cancel", "[FPGA][Full]") {
 
 
 TEST_CASE("HLS_C_Simulation_check_cancel_conversion", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 4;
     DiffractionExperiment x((DetectorGeometry(nmodules)));
 
@@ -161,6 +168,8 @@ TEST_CASE("HLS_C_Simulation_check_cancel_conversion", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_delay", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> raw_frames(RAW_MODULE_SIZE*20);
 
     const uint16_t nmodules = 4;
@@ -203,6 +212,8 @@ TEST_CASE("HLS_C_Simulation_check_delay", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_lost_frame_raw", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> raw_frames(RAW_MODULE_SIZE*20);
 
     const uint16_t nmodules = 4;
@@ -232,6 +243,8 @@ TEST_CASE("HLS_C_Simulation_check_lost_frame_raw", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_lost_frame_conversion", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> raw_frames(RAW_MODULE_SIZE*20);
 
     const uint16_t nmodules = 4;
@@ -261,6 +274,8 @@ TEST_CASE("HLS_C_Simulation_check_lost_frame_conversion", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_single_packet", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> raw_frames(RAW_MODULE_SIZE*20);
 
     const uint16_t nmodules = 4;
@@ -323,7 +338,7 @@ TEST_CASE("HLS_C_Simulation_check_single_packet", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_convert_full_range", "[FPGA][Full]") {
-    Logger logger("HLS_C_Simulation_check_convert_full_range");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
     std::vector<double> gain(3 * RAW_MODULE_SIZE);
 
@@ -371,7 +386,8 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_convert_full_range_HG0", "[FPGA][Full]") {
-    Logger logger("HLS_C_Simulation_check_convert_full_range_HG0");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
     std::vector<double> gain(3 * RAW_MODULE_SIZE);
 
@@ -453,7 +469,8 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_HG0", "[FPGA][Full]") {
 
 
 TEST_CASE("HLS_C_Simulation_check_convert_full_range_fixedG1", "[FPGA][Full]") {
-    Logger logger("HLS_C_Simulation_check_convert_full_range_fixedG1");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
     std::vector<double> gain(3 * RAW_MODULE_SIZE);
 
@@ -502,7 +519,8 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_fixedG1", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_convert_full_range_I32", "[FPGA][Full]") {
-    Logger logger("HLS_C_Simulation_check_convert_full_range_I32");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
     std::vector<double> gain(3 * RAW_MODULE_SIZE);
 
@@ -552,7 +570,8 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_I32", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_convert_full_range_sum4", "[FPGA][Full]") {
-    Logger logger("HLS_C_Simulation_check_convert_full_range_sum4");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
     std::vector<double> gain(3 * RAW_MODULE_SIZE);
 
@@ -606,7 +625,8 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_sum4", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_convert_full_range_U16", "[FPGA][Full]") {
-    Logger logger("HLS_C_Simulation_check_convert_full_range_U16");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
     std::vector<double> gain(3 * RAW_MODULE_SIZE);
 
@@ -662,7 +682,8 @@ TEST_CASE("HLS_C_Simulation_check_poisson_full_range", "[FPGA][Full]") {
     // So hls::sqrt is actually implemented as round(sqrt())
     // This can be only handled by HLS test bench
 
-    Logger logger("HLS_C_Simulation_check_poisson_full_range");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
 
     for (int i = 0; i < RAW_MODULE_SIZE; i++) {
@@ -708,7 +729,8 @@ TEST_CASE("HLS_C_Simulation_check_poisson_full_range", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_threshold_full_range", "[FPGA][Full]") {
-    Logger logger("HLS_C_Simulation_check_threshold_full_range");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
 
     for (int i = 0; i < RAW_MODULE_SIZE; i++) {
@@ -756,7 +778,8 @@ TEST_CASE("HLS_C_Simulation_check_threshold_full_range", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_convert_full_range_poisson", "[FPGA][Full]") {
-    Logger logger("HLS_C_Simulation_check_convert_full_range_poisson");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
     std::vector<double> gain(3 * RAW_MODULE_SIZE);
 
@@ -807,7 +830,8 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_poisson", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_no_conversion_U16", "[FPGA][Full]") {
-    Logger logger("HLS_C_Simulation_no_conversion_U16");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
 
     for (int i = 0; i < RAW_MODULE_SIZE; i++)
@@ -841,7 +865,8 @@ TEST_CASE("HLS_C_Simulation_no_conversion_U16", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_no_conversion_U32", "[FPGA][Full]") {
-    Logger logger("HLS_C_Simulation_no_conversion_U32");
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> data(RAW_MODULE_SIZE);
 
     for (int i = 0; i < RAW_MODULE_SIZE; i++)
@@ -916,6 +941,8 @@ TEST_CASE("HLS_C_Simulation_no_conversion_I32", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_convert_full_range", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     double energy = 6.0;
     const uint16_t nmodules = 1;
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -970,6 +997,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_convert_full_range", "[FPG
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_convert_full_range_adu_histo", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     double energy = 6.0;
     const uint16_t nmodules = 4;
     DiffractionExperiment x((DetectorGeometry(nmodules, 2, 8, 36, true)));
@@ -1027,6 +1056,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_convert_full_range_adu_his
 }
 
 TEST_CASE("HLS_C_Simulation_check_2_trigger_convert", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<float> pedestal_g0(RAW_MODULE_SIZE), pedestal_g1(RAW_MODULE_SIZE), pedestal_g2(RAW_MODULE_SIZE);
 
     LoadBinaryFile("../../tests/test_data/mod5_pedeG0.bin", pedestal_g0.data(), RAW_MODULE_SIZE);
@@ -1094,6 +1125,8 @@ TEST_CASE("HLS_C_Simulation_check_2_trigger_convert", "[FPGA][Full]") {
 
 
 TEST_CASE("HLS_C_Simulation_check_detect_last_frame", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 4;
     DiffractionExperiment x((DetectorGeometry(nmodules)));
 
@@ -1115,6 +1148,8 @@ TEST_CASE("HLS_C_Simulation_check_detect_last_frame", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_wrong_packet_size", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 1;
     DiffractionExperiment x((DetectorGeometry(nmodules)));
 
@@ -1157,6 +1192,8 @@ TEST_CASE("HLS_C_Simulation_check_wrong_packet_size", "[FPGA][Full]") {
 
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_15_storage_cell_convert_G0", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 2;
     const uint16_t ntrigger = 2;
     const uint16_t nstoragecells = 15;
@@ -1206,6 +1243,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_15_storage_cell_convert_G0
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_8_storage_cell_convert_G0", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
     const uint16_t nmodules = 2;
     const uint16_t ntrigger = 2;
     const uint16_t nstoragecells = 8;
@@ -1256,6 +1294,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_8_storage_cell_convert_G0"
 
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_16_storage_cell_convert_G0", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
     const uint16_t nmodules = 2;
     const uint16_t ntrigger = 4;
     const uint16_t nstoragecells = 16;
@@ -1303,6 +1342,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_16_storage_cell_convert_G0
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_storage_cell_convert_G1", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 2;
     DiffractionExperiment x((DetectorGeometry(nmodules)));
 
@@ -1348,6 +1389,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_storage_cell_convert_G1",
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_integration", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 4;
 
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -1411,6 +1454,8 @@ bool spot_finder_output_contains(const SpotFindingResult& output, uint32_t numbe
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_count_threshold", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 4;
 
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -1461,6 +1506,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_count_threshol
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_mask", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 4;
 
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -1519,6 +1566,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_mask", "[FPGA]
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_min_pix_per_spot", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 4;
 
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -1579,6 +1628,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_min_pix_per_sp
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_d_min_max", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 4;
 
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -1633,6 +1684,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_d_min_max", "[
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_snr_threshold", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 4;
 
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -1690,6 +1743,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_snr_threshold"
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_32bit", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 1;
     const size_t nframes = 2;
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -1737,6 +1792,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_32bit", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_summation", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 1;
     const size_t nframes = 16;
     const size_t nsummation = 16;
@@ -1784,6 +1841,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_summation", "[FPGA][Full]"
 }
 
 TEST_CASE("HLS_C_Simulation_count_sat_and_err_pixels", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 3;
 
     DiffractionExperiment x((DetectorGeometry(nmodules)));
@@ -1816,6 +1875,7 @@ TEST_CASE("HLS_C_Simulation_count_sat_and_err_pixels", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_bunchid", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
 
     const uint64_t bunchid = 0xAAAAAAAA87345600;
     const uint16_t nmodules = 4;
@@ -1836,6 +1896,8 @@ TEST_CASE("HLS_C_Simulation_check_bunchid", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_check_raw_eiger", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> raw_frame(RAW_MODULE_SIZE);
     std::vector<uint16_t> raw_frame_eiger(RAW_MODULE_SIZE);
 
@@ -1881,6 +1943,8 @@ TEST_CASE("HLS_C_Simulation_check_raw_eiger", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_eiger", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     std::vector<uint16_t> raw_frame(RAW_MODULE_SIZE), raw_frame_eiger(RAW_MODULE_SIZE);
     std::mt19937 g1(1387);
     std::uniform_int_distribution<uint16_t> dist(0, 65535);
@@ -1918,6 +1982,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_eiger", "[FPGA][Full]") {
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_roi_calc", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 4;
     const size_t nimages = 4;
 
@@ -1984,6 +2050,8 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_roi_calc", "[FPGA][Full]")
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_4_images", "[FPGA][Full]") {
+    Logger logger(Catch::getResultCapture().getCurrentTestName());
+
     const uint16_t nmodules = 4;
     const uint16_t nimages = 4;
     DiffractionExperiment x((DetectorGeometry(nmodules)));