From 929f6c654463413b9d2cfb131ecb77518556e673 Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Sat, 9 Sep 2023 20:30:53 +0200 Subject: [PATCH] FPGA: Handle HBM offsets internally in Jungfraujoch logic --- fpga/README.md | 96 +++++++++++----------- fpga/hdl/action_config.v | 23 +++++- fpga/hls/data_collection_fsm.cpp | 5 +- fpga/hls/hls_jfjoch.h | 7 +- fpga/hls/jf_conversion.cpp | 85 +++++++++++-------- fpga/hls/save_to_hbm.cpp | 36 ++++---- fpga/pcie_driver/ActionConfig.h | 2 +- fpga/scripts/bd_pcie.tcl | 4 - fpga/scripts/jfjoch.tcl | 137 +------------------------------ receiver/HLSSimulatedDevice.cpp | 38 ++++----- tests/FPGAIntegrationTest.cpp | 29 ++++--- 11 files changed, 182 insertions(+), 280 deletions(-) diff --git a/fpga/README.md b/fpga/README.md index 30554051..ac7593e9 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -54,53 +54,55 @@ To test that FPGA board is working properly without access to a JUNGFRAU detecto ## FPGA reference FPGA setup can be done via 32-bit registers: -| Address | Bits | Meaning | Mode | Notes | -|-------------------|------|------------------------------------------------------------------------------------------------------|:-----|-----------------------------------| -| 0x00000 - 0x0FFFF | | Reserved for internal memory of MicroBlaze | | | -| 0x10000 | 32 | Action Control Register | | | -| | | Bit 0 - Action start | R/W | | -| | | Bit 1 - Action idle | R | | -| | | Bit 2 - Action cancel | R/W | cleared on reset or action start | -| | | Bit 3 - Clear network counters | R/W | cleared on reset or action start | -| | | Bit 4 - Host writer idle | R | cleared on reset | -| | | Bit 7 - Design number | R | 0 = PCIe #0, 1 = PCIe #1 | -| | | Bit 16 - AXI Mailbox interrupt 0 | R | | -| | | Bit 17 - AXI Mailbox interrupt 1 | R | | -| | | Bits 24-27 - Various errors in host memory writer | R | cleared on reset or action start | -| 0x10004 | 32 | Reserved | - | | -| 0x1000C | 32 | Action GIT SHA1 | R | | -| 0x10010 | 32 | Action Type | R | | -| 0x10014 | 32 | Action Release Level | R | | -| 0x10020 | 32 | Max. number supported detector modules | R | constant | -| 0x10024 | 32 | Number of modules in internal packet generator memory | R | constant | -| 0x10028 | 64 | Pipeline stalls before writing to host memory | R | reset on action start | -| 0x10030 | 64 | Pipeline stalls before accessing HBM | R | reset on action start | -| 0x10038 | 32 | FIFO status (see action_config.v for details) | R/W | | -| 0x1003C | 32 | Reserved | - | | -| 0x10040 | 64 | Packets processed by the action | R/W | cleared on reset or action start | -| 0x10048 | 64 | Valid ethernet packets | R/W | cleared on reset | -| 0x10050 | 64 | Valid ICMP packets | R/W | cleared on reset | -| 0x10058 | 64 | Valid UDP packets | R/W | cleared on reset | -| 0x10060 | 64 | MAC address of FPGA card | R/W | network byte order | -| 0x10068 | 32 | IPv4 address of FPGA card | R/W | network byte order | -| 0x1006C | 32 | Number of detector modules | R/W | | -| 0x10070 | 32 | Data collection mode | R/W | | -| | | Bit 0 - Conversion to photons | | | -| | | Bit 1 - Use internal packet generator | | | -| | | Bit 2 - Nonblocking operation (host writer will ignore frames if there is no available work request) | | | -| | | Bit 16:31 - Data collection ID (carried with completions) | | | -| 0x10074 | 32 | One over energy in keV (in fixed-point:12 int. + 24 frac. bit format) | R/W | | -| 0x10078 | 32 | Number of frames to be generated by internal packet generator | R/W | | -| 0x1007C | 32 | Number of storage cells | R/W | | -| | | | | | -| 0x20000 - 0x2FFFF | | CMAC 100G | | See Xilinx PG203 for register map | -| 0x30000 - 0x3FFFF | | AXI Mailbox for Work Request / Work Completion | | See Xilinx PG114 for register map | -| 0x40000 - 0x4FFFF | | QuadSPI flash | | See Xilinx PG153 for register map | -| 0x60000 - 0x60FFF | 64 | Input calibration memory addresses block RAM | | | -| 0x70000 - 0x7FFFF | | AXI Firewall | | See Xilinx PG293 for register map | -| 0x80000 - 0x8FFFF | | Interrupt controller | | See Xilinx PG099 for register map | -| 0x70000 - 0x7FFFF | | PCIe DMA control | | See Xilinx PG195 for register map | -| 0xC0000 - 0xFFFFF | | Xilinx Card Management Solution Subsystem management subsystem | | See Xilinx PG348 for register map | +| Address | Bits | Meaning | Mode | Notes | +|---------------------|------|------------------------------------------------------------------------------------------------------|:-----|----------------------------------------------| +| 0x00000 - 0x0FFFF | | Reserved (in case using MicroBlaze in the future, this has to reserved for internal memory) | | | +| 0x010000 | 32 | Action Control Register | | | +| | | Bit 0 - Action start | R/W | | +| | | Bit 1 - Action idle | R | | +| | | Bit 2 - Action cancel | R/W | cleared on reset or action start | +| | | Bit 3 - Clear network counters | R/W | cleared on reset or action start | +| | | Bit 4 - Host writer idle | R | cleared on reset | +| | | Bit 7 - Design number | R | 0 = PCIe #0, 1 = PCIe #1 | +| | | Bit 16 - AXI Mailbox interrupt 0 | R | | +| | | Bit 17 - AXI Mailbox interrupt 1 | R | | +| | | Bits 24-27 - Various errors in host memory writer | R | cleared on reset or action start | +| 0x010004 | 32 | Reserved | - | | +| 0x01000C | 32 | Action GIT SHA1 | R | | +| 0x010010 | 32 | Action Type | R | | +| 0x010014 | 32 | Action Release Level | R | | +| 0x010020 | 32 | Max. number supported detector modules | R | constant | +| 0x010024 | 32 | Number of modules in internal packet generator memory | R | constant | +| 0x010028 | 64 | Pipeline stalls before writing to host memory | R | reset on action start | +| 0x010030 | 64 | Pipeline stalls before accessing HBM | R | reset on action start | +| 0x010038 | 32 | FIFO status (see action_config.v for details) | R | | +| 0x01003C | 32 | Size of single HBM channel in bytes (default value for the particular card) | R/W | should not be altered for standard operation | +| 0x010040 | 64 | Packets processed by the action | R | cleared on reset or action start | +| 0x010048 | 64 | Valid ethernet packets | R | cleared on reset | +| 0x010050 | 64 | Valid ICMP packets | R | cleared on reset | +| 0x010058 | 64 | Valid UDP packets | R | cleared on reset | +| 0x010060 | 64 | MAC address of FPGA card | R/W | network byte order | +| 0x010068 | 32 | IPv4 address of FPGA card | R/W | network byte order | +| 0x01006C | 32 | Number of detector modules | R/W | | +| 0x010070 | 32 | Data collection mode | R/W | | +| | | Bit 0 - Conversion to photons | | | +| | | Bit 1 - Use internal packet generator | | | +| | | Bit 2 - Nonblocking operation (host writer will ignore frames if there is no available work request) | | | +| | | Bit 16:31 - Data collection ID (carried with completions) | | | +| 0x010074 | 32 | One over energy in keV (in fixed-point:12 int. + 24 frac. bit format) | R/W | | +| 0x010078 | 32 | Number of frames to be generated by internal packet generator | R/W | | +| 0x01007C | 32 | Number of storage cells | R/W | | +| | | | | | +| 0x020000 - 0x02FFFF | | CMAC 100G | | See Xilinx PG203 for register map | +| 0x030000 - 0x03FFFF | | AXI Mailbox for Work Request / Work Completion | | See Xilinx PG114 for register map | +| 0x040000 - 0x04FFFF | | QuadSPI flash | | See Xilinx PG153 for register map | +| 0x060000 - 0x060FFF | 64 | Input calibration memory addresses block RAM | | | +| 0x070000 - 0x07FFFF | | AXI Firewall | | See Xilinx PG293 for register map | +| 0x090000 - 0x09FFFF | | PCIe DMA control | | See Xilinx PG195 for register map | +| 0x0A0000 - 0x0AFFFF | | Transfer between UltraRAM buffer <-> HBM (HLS registers) | | | +| 0x0C0000 - 0x0FFFFF | | Xilinx Card Management Solution Subsystem management subsystem | | See Xilinx PG348 for register map | +| 0x100000 - 0x1FFFFF | 16 | Internal packet generator frame | | | +| 0x200000 - 0x2FFFFF | | UltraRAM buffer for transfers to/from HBM | | | ### AXI Mailbox diff --git a/fpga/hdl/action_config.v b/fpga/hdl/action_config.v index 527349bb..f8ad79cb 100644 --- a/fpga/hdl/action_config.v +++ b/fpga/hdl/action_config.v @@ -5,9 +5,10 @@ // parameters imported from source files `define ACTION_TYPE 32'h52324158 -`define RELEASE_LEVEL 32'h00000000 -`define GIT_SHA1 32'h00000000 -`define MAX_MODULES_FPGA 32'd8 +`define RELEASE_LEVEL 32'h003A +`define GIT_SHA1 32'hd4bcfb9f +`define MAX_MODULES_FPGA 32'd16 +`define HBM_SIZE_BYTES 32'h20000000 `define ADDR_AP_CTRL 16'h0000 `define ADDR_SET_LED 16'h0008 @@ -23,6 +24,7 @@ `define ADDR_STALLS_HBM_LO 16'h0030 `define ADDR_STALLS_HBM_HI 16'h0034 `define ADDR_FIFO_STATUS 16'h0038 +`define ADDR_HBM_SIZE 16'h003C `define ADDR_PACKETS_PROC_LO 16'h0040 `define ADDR_PACKETS_PROC_HI 16'h0044 @@ -88,6 +90,7 @@ module action_config output reg [31:0] nframes , output reg [7:0] nmodules , output reg [3:0] nstorage_cells , + output reg [31:0] hbm_size_bytes , output reg data_collection_start , output reg data_collection_cancel , @@ -359,6 +362,9 @@ always @(posedge clk) begin `ADDR_PACKETS_ERR_ETH: begin rdata <= reg_udp_err_eth; end + `ADDR_HBM_SIZE: begin + rdata <= hbm_size_bytes; + end `ADDR_FIFO_STATUS: begin rdata <= reg_fifo_status; end @@ -375,6 +381,17 @@ initial data_collection_start = 1'b0; initial data_collection_cancel = 1'b0; initial reg_ctrl = 32'b0; +initial hbm_size_bytes = `HBM_SIZE_BYTES; + +always @(posedge clk) begin + if (!resetn) + hbm_size_bytes = `HBM_SIZE_BYTES; + else if (reg_data_collection_idle) begin + if (w_hs && waddr == `ADDR_HBM_SIZE) + hbm_size_bytes <= (s_axi_WDATA[31:0] & wmask) | (hbm_size_bytes & !wmask); + end +end + always @(posedge clk) begin if (!resetn) reg_ctrl <= 32'b0; diff --git a/fpga/hls/data_collection_fsm.cpp b/fpga/hls/data_collection_fsm.cpp index 1dade42a..87d59bf3 100644 --- a/fpga/hls/data_collection_fsm.cpp +++ b/fpga/hls/data_collection_fsm.cpp @@ -14,7 +14,8 @@ void data_collection_fsm(AXI_STREAM ð_in, ap_uint<32> one_over_energy, ap_uint<32> nframes, ap_uint<8> nmodules, - ap_uint<4> nstorage_cells) { + ap_uint<4> nstorage_cells, + ap_uint<32> hbm_size_bytes) { #pragma HLS INTERFACE ap_ctrl_none port=return #pragma HLS INTERFACE axis register both port=eth_in @@ -30,6 +31,7 @@ void data_collection_fsm(AXI_STREAM ð_in, #pragma HLS INTERFACE ap_none register port=nframes #pragma HLS INTERFACE ap_none register port=nmodules #pragma HLS INTERFACE ap_none register port=nstorage_cells +#pragma HLS INTERFACE ap_none register port=hbm_size_bytes #pragma HLS PIPELINE II=1 style=flp @@ -75,6 +77,7 @@ void data_collection_fsm(AXI_STREAM ð_in, ACT_REG_NFRAMES(packet_out.data) = nframes; ACT_REG_NMODULES(packet_out.data) = nmodules; ACT_REG_NSTORAGE_CELLS(packet_out.data) = nstorage_cells + 1; + ACT_REG_HBM_SIZE_256b(packet_out.data) = hbm_size_bytes / 32; packet_out.user = 0; packet_out.last = 0; diff --git a/fpga/hls/hls_jfjoch.h b/fpga/hls/hls_jfjoch.h index 314a1acb..47a36c56 100644 --- a/fpga/hls/hls_jfjoch.h +++ b/fpga/hls/hls_jfjoch.h @@ -64,6 +64,7 @@ typedef hls::stream STREAM_512; #define ACT_REG_NFRAMES(x) ((x)(95 , 64)) // 32 bit #define ACT_REG_NMODULES(x) ((x)(132, 128)) // 5 bit (0..31) #define ACT_REG_NSTORAGE_CELLS(x) ((x)(148, 144)) // 5 bit +#define ACT_REG_HBM_SIZE_256b(x) ((x)(191, 160)) // 32 bit struct axis_datamover_ctrl { ap_uint<40+64> data; @@ -82,7 +83,8 @@ void data_collection_fsm(AXI_STREAM ð_in, ap_uint<32> one_over_energy, ap_uint<32> nframes, ap_uint<8> nmodules, - ap_uint<4> nstorage_cells); + ap_uint<4> nstorage_cells, + ap_uint<32> hbm_size_bytes); void load_calibration(STREAM_512 &data_in, STREAM_512 &data_out, hls::stream &datamover_in_cmd, @@ -132,8 +134,7 @@ void save_to_hbm(STREAM_512 &data_in, hls::burst_maxi d_hbm_p2, hls::burst_maxi d_hbm_p3, volatile uint64_t &packets_processed, volatile ap_uint<1> &idle, - ap_uint<8> &err_reg, - uint32_t hbm_size); + ap_uint<8> &err_reg); template ap_uint pack32(ap_int in[32]) { #pragma HLS INLINE diff --git a/fpga/hls/jf_conversion.cpp b/fpga/hls/jf_conversion.cpp index 4f62cdfd..1cff39df 100644 --- a/fpga/hls/jf_conversion.cpp +++ b/fpga/hls/jf_conversion.cpp @@ -115,29 +115,29 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out, #pragma HLS INTERFACE register both axis port=addr_in #pragma HLS INTERFACE register both axis port=addr_out -#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p2 bundle=d_hbm_p2 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p2 bundle=d_hbm_p2 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p3 bundle=d_hbm_p3 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p3 bundle=d_hbm_p3 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p4 bundle=d_hbm_p4 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p4 bundle=d_hbm_p4 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p5 bundle=d_hbm_p5 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p5 bundle=d_hbm_p5 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p6 bundle=d_hbm_p6 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p6 bundle=d_hbm_p6 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p7 bundle=d_hbm_p7 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p7 bundle=d_hbm_p7 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p8 bundle=d_hbm_p8 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p8 bundle=d_hbm_p8 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p9 bundle=d_hbm_p9 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p9 bundle=d_hbm_p9 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p10 bundle=d_hbm_p10 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p10 bundle=d_hbm_p10 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=d_hbm_p11 bundle=d_hbm_p11 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p11 bundle=d_hbm_p11 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 packet_512_t packet_in; @@ -152,6 +152,19 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out, ap_uint<5> modules = ACT_REG_NMODULES(packet_in.data); ap_uint<32> in_one_over_energy = ACT_REG_ONE_OVER_ENERGY(packet_in.data); ap_uint<5> storage_cells = ACT_REG_NSTORAGE_CELLS(packet_in.data); + ap_uint<32> hbm_size_256b = ACT_REG_HBM_SIZE_256b(packet_in.data); + ap_uint<32> offset_hbm_0 = 0 * hbm_size_256b; + ap_uint<32> offset_hbm_1 = 1 * hbm_size_256b; + ap_uint<32> offset_hbm_2 = 2 * hbm_size_256b; + ap_uint<32> offset_hbm_3 = 3 * hbm_size_256b; + ap_uint<32> offset_hbm_4 = 4 * hbm_size_256b; + ap_uint<32> offset_hbm_5 = 5 * hbm_size_256b; + ap_uint<32> offset_hbm_6 = 6 * hbm_size_256b; + ap_uint<32> offset_hbm_7 = 7 * hbm_size_256b; + ap_uint<32> offset_hbm_8 = 8 * hbm_size_256b; + ap_uint<32> offset_hbm_9 = 9 * hbm_size_256b; + ap_uint<32> offset_hbm_10 = 10 * hbm_size_256b; + ap_uint<32> offset_hbm_11 = 11 * hbm_size_256b; one_over_energy_t one_over_energy; for (int i = 0; i < 32; i++) @@ -166,8 +179,8 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out, #pragma HLS PIPELINE II=1 data_in >> packet_in; if (i % HBM_BURST == 0) { - d_hbm_p0.write_request(i, HBM_BURST); - d_hbm_p1.write_request(i, HBM_BURST); + d_hbm_p0.write_request(offset_hbm_0 + i, HBM_BURST); + d_hbm_p1.write_request(offset_hbm_1 + i, HBM_BURST); } d_hbm_p0.write(packet_in.data(255, 0)); d_hbm_p1.write(packet_in.data(511, 256)); @@ -182,8 +195,8 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out, #pragma HLS PIPELINE II=1 data_in >> packet_in; if (i % HBM_BURST == 0) { - d_hbm_p2.write_request(i, HBM_BURST); - d_hbm_p3.write_request(i, HBM_BURST); + d_hbm_p2.write_request(offset_hbm_2 + i, HBM_BURST); + d_hbm_p3.write_request(offset_hbm_3 + i, HBM_BURST); } d_hbm_p2.write(packet_in.data(255, 0)); d_hbm_p3.write(packet_in.data(511, 256)); @@ -198,8 +211,8 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out, #pragma HLS PIPELINE II=1 data_in >> packet_in; if (i % HBM_BURST == 0) { - d_hbm_p4.write_request(i, HBM_BURST); - d_hbm_p5.write_request(i, HBM_BURST); + d_hbm_p4.write_request(offset_hbm_4 + i, HBM_BURST); + d_hbm_p5.write_request(offset_hbm_5 + i, HBM_BURST); } d_hbm_p4.write(packet_in.data(255, 0)); d_hbm_p5.write(packet_in.data(511, 256)); @@ -214,8 +227,8 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out, #pragma HLS PIPELINE II=1 data_in >> packet_in; if (i % HBM_BURST == 0) { - d_hbm_p6.write_request(i, HBM_BURST); - d_hbm_p7.write_request(i, HBM_BURST); + d_hbm_p6.write_request(offset_hbm_6 + i, HBM_BURST); + d_hbm_p7.write_request(offset_hbm_7 + i, HBM_BURST); } d_hbm_p6.write(packet_in.data(255, 0)); d_hbm_p7.write(packet_in.data(511, 256)); @@ -230,8 +243,8 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out, #pragma HLS PIPELINE II=1 data_in >> packet_in; if (i % HBM_BURST == 0) { - d_hbm_p8.write_request(i, HBM_BURST); - d_hbm_p9.write_request(i, HBM_BURST); + d_hbm_p8.write_request(offset_hbm_8 + i, HBM_BURST); + d_hbm_p9.write_request(offset_hbm_9 + i, HBM_BURST); } d_hbm_p8.write(packet_in.data(255, 0)); d_hbm_p9.write(packet_in.data(511, 256)); @@ -246,8 +259,8 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out, #pragma HLS PIPELINE II=1 data_in >> packet_in; if (i % HBM_BURST == 0) { - d_hbm_p10.write_request(i, HBM_BURST); - d_hbm_p11.write_request(i, HBM_BURST); + d_hbm_p10.write_request(offset_hbm_10 + i, HBM_BURST); + d_hbm_p11.write_request(offset_hbm_11 + i, HBM_BURST); } d_hbm_p10.write(packet_in.data(255, 0)); d_hbm_p11.write(packet_in.data(511, 256)); @@ -274,18 +287,18 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out, ap_uint<26> pedestal_offset = (pedestal_location, addr_eth_packet(addr), counter); - d_hbm_p0.read_request(gain_offset, 16); - d_hbm_p1.read_request(gain_offset, 16); - d_hbm_p2.read_request(gain_offset, 16); - d_hbm_p3.read_request(gain_offset, 16); - d_hbm_p4.read_request(gain_offset, 16); - d_hbm_p5.read_request(gain_offset, 16); - d_hbm_p6.read_request(pedestal_offset, 16); - d_hbm_p7.read_request(pedestal_offset, 16); - d_hbm_p8.read_request(pedestal_offset, 16); - d_hbm_p9.read_request(pedestal_offset, 16); - d_hbm_p10.read_request(pedestal_offset, 16); - d_hbm_p11.read_request(pedestal_offset, 16); + d_hbm_p0.read_request(offset_hbm_0 + gain_offset, 16); + d_hbm_p1.read_request(offset_hbm_1 + gain_offset, 16); + d_hbm_p2.read_request(offset_hbm_2 + gain_offset, 16); + d_hbm_p3.read_request(offset_hbm_3 + gain_offset, 16); + d_hbm_p4.read_request(offset_hbm_4 + gain_offset, 16); + d_hbm_p5.read_request(offset_hbm_5 + gain_offset, 16); + d_hbm_p6.read_request(offset_hbm_6 + pedestal_offset, 16); + d_hbm_p7.read_request(offset_hbm_7 + pedestal_offset, 16); + d_hbm_p8.read_request(offset_hbm_8 + pedestal_offset, 16); + d_hbm_p9.read_request(offset_hbm_9 + pedestal_offset, 16); + d_hbm_p10.read_request(offset_hbm_10 + pedestal_offset, 16); + d_hbm_p11.read_request(offset_hbm_11 + pedestal_offset, 16); } ap_uint<256> packed_gainG0_1 = d_hbm_p0.read(); ap_uint<256> packed_gainG0_2 = d_hbm_p1.read(); diff --git a/fpga/hls/save_to_hbm.cpp b/fpga/hls/save_to_hbm.cpp index 24815ef9..d755c1bc 100644 --- a/fpga/hls/save_to_hbm.cpp +++ b/fpga/hls/save_to_hbm.cpp @@ -62,8 +62,7 @@ void save_to_hbm(STREAM_512 &data_in, hls::burst_maxi d_hbm_p2, hls::burst_maxi d_hbm_p3, volatile uint64_t &packets_processed, volatile ap_uint<1> &idle, - ap_uint<8> &err_reg, - uint32_t hbm_size) { + ap_uint<8> &err_reg) { #pragma HLS INTERFACE ap_ctrl_none port=return #pragma HLS INTERFACE register both axis port=data_in #pragma HLS INTERFACE register both axis port=addr_in @@ -71,15 +70,14 @@ void save_to_hbm(STREAM_512 &data_in, #pragma HLS INTERFACE register ap_vld port=packets_processed #pragma HLS INTERFACE register ap_vld port=err_reg #pragma HLS INTERFACE register ap_none port=idle -#pragma HLS INTERFACE register ap_stable port=hbm_size -#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \ max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 -#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 -#pragma HLS INTERFACE m_axi port=d_hbm_p2 bundle=d_hbm_p2 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p2 bundle=d_hbm_p2 depth=512 offset=off \ max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 -#pragma HLS INTERFACE m_axi port=d_hbm_p3 bundle=d_hbm_p3 depth=512 offset=direct \ +#pragma HLS INTERFACE m_axi port=d_hbm_p3 bundle=d_hbm_p3 depth=512 offset=off \ max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 ap_uint<128> packet_mask[MAX_MODULES_FPGA*2]; @@ -124,6 +122,12 @@ void save_to_hbm(STREAM_512 &data_in, ap_uint<5> nmodules = ACT_REG_NMODULES(packet_in.data); ap_uint<32> data_collection_mode = ACT_REG_MODE(packet_in.data); ap_uint<32> data_collection_id = data_collection_mode(31, 16); // upper 16-bit of mode + ap_uint<32> hbm_size_256b = ACT_REG_HBM_SIZE_256b(packet_in.data); + ap_uint<32> offset_hbm_0 = 12 * hbm_size_256b; + ap_uint<32> offset_hbm_1 = 13 * hbm_size_256b; + ap_uint<32> offset_hbm_2 = 14 * hbm_size_256b; + ap_uint<32> offset_hbm_3 = 15 * hbm_size_256b; + ap_uint<32> hbm_size = hbm_size_256b * 32 * 4 / (RAW_MODULE_SIZE * 2); ap_uint<1> mode_nonblocking = (data_collection_mode & MODE_NONBLOCKING_ON_WR) ? 1 : 0; @@ -171,16 +175,8 @@ void save_to_hbm(STREAM_512 &data_in, packet_mask[id] = ap_uint<128>(1) << eth_packet; packet_count[id] = 1; - - if (hbm_size == 64) - handle_val = (handle_val + 1) % 64; - else if (hbm_size == 512) - handle_val = (handle_val + 1) % 512; - else if (hbm_size == 1024) - handle_val = (handle_val + 1) % 1024; - else - handle_val = (handle_val + 1) % 32; + handle_val = (handle_val + 1) % hbm_size; } else { packet_count[id]++; packet_mask[id] |= ap_uint<128>(1) << eth_packet; @@ -190,10 +186,10 @@ void save_to_hbm(STREAM_512 &data_in, for (int i = 0; i < 64; i++) { if (i % 16 == 0) { - d_hbm_p0.write_request(out_frame_addr + i, 16); - d_hbm_p1.write_request(out_frame_addr + i, 16); - d_hbm_p2.write_request(out_frame_addr + i, 16); - d_hbm_p3.write_request(out_frame_addr + i, 16); + d_hbm_p0.write_request(offset_hbm_0 + out_frame_addr + i, 16); + d_hbm_p1.write_request(offset_hbm_1 + out_frame_addr + i, 16); + d_hbm_p2.write_request(offset_hbm_2 + out_frame_addr + i, 16); + d_hbm_p3.write_request(offset_hbm_3 + out_frame_addr + i, 16); } data_in >> packet_in; diff --git a/fpga/pcie_driver/ActionConfig.h b/fpga/pcie_driver/ActionConfig.h index 0e2fd0ce..8a31793b 100644 --- a/fpga/pcie_driver/ActionConfig.h +++ b/fpga/pcie_driver/ActionConfig.h @@ -36,7 +36,7 @@ struct ActionStatus { uint64_t pipeline_stalls_host; uint64_t pipeline_stalls_hbm; uint32_t fifo_status; - uint32_t reserved_2; + uint32_t hbm_size_bytes; uint64_t packets_processed; uint64_t packets_eth; uint64_t packets_icmp; diff --git a/fpga/scripts/bd_pcie.tcl b/fpga/scripts/bd_pcie.tcl index 7ccb8570..b08632ea 100644 --- a/fpga/scripts/bd_pcie.tcl +++ b/fpga/scripts/bd_pcie.tcl @@ -460,10 +460,6 @@ proc create_root_design { parentCell } { CONFIG.DESIGN_NUMBER {0} \ ] [get_bd_cells jungfraujoch_0/action_config_0] - for {set i 0} {$i < 16} {incr i} { - set_property -dict [list CONFIG.CONST_VAL [expr 0x20000000 * $i]] [get_bd_cells jungfraujoch_0/constant_hbm_offset_${i}] - } - # Restore current instance current_bd_instance $oldCurInst diff --git a/fpga/scripts/jfjoch.tcl b/fpga/scripts/jfjoch.tcl index bd5c6d70..1f915f8e 100644 --- a/fpga/scripts/jfjoch.tcl +++ b/fpga/scripts/jfjoch.tcl @@ -372,118 +372,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { CONFIG.Use_RSTB_Pin {true} \ ] $calibration_addr_bram - # Create instance: constant_hbm_offset_0, and set properties - set constant_hbm_offset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_0 - - # Create instance: constant_hbm_offset_1, and set properties - set constant_hbm_offset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_1 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {536870912} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_1 - - # Create instance: constant_hbm_offset_2, and set properties - set constant_hbm_offset_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_2 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {1073741824} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_2 - - # Create instance: constant_hbm_offset_3, and set properties - set constant_hbm_offset_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_3 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {1610612736} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_3 - - # Create instance: constant_hbm_offset_4, and set properties - set constant_hbm_offset_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_4 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {2147483648} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_4 - - # Create instance: constant_hbm_offset_5, and set properties - set constant_hbm_offset_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_5 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {2684354560} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_5 - - # Create instance: constant_hbm_offset_6, and set properties - set constant_hbm_offset_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_6 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {3221225472} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_6 - - # Create instance: constant_hbm_offset_7, and set properties - set constant_hbm_offset_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_7 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {3758096384} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_7 - - # Create instance: constant_hbm_offset_8, and set properties - set constant_hbm_offset_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_8 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {4294967296} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_8 - - # Create instance: constant_hbm_offset_9, and set properties - set constant_hbm_offset_9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_9 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {4831838208} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_9 - - # Create instance: constant_hbm_offset_10, and set properties - set constant_hbm_offset_10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_10 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {5368709120} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_10 - - # Create instance: constant_hbm_offset_11, and set properties - set constant_hbm_offset_11 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_11 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {5905580032} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_11 - - # Create instance: constant_hbm_offset_12, and set properties - set constant_hbm_offset_12 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_12 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {6442450944} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_12 - - # Create instance: constant_hbm_offset_13, and set properties - set constant_hbm_offset_13 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_13 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {6979321856} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_13 - - # Create instance: constant_hbm_offset_14, and set properties - set constant_hbm_offset_14 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_14 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {7516192768} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_14 - - # Create instance: constant_hbm_offset_15, and set properties - set constant_hbm_offset_15 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_hbm_offset_15 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {8053063680} \ - CONFIG.CONST_WIDTH {64} \ - ] $constant_hbm_offset_15 - # Create instance: data_collection_fsm_0, and set properties set data_collection_fsm_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:data_collection_fsm:1.0 data_collection_fsm_0 ] @@ -579,13 +467,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { # Create instance: writer_split_0, and set properties set writer_split_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:writer_split:1.0 writer_split_0 ] - # Create instance: xlconstant_hbm_size, and set properties - set xlconstant_hbm_size [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_hbm_size ] - set_property -dict [ list \ - CONFIG.CONST_VAL {64} \ - CONFIG.CONST_WIDTH {32} \ - ] $xlconstant_hbm_size - # Create interface connections connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins eth_out] [get_bd_intf_pins network_stack/M00_AXIS] connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins eth_in] [get_bd_intf_pins network_stack/eth_in] @@ -680,6 +561,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net action_config_0_fpga_ipv4_addr [get_bd_pins action_config_0/fpga_ipv4_addr] [get_bd_pins network_stack/fpga_ipv4_addr] connect_bd_net -net action_config_0_fpga_mac_addr [get_bd_pins action_config_0/fpga_mac_addr] [get_bd_pins network_stack/fpga_mac_addr] connect_bd_net -net action_config_0_frames_per_trigger [get_bd_pins action_config_0/nframes] [get_bd_pins data_collection_fsm_0/nframes] + connect_bd_net -net action_config_0_hbm_size_bytes [get_bd_pins action_config_0/hbm_size_bytes] [get_bd_pins data_collection_fsm_0/hbm_size_bytes] connect_bd_net -net action_config_0_nmodules [get_bd_pins action_config_0/nmodules] [get_bd_pins data_collection_fsm_0/nmodules] connect_bd_net -net action_config_0_nstorage_cells [get_bd_pins action_config_0/nstorage_cells] [get_bd_pins data_collection_fsm_0/nstorage_cells] connect_bd_net -net action_config_0_one_over_energy [get_bd_pins action_config_0/one_over_energy] [get_bd_pins data_collection_fsm_0/one_over_energy] @@ -702,22 +584,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net axis_work_completion_fifo_0_almost_full [get_bd_pins action_config_0/work_compl_fifo_full] [get_bd_pins axis_work_completion_fifo_0/almost_full] connect_bd_net -net axis_work_request_fifo_0_almost_empty [get_bd_pins action_config_0/work_req_fifo_empty] [get_bd_pins axis_work_request_fifo_0/almost_empty] connect_bd_net -net axis_work_request_fifo_0_almost_full [get_bd_pins action_config_0/work_req_fifo_full] [get_bd_pins axis_work_request_fifo_0/almost_full] - connect_bd_net -net constant_hbm_offset_0_dout [get_bd_pins constant_hbm_offset_0/dout] [get_bd_pins jf_conversion_0/d_hbm_p0_offset] - connect_bd_net -net constant_hbm_offset_10_dout [get_bd_pins constant_hbm_offset_10/dout] [get_bd_pins jf_conversion_0/d_hbm_p10_offset] - connect_bd_net -net constant_hbm_offset_11_dout [get_bd_pins constant_hbm_offset_11/dout] [get_bd_pins jf_conversion_0/d_hbm_p11_offset] - connect_bd_net -net constant_hbm_offset_12_dout [get_bd_pins constant_hbm_offset_12/dout] [get_bd_pins save_to_hbm_0/d_hbm_p0_offset] - connect_bd_net -net constant_hbm_offset_13_dout [get_bd_pins constant_hbm_offset_13/dout] [get_bd_pins save_to_hbm_0/d_hbm_p1_offset] - connect_bd_net -net constant_hbm_offset_14_dout [get_bd_pins constant_hbm_offset_14/dout] [get_bd_pins save_to_hbm_0/d_hbm_p2_offset] - connect_bd_net -net constant_hbm_offset_15_dout [get_bd_pins constant_hbm_offset_15/dout] [get_bd_pins save_to_hbm_0/d_hbm_p3_offset] - connect_bd_net -net constant_hbm_offset_1_dout [get_bd_pins constant_hbm_offset_1/dout] [get_bd_pins jf_conversion_0/d_hbm_p1_offset] - connect_bd_net -net constant_hbm_offset_2_dout [get_bd_pins constant_hbm_offset_2/dout] [get_bd_pins jf_conversion_0/d_hbm_p2_offset] - connect_bd_net -net constant_hbm_offset_3_dout [get_bd_pins constant_hbm_offset_3/dout] [get_bd_pins jf_conversion_0/d_hbm_p3_offset] - connect_bd_net -net constant_hbm_offset_4_dout [get_bd_pins constant_hbm_offset_4/dout] [get_bd_pins jf_conversion_0/d_hbm_p4_offset] - connect_bd_net -net constant_hbm_offset_5_dout [get_bd_pins constant_hbm_offset_5/dout] [get_bd_pins jf_conversion_0/d_hbm_p5_offset] - connect_bd_net -net constant_hbm_offset_6_dout [get_bd_pins constant_hbm_offset_6/dout] [get_bd_pins jf_conversion_0/d_hbm_p6_offset] - connect_bd_net -net constant_hbm_offset_7_dout [get_bd_pins constant_hbm_offset_7/dout] [get_bd_pins jf_conversion_0/d_hbm_p7_offset] - connect_bd_net -net constant_hbm_offset_8_dout [get_bd_pins constant_hbm_offset_8/dout] [get_bd_pins jf_conversion_0/d_hbm_p8_offset] - connect_bd_net -net constant_hbm_offset_9_dout [get_bd_pins constant_hbm_offset_9/dout] [get_bd_pins jf_conversion_0/d_hbm_p9_offset] connect_bd_net -net data_collection_fsm_0_out_idle_V [get_bd_pins action_config_0/data_collection_idle] [get_bd_pins data_collection_fsm_0/out_idle] connect_bd_net -net host_writer_0_err_reg_V [get_bd_pins action_config_0/host_writer_err] [get_bd_pins host_writer_0/err_reg] connect_bd_net -net host_writer_0_err_reg_V_ap_vld [get_bd_pins action_config_0/host_writer_err_valid] [get_bd_pins host_writer_0/err_reg_ap_vld] @@ -745,7 +611,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net timer_hbm_0_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm_0/counter_ap_vld] connect_bd_net -net timer_host_0_counter [get_bd_pins action_config_0/stalls_host] [get_bd_pins timer_host_0/counter] connect_bd_net -net timer_host_0_counter_ap_vld [get_bd_pins action_config_0/stalls_host_valid] [get_bd_pins timer_host_0/counter_ap_vld] - connect_bd_net -net xlconstant_0_dout [get_bd_pins save_to_hbm_0/hbm_size] [get_bd_pins xlconstant_hbm_size/dout] # Restore current instance current_bd_instance $oldCurInst diff --git a/receiver/HLSSimulatedDevice.cpp b/receiver/HLSSimulatedDevice.cpp index 6af6cb6e..71678500 100644 --- a/receiver/HLSSimulatedDevice.cpp +++ b/receiver/HLSSimulatedDevice.cpp @@ -278,7 +278,8 @@ void HLSSimulatedDevice::HLSMainThread() { cfg.one_over_energy, cfg.nframes, cfg.nmodules, - cfg.nstorage_cells); + cfg.nstorage_cells, + hbm_if_size); run_data_collection = 0; } }); @@ -298,18 +299,18 @@ void HLSSimulatedDevice::HLSMainThread() { // 2. Apply pedestal & gain corrections hls_cores.emplace_back([&] { jf_conversion(raw4, converted_1, addr2, addr3, - hbm.data() + 0 * hbm_if_size / 32, - hbm.data() + 1 * hbm_if_size / 32, - hbm.data() + 2 * hbm_if_size / 32, - hbm.data() + 3 * hbm_if_size / 32, - hbm.data() + 4 * hbm_if_size / 32, - hbm.data() + 5 * hbm_if_size / 32, - hbm.data() + 6 * hbm_if_size / 32, - hbm.data() + 7 * hbm_if_size / 32, - hbm.data() + 8 * hbm_if_size / 32, - hbm.data() + 9 * hbm_if_size / 32, - hbm.data() + 10 * hbm_if_size / 32, - hbm.data() + 11 * hbm_if_size / 32); }); + hbm.data(), + hbm.data(), + hbm.data(), + hbm.data(), + hbm.data(), + hbm.data(), + hbm.data(), + hbm.data(), + hbm.data(), + hbm.data(), + hbm.data(), + hbm.data()); }); // Timer procedure - count how many times write_data is not accepting input (to help track down latency issues) hls_cores.emplace_back([&] { timer_host(converted_1, converted_2, counter_host); }); @@ -325,14 +326,13 @@ void HLSSimulatedDevice::HLSMainThread() { // 3. Write images to HBM hls_cores.emplace_back([&] { save_to_hbm(converted_3, addr4, save_to_hbm_completion, - hbm.data() + 12 * hbm_if_size / 32, - hbm.data() + 13 * hbm_if_size / 32, - hbm.data() + 14 * hbm_if_size / 32, - hbm.data() + 15 * hbm_if_size / 32, + hbm.data(), + hbm.data(), + hbm.data(), + hbm.data(), save_to_hbm_packets_processed, save_to_hbm_idle, - save_to_hbm_err_reg, - 16); }); + save_to_hbm_err_reg); }); // 4. Prepare data to write to host memory hls_cores.emplace_back([&] { diff --git a/tests/FPGAIntegrationTest.cpp b/tests/FPGAIntegrationTest.cpp index de8ad964..704d6ed9 100644 --- a/tests/FPGAIntegrationTest.cpp +++ b/tests/FPGAIntegrationTest.cpp @@ -95,7 +95,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_custom_frame", "[FPGA][Ful auto imageBuf = (uint16_t *) test.GetFrameBuffer(image, m); for (int i = 0; i < RAW_MODULE_SIZE; i++) { if (imageBuf[i] != test_frame[i]) - std::cout << m << " " << i << " " << imageBuf[i] << std::endl; + std::cout << m << " " << i << " " << imageBuf[i] << std::endl; REQUIRE(imageBuf[i] == test_frame[i]); } } @@ -689,7 +689,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") { act_reg.one_over_energy, act_reg.nframes, act_reg.nmodules, - act_reg.nstorage_cells); + act_reg.nstorage_cells, + 0); REQUIRE(idle_data_collection == 1); REQUIRE(addr1.empty()); REQUIRE(raw1.empty()); @@ -706,7 +707,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") { act_reg.one_over_energy, act_reg.nframes, act_reg.nmodules, - act_reg.nstorage_cells); + act_reg.nstorage_cells, + 0); REQUIRE(idle_data_collection == 0); REQUIRE(addr1.empty()); REQUIRE(raw1.empty()); @@ -721,7 +723,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") { act_reg.one_over_energy, act_reg.nframes, act_reg.nmodules, - act_reg.nstorage_cells); + act_reg.nstorage_cells, + 0); REQUIRE(idle_data_collection == 0); REQUIRE(addr1.empty()); REQUIRE(raw1.empty()); @@ -739,7 +742,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") { act_reg.one_over_energy, act_reg.nframes, act_reg.nmodules, - act_reg.nstorage_cells); + act_reg.nstorage_cells, + 0); REQUIRE(idle_data_collection == 0); REQUIRE(addr1.empty()); REQUIRE(raw1.empty()); @@ -754,7 +758,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") { act_reg.one_over_energy, act_reg.nframes, act_reg.nmodules, - act_reg.nstorage_cells); + act_reg.nstorage_cells, + 0); REQUIRE(idle_data_collection == 0); REQUIRE(addr1.size() == 1); @@ -771,7 +776,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") { act_reg.one_over_energy, act_reg.nframes, act_reg.nmodules, - act_reg.nstorage_cells); + act_reg.nstorage_cells, + 0); REQUIRE(idle_data_collection == 0); REQUIRE(addr1.size() == 1); @@ -790,7 +796,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") { act_reg.one_over_energy, act_reg.nframes, act_reg.nmodules, - act_reg.nstorage_cells); + act_reg.nstorage_cells, + 0); REQUIRE(idle_data_collection == 0); REQUIRE(addr1.size() == 1); @@ -807,7 +814,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") { act_reg.one_over_energy, act_reg.nframes, act_reg.nmodules, - act_reg.nstorage_cells); + act_reg.nstorage_cells, + 0); REQUIRE(idle_data_collection == 0); REQUIRE(addr1.size() == 2); @@ -824,7 +832,8 @@ TEST_CASE("HLS_DataCollectionFSM","[OpenCAPI]") { act_reg.one_over_energy, act_reg.nframes, act_reg.nmodules, - act_reg.nstorage_cells); + act_reg.nstorage_cells, + 0); REQUIRE(idle_data_collection == 1); REQUIRE(addr1.size() == 2);