From 8f2b01be8011bf56116d2017e37b47bb8a0f88ee Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Wed, 1 Nov 2023 13:31:41 +0100 Subject: [PATCH] FPGA: frame_generator and load_calibration return value for error checking --- fpga/hls/frame_generator.cpp | 30 +++++++++++++----------- fpga/hls/hls_jfjoch.h | 44 +++++++++++++++++------------------ fpga/hls/load_calibration.cpp | 7 +++--- 3 files changed, 43 insertions(+), 38 deletions(-) diff --git a/fpga/hls/frame_generator.cpp b/fpga/hls/frame_generator.cpp index b2d149fa..a3444852 100644 --- a/fpga/hls/frame_generator.cpp +++ b/fpga/hls/frame_generator.cpp @@ -73,19 +73,19 @@ void generate_packet(STREAM_512 &data_out, data_out << packet; } -void frame_generator(STREAM_512 &data_out, - ap_uint<256> *d_hbm_p0, - ap_uint<256> *d_hbm_p1, - ap_uint<32> hbm_size_bytes, - ap_uint<32> frames, - ap_uint<5> modules, - ap_uint<48> src_mac_addr, - ap_uint<48> dest_mac_addr, - ap_uint<32> src_ipv4_addr, - ap_uint<32> dest_ipv4_addr, - ap_uint<64> bunchid, - ap_uint<32> exptime, - ap_uint<32> debug) { +int frame_generator(STREAM_512 &data_out, + ap_uint<256> *d_hbm_p0, + ap_uint<256> *d_hbm_p1, + ap_uint<32> hbm_size_bytes, + ap_uint<32> frames, + ap_uint<5> modules, + ap_uint<48> src_mac_addr, + ap_uint<48> dest_mac_addr, + ap_uint<32> src_ipv4_addr, + ap_uint<32> dest_ipv4_addr, + ap_uint<64> bunchid, + ap_uint<32> exptime, + ap_uint<32> debug) { #pragma HLS INTERFACE mode=s_axilite port=return #pragma HLS INTERFACE mode=s_axilite port=frames #pragma HLS INTERFACE mode=s_axilite port=modules @@ -104,6 +104,9 @@ void frame_generator(STREAM_512 &data_out, max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9 #pragma HLS INTERFACE register both axis port=data_out + if (modules > MAX_MODULES_FPGA) + return 1; + for (uint32_t f = 0; f < frames; f++) { for (uint32_t p = 0; p < 128; p++) { for (uint32_t m = 0; m < modules; m++) { @@ -123,4 +126,5 @@ void frame_generator(STREAM_512 &data_out, } } } + return 0; } diff --git a/fpga/hls/hls_jfjoch.h b/fpga/hls/hls_jfjoch.h index a715c9ea..e88ff38e 100644 --- a/fpga/hls/hls_jfjoch.h +++ b/fpga/hls/hls_jfjoch.h @@ -317,30 +317,30 @@ void timer_host(STREAM_512 &data_in, // Helper cores - not part of main "data" path -void frame_generator(STREAM_512 &data_out, - ap_uint<256> *d_hbm_p0, +int frame_generator(STREAM_512 &data_out, + ap_uint<256> *d_hbm_p0, + ap_uint<256> *d_hbm_p1, + ap_uint<32> hbm_size_bytes, + ap_uint<32> frames, + ap_uint<5> modules, + ap_uint<48> src_mac_addr, + ap_uint<48> dest_mac_addr, + ap_uint<32> src_ipv4_addr, + ap_uint<32> dest_ipv4_addr, + ap_uint<64> bunchid, + ap_uint<32> exptime, + ap_uint<32> debug); + + +int load_calibration(ap_uint<256> *d_hbm_p0, ap_uint<256> *d_hbm_p1, + ap_uint<8> modules, + ap_uint<5> storage_cells, ap_uint<32> hbm_size_bytes, - ap_uint<32> frames, - ap_uint<5> modules, - ap_uint<48> src_mac_addr, - ap_uint<48> dest_mac_addr, - ap_uint<32> src_ipv4_addr, - ap_uint<32> dest_ipv4_addr, - ap_uint<64> bunchid, - ap_uint<32> exptime, - ap_uint<32> debug); - - -void load_calibration(ap_uint<256> *d_hbm_p0, - ap_uint<256> *d_hbm_p1, - ap_uint<8> modules, - ap_uint<5> storage_cells, - ap_uint<32> hbm_size_bytes, - ap_uint<8> destination, - hls::stream &datamover_in_cmd, - hls::stream > &host_memory_in, - uint64_t in_mem_location[(3 * 16 + 3) * MAX_MODULES_FPGA]) ; + ap_uint<8> destination, + hls::stream &datamover_in_cmd, + hls::stream > &host_memory_in, + uint64_t in_mem_location[(3 * 16 + 3) * MAX_MODULES_FPGA]) ; void add_multipixel(STREAM_512 &data_in, STREAM_512 &data_out); void module_upside_down(STREAM_512 &data_in, STREAM_512 &data_out); diff --git a/fpga/hls/load_calibration.cpp b/fpga/hls/load_calibration.cpp index 0723d654..5ff81bd0 100644 --- a/fpga/hls/load_calibration.cpp +++ b/fpga/hls/load_calibration.cpp @@ -25,7 +25,7 @@ void read_module(ap_uint<256> *d_hbm_p0, } } -void load_calibration(ap_uint<256> *d_hbm_p0, +int load_calibration(ap_uint<256> *d_hbm_p0, ap_uint<256> *d_hbm_p1, ap_uint<8> modules, ap_uint<5> storage_cells, @@ -50,11 +50,11 @@ void load_calibration(ap_uint<256> *d_hbm_p0, max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 if (modules > MAX_MODULES_FPGA) - return; + return 1; if (destination == LOAD_CALIBRATION_DEST_CALIB) { if (storage_cells > 16) - return; + return 1; for (int c = 0; c < 3; c++) { for (int m = 0; m < modules; m++) { @@ -103,4 +103,5 @@ void load_calibration(ap_uint<256> *d_hbm_p0, read_module(d_hbm_p0, d_hbm_p1, host_memory_in, offset_hbm_0, offset_hbm_1); } } + return 0; }