From 84bf69b8a65c7bbe54a9ee02367718d683ad87d8 Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Tue, 26 Sep 2023 13:14:43 +0200 Subject: [PATCH] FPGA: frame generator reads from HBM (work in progress) --- common/Definitions.h | 1 + fpga/hls/frame_generator.cpp | 33 ++++++++----- fpga/hls/hls_jfjoch.h | 4 +- fpga/hls/load_calibration.cpp | 8 ++++ fpga/pcie_driver/jfjoch_drv.h | 4 +- fpga/pcie_driver/jfjoch_function.c | 53 +++++++++++++++++---- fpga/pcie_driver/jfjoch_ioctl.c | 24 ++-------- fpga/pcie_driver/jfjoch_ioctl.h | 3 +- fpga/scripts/bd_pcie.tcl | 4 +- fpga/scripts/hbm_u55c.tcl | 5 +- fpga/scripts/jfjoch.tcl | 62 +++++-------------------- receiver/FPGAAcquisitionDevice.cpp | 44 ++++++++++++------ receiver/FPGAAcquisitionDevice.h | 4 +- receiver/HLSSimulatedDevice.cpp | 32 ++++++++++++- receiver/HLSSimulatedDevice.h | 3 +- receiver/PCIExpressDevice.cpp | 21 ++++----- receiver/PCIExpressDevice.h | 2 +- receiver/jfjoch_action_test.cpp | 2 +- receiver/jfjoch_receiver.cpp | 2 +- tests/FPGAIntegrationTest.cpp | 17 +++---- tests/JFJochReceiverIntegrationTest.cpp | 1 + 21 files changed, 188 insertions(+), 141 deletions(-) diff --git a/common/Definitions.h b/common/Definitions.h index 4a90e756..b94eb23a 100644 --- a/common/Definitions.h +++ b/common/Definitions.h @@ -64,6 +64,7 @@ #define LOAD_CALIBRATION_BRAM_SIZE 1024 #define LOAD_CALIBRATION_DEST_CALIB 0 #define LOAD_CALIBRATION_DEST_INTEGRATION 1 +#define LOAD_CALIBRATION_DEST_FRAME_GEN 2 // FPGA register map #define ADDR_CTRL_REGISTER 0x0000 diff --git a/fpga/hls/frame_generator.cpp b/fpga/hls/frame_generator.cpp index 1f9af9d9..4147e9a1 100644 --- a/fpga/hls/frame_generator.cpp +++ b/fpga/hls/frame_generator.cpp @@ -4,7 +4,9 @@ #include "ip_header_checksum.h" void generate_packet(STREAM_512 &data_out, - ap_uint<512> *uram, + ap_uint<256> *d_hbm_p0, + ap_uint<256> *d_hbm_p1, + ap_uint<32> hbm_size_bytes, ap_uint<32> frame, ap_uint<8> module, ap_uint<7> eth_packet, @@ -50,9 +52,15 @@ void generate_packet(STREAM_512 &data_out, data_out << packet; + ap_uint<32> offset_hbm_0 = 18 * hbm_size_bytes / 32; + ap_uint<32> offset_hbm_1 = 19 * hbm_size_bytes / 32; + ap_uint<208> remainder = header(719, 512); for (int i = 0; i < 128; i++) { - ap_uint<512> tmp = uram[(module % FRAME_GENERATOR_MODULES) * 128 * 128 + eth_packet * 128 + i]; + ap_uint<512> tmp; + tmp(255, 0) = d_hbm_p0[offset_hbm_0 + (module % FRAME_GENERATOR_MODULES) * 128 * 128 + eth_packet * 128 + i]; + tmp(511, 256) = d_hbm_p1[offset_hbm_1 + (module % FRAME_GENERATOR_MODULES) * 128 * 128 + eth_packet * 128 + i]; + packet.data(207, 0) = remainder; packet.data(511, 208) = tmp(303, 0); data_out << packet; @@ -66,7 +74,9 @@ void generate_packet(STREAM_512 &data_out, } void frame_generator(STREAM_512 &data_out, - ap_uint<512> *uram, + ap_uint<256> *d_hbm_p0, + ap_uint<256> *d_hbm_p1, + ap_uint<32> hbm_size_bytes, ap_uint<32> frames, ap_uint<5> modules, ap_uint<48> src_mac_addr, @@ -87,19 +97,20 @@ void frame_generator(STREAM_512 &data_out, #pragma HLS INTERFACE mode=ap_none port=src_mac_addr #pragma HLS INTERFACE mode=ap_none port=src_ipv4_addr -#pragma HLS INTERFACE register both axis port=data_out -#pragma HLS INTERFACE m_axi port=uram bundle=uram depth=512 offset=off \ - max_read_burst_length=64 max_write_burst_length=2 latency=5 num_write_outstanding=2 num_read_outstanding=2 -//#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \ -// max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9 -//#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ -// max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9 +#pragma HLS INTERFACE register ap_none port=hbm_size_bytes +#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \ + max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9 +#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ + max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=9 +#pragma HLS INTERFACE register both axis port=data_out for (uint32_t f = 0; f < frames; f++) { for (uint32_t p = 0; p < 128; p++) { for (uint32_t m = 0; m < modules; m++) { generate_packet(data_out, - uram, + d_hbm_p0, + d_hbm_p1, + hbm_size_bytes, f, m, p, src_mac_addr, dest_mac_addr, diff --git a/fpga/hls/hls_jfjoch.h b/fpga/hls/hls_jfjoch.h index 85f25ed8..14a6da62 100644 --- a/fpga/hls/hls_jfjoch.h +++ b/fpga/hls/hls_jfjoch.h @@ -109,7 +109,9 @@ void load_calibration(ap_uint<256> *d_hbm_p0, uint64_t in_mem_location[(3 * 16 + 3) * MAX_MODULES_FPGA]) ; void frame_generator(STREAM_512 &data_out, - ap_uint<512> *uram, + ap_uint<256> *d_hbm_p0, + ap_uint<256> *d_hbm_p1, + ap_uint<32> hbm_size_bytes, ap_uint<32> frames, ap_uint<5> modules, ap_uint<48> src_mac_addr, diff --git a/fpga/hls/load_calibration.cpp b/fpga/hls/load_calibration.cpp index bc0a49f5..5ab1d5a4 100644 --- a/fpga/hls/load_calibration.cpp +++ b/fpga/hls/load_calibration.cpp @@ -85,5 +85,13 @@ void load_calibration(ap_uint<256> *d_hbm_p0, size_t offset_hbm_1 = 17 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64; read_module(d_hbm_p0, d_hbm_p1, host_memory_in, offset_hbm_0, offset_hbm_1); } + } else if (destination == LOAD_CALIBRATION_DEST_FRAME_GEN) { + for (int m = 0; m < modules; m++) { +#pragma HLS PIPELINE OFF + setup_datamover(datamover_in_cmd, in_mem_location[m], RAW_MODULE_SIZE * sizeof(int16_t)); + size_t offset_hbm_0 = 18 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64; + size_t offset_hbm_1 = 19 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64; + read_module(d_hbm_p0, d_hbm_p1, host_memory_in, offset_hbm_0, offset_hbm_1); + } } } diff --git a/fpga/pcie_driver/jfjoch_drv.h b/fpga/pcie_driver/jfjoch_drv.h index 9090b8f8..89c6f90f 100644 --- a/fpga/pcie_driver/jfjoch_drv.h +++ b/fpga/pcie_driver/jfjoch_drv.h @@ -41,7 +41,6 @@ #define CMS_OFFSET (0x0C0000) #define CMAC_OFFSET (0x020000) #define PCIE_OFFSET (0x090000) -#define INT_PKT_GEN_OFFSET (0x800000) #define FRAME_GEN_OFFSET (0x080000) #define ADDR_LOAD_CALIBRATION_CTRL (LOAD_CALIBRATION_OFFSET | 0x000000) @@ -123,8 +122,7 @@ void jfjoch_set_mac_addr(struct jfjoch_drvdata *drvdata, u64 *mac_addr); void jfjoch_get_mac_addr(struct jfjoch_drvdata *drvdata, u64 *mac_addr); void jfjoch_set_ipv4_addr(struct jfjoch_drvdata *drvdata, const u32 *addr); void jfjoch_get_ipv4_addr(struct jfjoch_drvdata *drvdata, u32 *addr); -void jfjoch_load_int_pkt_gen(struct jfjoch_drvdata *drvdata, char* output); -void jfjoch_save_int_pkt_gen(struct jfjoch_drvdata *drvdata, const char* input); +int jfjoch_load_internal_generator_frame(struct jfjoch_drvdata *drvdata, struct ActionConfig *config); int jfjoch_load_calibration(struct jfjoch_drvdata *drvdata, struct ActionConfig *config); int jfjoch_load_integration_map(struct jfjoch_drvdata *drvdata, struct ActionConfig *config); int jfjoch_run_frame_gen(struct jfjoch_drvdata *drvdata, struct FrameGeneratorConfig *config); diff --git a/fpga/pcie_driver/jfjoch_function.c b/fpga/pcie_driver/jfjoch_function.c index 5412a11b..4dec7804 100644 --- a/fpga/pcie_driver/jfjoch_function.c +++ b/fpga/pcie_driver/jfjoch_function.c @@ -80,14 +80,6 @@ int jfjoch_send_wr(struct jfjoch_drvdata *drvdata, u32 handle) { return 0; } -void jfjoch_load_int_pkt_gen(struct jfjoch_drvdata *drvdata, char* output) { - memcpy_fromio(output, drvdata->bar0 + INT_PKT_GEN_OFFSET, INT_PKT_GEN_FRAME_SIZE_BYTES); -} - -void jfjoch_save_int_pkt_gen(struct jfjoch_drvdata *drvdata, const char* input) { - memcpy_toio(drvdata->bar0 + INT_PKT_GEN_OFFSET, input, INT_PKT_GEN_FRAME_SIZE_BYTES); -} - int jfjoch_read_wc(struct jfjoch_drvdata *drvdata, u32 *output) { u32 rta; int i; @@ -382,7 +374,52 @@ int jfjoch_load_integration_map(struct jfjoch_drvdata *drvdata, struct ActionCon } return 0; +} + +int jfjoch_load_internal_generator_frame(struct jfjoch_drvdata *drvdata, struct ActionConfig *config) { + struct device *const dev = &drvdata->pdev->dev; + u32 i; + u32 cell_count = config->nmodules; + + if (cell_count > drvdata->nbuf) { + dev_err(dev, "Not enough buffers to support this card\n"); + return -EINVAL; + } + + for (i = 0; i < cell_count; i++) { + u64 addr = drvdata->bufs[i].dma_address; + iowrite32(PCI_DMA_L(addr), drvdata->bar0 + ADDR_LOAD_CALIBRATION_MEM + i * 2 * 4); + iowrite32(PCI_DMA_H(addr), drvdata->bar0 + ADDR_LOAD_CALIBRATION_MEM + (i * 2 + 1) * 4); + } + + // Start DMA + // Clear counters and RUN H2C + iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0); + iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0); + iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04); + + iowrite32(config->nmodules, drvdata->bar0 + ADDR_LOAD_CALIBRATION_MOD); + iowrite32(LOAD_CALIBRATION_DEST_FRAME_GEN, drvdata->bar0 + ADDR_LOAD_CALIBRATION_DEST); + iowrite32(0x1, drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL); + + i = 0; + while (i < 1000) { + if (ioread32(drvdata->bar0 + ADDR_LOAD_CALIBRATION_CTRL) & (1 << 1)) + break; + msleep(10); + i++; + } + + // STOP H2C channel + iowrite32(0, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04); + + if (i == 1000) { + dev_err(dev, "Load calibration didn't finish in 10 seconds\n"); + return -ETIMEDOUT; + } + + return 0; } int jfjoch_run_frame_gen(struct jfjoch_drvdata *drvdata, struct FrameGeneratorConfig *config) { diff --git a/fpga/pcie_driver/jfjoch_ioctl.c b/fpga/pcie_driver/jfjoch_ioctl.c index e39ccbe8..512eab8b 100644 --- a/fpga/pcie_driver/jfjoch_ioctl.c +++ b/fpga/pcie_driver/jfjoch_ioctl.c @@ -110,28 +110,10 @@ long jfjoch_cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { if (copy_from_user(&frame_generator_config, (char *) arg, sizeof(struct FrameGeneratorConfig)) != 0) return -EFAULT; return jfjoch_run_frame_gen(drvdata, &frame_generator_config); - case IOCTL_JFJOCH_SET_INT_PKT: - tmp = vmalloc(INT_PKT_GEN_FRAME_SIZE_BYTES); - if (tmp == NULL) - return -ENOMEM; - if (copy_from_user(tmp, (char *) arg, INT_PKT_GEN_FRAME_SIZE_BYTES) != 0) { - vfree(tmp); + case IOCTL_JFJOCH_LOAD_INT_GEN: + if (copy_from_user(&config, (char *) arg, sizeof(struct ActionConfig)) != 0) return -EFAULT; - } - jfjoch_save_int_pkt_gen(drvdata, tmp); - vfree(tmp); - return 0; - case IOCTL_JFJOCH_GET_INT_PKT: - tmp = vmalloc(INT_PKT_GEN_FRAME_SIZE_BYTES); - if (tmp == NULL) - return -ENOMEM; - jfjoch_load_int_pkt_gen(drvdata, tmp); - if (copy_to_user((char *) arg, tmp, INT_PKT_GEN_FRAME_SIZE_BYTES) != 0) { - vfree(tmp); - return -EFAULT; - } - vfree(tmp); - return 0; + return jfjoch_load_internal_generator_frame(drvdata, &config); case IOCTL_JFJOCH_C2H_DMA_DESC: exchange[0] = jfjoch_get_c2h_descriptors(drvdata); if (copy_to_user((char *) arg, exchange, sizeof(u32)) != 0) diff --git a/fpga/pcie_driver/jfjoch_ioctl.h b/fpga/pcie_driver/jfjoch_ioctl.h index 92863818..cd5778b9 100644 --- a/fpga/pcie_driver/jfjoch_ioctl.h +++ b/fpga/pcie_driver/jfjoch_ioctl.h @@ -32,8 +32,7 @@ #define IOCTL_JFJOCH_DEFAULT_MAC _IO (IOCTL_JFJOCH_MAGIC, 16) #define IOCTL_JFJOCH_SET_IPV4 _IOW(IOCTL_JFJOCH_MAGIC, 17, uint32_t) #define IOCTL_JFJOCH_GET_IPV4 _IOR(IOCTL_JFJOCH_MAGIC, 18, uint32_t) -#define IOCTL_JFJOCH_SET_INT_PKT _IOW(IOCTL_JFJOCH_MAGIC, 19, char *) -#define IOCTL_JFJOCH_GET_INT_PKT _IOR(IOCTL_JFJOCH_MAGIC, 20, char *) +#define IOCTL_JFJOCH_LOAD_INT_GEN _IOW(IOCTL_JFJOCH_MAGIC, 19, struct ActionConfig) #define IOCTL_JFJOCH_LOAD_CALIB _IOW(IOCTL_JFJOCH_MAGIC, 21, struct ActionConfig) #define IOCTL_JFJOCH_LOAD_INT_MAP _IOW(IOCTL_JFJOCH_MAGIC, 22, struct ActionConfig) #define IOCTL_JFJOCH_RUN_FRAME_GEN _IOW(IOCTL_JFJOCH_MAGIC, 23, struct FrameGeneratorConfig) diff --git a/fpga/scripts/bd_pcie.tcl b/fpga/scripts/bd_pcie.tcl index 2a3f99b2..df8797d8 100644 --- a/fpga/scripts/bd_pcie.tcl +++ b/fpga/scripts/bd_pcie.tcl @@ -399,6 +399,8 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p15 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_15] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p15] connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p16 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_16] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p16] connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p17 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_17] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p17] + connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p18 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_18] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p18] + connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p19 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_19] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p19] connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_data [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_data] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_data] connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_cmd] connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_h2c_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_h2c_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_h2c_cmd] @@ -451,8 +453,6 @@ proc create_root_design { parentCell } { assign_bd_address -offset 0x00080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/frame_generator_0/s_axi_control/Reg] -force assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/xdma_0/S_AXI_LITE/CTL0] -force assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force - assign_bd_address -offset 0x00800000 -range 0x00800000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_frame_generator_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x00000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jungfraujoch_0/frame_generator_0/Data_m_axi_uram] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_frame_generator_1/S_AXI/Mem0] -force assign_bd_address diff --git a/fpga/scripts/hbm_u55c.tcl b/fpga/scripts/hbm_u55c.tcl index 6363d414..fc0ce8eb 100644 --- a/fpga/scripts/hbm_u55c.tcl +++ b/fpga/scripts/hbm_u55c.tcl @@ -217,7 +217,6 @@ proc create_hier_cell_hbm_infrastructure { parentCell nameHier } { CONFIG.USER_MC9_LOOKAHEAD_SBRF {true} \ CONFIG.USER_MC9_REF_TEMP_COMP {false} \ CONFIG.USER_MC9_TRAFFIC_OPTION {Linear} \ - CONFIG.USER_MC_ENABLE_09 {FALSE} \ CONFIG.USER_MC_ENABLE_10 {FALSE} \ CONFIG.USER_MC_ENABLE_11 {FALSE} \ CONFIG.USER_MC_ENABLE_12 {FALSE} \ @@ -234,8 +233,6 @@ proc create_hier_cell_hbm_infrastructure { parentCell nameHier } { CONFIG.USER_PHY_ENABLE_13 {TRUE} \ CONFIG.USER_PHY_ENABLE_14 {TRUE} \ CONFIG.USER_PHY_ENABLE_15 {TRUE} \ - CONFIG.USER_SAXI_18 {false} \ - CONFIG.USER_SAXI_19 {false} \ CONFIG.USER_SAXI_20 {false} \ CONFIG.USER_SAXI_21 {false} \ CONFIG.USER_SAXI_22 {false} \ @@ -284,7 +281,7 @@ proc create_hier_cell_hbm_infrastructure { parentCell nameHier } { connect_bd_net [get_bd_pins axi_resetn] [get_bd_pins hbm/APB_0_PRESET_N] [get_bd_pins hbm/APB_1_PRESET_N] connect_bd_net [get_bd_pins refclk100] [get_bd_pins hbm/APB_0_PCLK] [get_bd_pins hbm/APB_1_PCLK] [get_bd_pins hbm/HBM_REF_CLK_0] [get_bd_pins hbm/HBM_REF_CLK_1] - for {set i 0} {$i < 18} {incr i} { + for {set i 0} {$i < 20} {incr i} { create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hbm_$i set cell [create_bd_cell -type ip -vlnv {xilinx.com:ip:axi_register_slice:*} axi_register_slice_$i ] diff --git a/fpga/scripts/jfjoch.tcl b/fpga/scripts/jfjoch.tcl index 151605f1..e459b658 100644 --- a/fpga/scripts/jfjoch.tcl +++ b/fpga/scripts/jfjoch.tcl @@ -75,6 +75,10 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p17 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p18 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p19 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_c2h_data create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_c2h_datamover_cmd @@ -106,24 +110,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { CONFIG.MAX_MODULES_FPGA_PARAM {0x00000010} \ ] $action_config_0 - # Create instance: axi_bram_ctrl_frame_generator_0, and set properties - set axi_bram_ctrl_frame_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_frame_generator_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {512} \ - CONFIG.PROTOCOL {AXI4} \ - CONFIG.READ_LATENCY {3} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_frame_generator_0 - - # Create instance: axi_bram_ctrl_frame_generator_1, and set properties - set axi_bram_ctrl_frame_generator_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_frame_generator_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {512} \ - CONFIG.PROTOCOL {AXI4} \ - CONFIG.READ_LATENCY {3} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_frame_generator_1 - # Create instance: axi_datamover_0, and set properties set axi_datamover_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_datamover:5.1 axi_datamover_0 ] set_property -dict [ list \ @@ -466,28 +452,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { # Create instance: integration_0, and set properties set integration_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:integration:1.0 integration_0 ] - # Create instance: frame_generator_uram, and set properties - set frame_generator_uram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 frame_generator_uram ] - set_property -dict [ list \ - CONFIG.Assume_Synchronous_Clk {true} \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Enable_B {Use_ENB_Pin} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.Operating_Mode_A {NO_CHANGE} \ - CONFIG.Operating_Mode_B {NO_CHANGE} \ - CONFIG.PRIM_type_to_Implement {URAM} \ - CONFIG.Port_A_Write_Rate {50} \ - CONFIG.Port_B_Clock {100} \ - CONFIG.Port_B_Enable_Rate {100} \ - CONFIG.Port_B_Write_Rate {50} \ - CONFIG.READ_LATENCY_A {3} \ - CONFIG.READ_LATENCY_B {3} \ - CONFIG.Read_Width_B {512} \ - CONFIG.Use_Byte_Write_Enable {true} \ - CONFIG.Use_RSTB_Pin {true} \ - CONFIG.Write_Width_B {512} \ - ] $frame_generator_uram - # Create instance: jf_conversion_0, and set properties set jf_conversion_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:jf_conversion:1.0 jf_conversion_0 ] @@ -521,7 +485,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] set_property -dict [ list \ CONFIG.NUM_CLKS {1} \ - CONFIG.NUM_MI {5} \ + CONFIG.NUM_MI {4} \ CONFIG.NUM_SI {1} \ ] $smartconnect_0 @@ -543,8 +507,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { # Create interface connections connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins eth_out] [get_bd_intf_pins network_stack/M00_AXIS] connect_bd_intf_net -intf_net S_AXIS_1 [get_bd_intf_pins s_axis_h2c_data] [get_bd_intf_pins axis_data_fifo_h2c_data/S_AXIS] - connect_bd_intf_net -intf_net axi_bram_ctrl_frame_generator_1_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_frame_generator_1/BRAM_PORTA] [get_bd_intf_pins frame_generator_uram/BRAM_PORTB] - connect_bd_intf_net -intf_net axi_bram_ctrl_frame_generator_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_frame_generator_0/BRAM_PORTA] [get_bd_intf_pins frame_generator_uram/BRAM_PORTA] connect_bd_intf_net -intf_net axi_datamover_0_M_AXIS_MM2S [get_bd_intf_pins axi_datamover_0/M_AXIS_MM2S] [get_bd_intf_pins axis_datamover_fifo_2/S_AXIS] connect_bd_intf_net -intf_net axi_datamover_0_M_AXI_MM2S [get_bd_intf_pins m_axi_d_hbm_p12] [get_bd_intf_pins axi_datamover_0/M_AXI_MM2S] connect_bd_intf_net -intf_net axi_datamover_0_M_AXI_S2MM [get_bd_intf_pins m_axi_d_hbm_p13] [get_bd_intf_pins axi_datamover_0/M_AXI_S2MM] @@ -596,7 +558,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_intf_net -intf_net data_collection_fsm_0_data_out [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins data_collection_fsm_0/data_out] connect_bd_intf_net -intf_net eth_in_1 [get_bd_intf_pins eth_in] [get_bd_intf_pins stream_merge_0/input_1] connect_bd_intf_net -intf_net frame_generator_0_data_out [get_bd_intf_pins axis_frame_generator_fifo_0/S_AXIS] [get_bd_intf_pins frame_generator_0/data_out] - connect_bd_intf_net -intf_net frame_generator_0_m_axi_uram [get_bd_intf_pins axi_bram_ctrl_frame_generator_1/S_AXI] [get_bd_intf_pins frame_generator_0/m_axi_uram] + connect_bd_intf_net -intf_net frame_generator_0_m_axi_d_hbm_p0 [get_bd_intf_pins m_axi_d_hbm_p18] [get_bd_intf_pins frame_generator_0/m_axi_d_hbm_p0] + connect_bd_intf_net -intf_net frame_generator_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p19] [get_bd_intf_pins frame_generator_0/m_axi_d_hbm_p1] connect_bd_intf_net -intf_net host_writer_0_datamover_out_cmd [get_bd_intf_pins axis_data_fifo_c2h_cmd/S_AXIS] [get_bd_intf_pins host_writer_0/datamover_out_cmd] connect_bd_intf_net -intf_net host_writer_0_host_memory_out [get_bd_intf_pins axis_register_slice_host_mem/S_AXIS] [get_bd_intf_pins host_writer_0/host_memory_out] connect_bd_intf_net -intf_net host_writer_0_m_axis_completion [get_bd_intf_pins axis_work_completion_fifo_0/S_AXIS] [get_bd_intf_pins host_writer_0/m_axis_completion] @@ -642,8 +605,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins action_config_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI] connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins mailbox_0/S0_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI] connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins load_calibration_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M02_AXI] - connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_bram_ctrl_frame_generator_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI] - connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins frame_generator_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M04_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins frame_generator_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M03_AXI] connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/M00_AXI] connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p2] [get_bd_intf_pins smartconnect_2/M00_AXI] connect_bd_intf_net -intf_net stream_merge_0_output_r [get_bd_intf_pins axis_eth_in_fifo/S_AXIS] [get_bd_intf_pins stream_merge_0/output_r] @@ -658,11 +620,11 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net action_config_0_fpga_ipv4_addr [get_bd_pins action_config_0/fpga_ipv4_addr] [get_bd_pins frame_generator_0/src_ipv4_addr] [get_bd_pins network_stack/fpga_ipv4_addr] connect_bd_net -net action_config_0_fpga_mac_addr [get_bd_pins action_config_0/fpga_mac_addr] [get_bd_pins frame_generator_0/src_mac_addr] [get_bd_pins network_stack/fpga_mac_addr] connect_bd_net -net action_config_0_frames_per_trigger [get_bd_pins action_config_0/nframes] [get_bd_pins data_collection_fsm_0/nframes] - connect_bd_net -net action_config_0_hbm_size_bytes [get_bd_pins action_config_0/hbm_size_bytes] [get_bd_pins load_calibration_0/hbm_size_bytes] [get_bd_pins load_from_hbm_0/hbm_size_bytes] [get_bd_pins save_to_hbm_0/hbm_size_bytes] [get_bd_pins jf_conversion_0/hbm_size_bytes] [get_bd_pins integration_0/hbm_size_bytes] + connect_bd_net -net action_config_0_hbm_size_bytes [get_bd_pins action_config_0/hbm_size_bytes] [get_bd_pins frame_generator_0/hbm_size_bytes] [get_bd_pins integration_0/hbm_size_bytes] [get_bd_pins jf_conversion_0/hbm_size_bytes] [get_bd_pins load_calibration_0/hbm_size_bytes] [get_bd_pins load_from_hbm_0/hbm_size_bytes] [get_bd_pins save_to_hbm_0/hbm_size_bytes] connect_bd_net -net action_config_0_nmodules [get_bd_pins action_config_0/nmodules] [get_bd_pins data_collection_fsm_0/nmodules] connect_bd_net -net action_config_0_nstorage_cells [get_bd_pins action_config_0/nstorage_cells] [get_bd_pins data_collection_fsm_0/nstorage_cells] connect_bd_net -net action_config_0_one_over_energy [get_bd_pins action_config_0/one_over_energy] [get_bd_pins data_collection_fsm_0/one_over_energy] - connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_frame_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_frame_generator_1/s_axi_aclk] [get_bd_pins axi_datamover_0/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_datamover_1/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_1/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_compl_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_7/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aclk] [get_bd_pins axis_datamover_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_fifo_3/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_hbm_handles_fifo/s_axis_aclk] [get_bd_pins axis_integration_result_fifo/s_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins integration_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins load_from_hbm_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk] + connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_datamover_0/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_datamover_1/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_1/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_compl_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_7/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aclk] [get_bd_pins axis_datamover_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_fifo_3/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_hbm_handles_fifo/s_axis_aclk] [get_bd_pins axis_integration_result_fifo/s_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins integration_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins load_from_hbm_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk] connect_bd_net -net axis_addr_fifo_0_almost_empty [get_bd_pins action_config_0/calib_addr_fifo_empty] [get_bd_pins axis_addr_fifo_0/almost_empty] connect_bd_net -net axis_addr_fifo_0_almost_full [get_bd_pins action_config_0/calib_addr_fifo_full] [get_bd_pins axis_addr_fifo_0/almost_full] connect_bd_net -net axis_addr_fifo_4_almost_empty [get_bd_pins action_config_0/last_addr_fifo_empty] [get_bd_pins axis_addr_fifo_1/almost_empty] @@ -715,7 +677,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net network_stack_packets_udp_ap_vld [get_bd_pins action_config_0/packets_udp_valid] [get_bd_pins network_stack/packets_udp_ap_vld] connect_bd_net -net one_dout [get_bd_pins axi_datamover_0/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_0/m_axis_s2mm_sts_tready] [get_bd_pins axi_datamover_1/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_1/m_axis_s2mm_sts_tready] [get_bd_pins one/dout] connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_0/s_axis_aresetn] [get_bd_pins axis_compl_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_compl_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_7/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_3/s_axis_aresetn] [get_bd_pins axis_eth_in_fifo/s_axis_aresetn] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aresetn] [get_bd_pins axis_hbm_handles_fifo/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo/s_axis_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn] - connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_frame_generator_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_frame_generator_1/s_axi_aresetn] [get_bd_pins axi_datamover_0/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_1/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins frame_generator_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins integration_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins load_from_hbm_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins save_to_hbm_0/ap_rst_n] [get_bd_pins stream_merge_0/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n] + connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_datamover_0/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_1/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins frame_generator_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins integration_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins load_from_hbm_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins save_to_hbm_0/ap_rst_n] [get_bd_pins stream_merge_0/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n] connect_bd_net -net timer_hbm_counter [get_bd_pins action_config_0/stalls_hbm] [get_bd_pins timer_hbm/counter] connect_bd_net -net timer_hbm_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm/counter_ap_vld] connect_bd_net -net timer_host_counter [get_bd_pins action_config_0/stalls_host] [get_bd_pins timer_host/counter] @@ -723,4 +685,4 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { # Restore current instance current_bd_instance $oldCurInst -} +} \ No newline at end of file diff --git a/receiver/FPGAAcquisitionDevice.cpp b/receiver/FPGAAcquisitionDevice.cpp index 8561e408..8795fafb 100644 --- a/receiver/FPGAAcquisitionDevice.cpp +++ b/receiver/FPGAAcquisitionDevice.cpp @@ -80,6 +80,28 @@ void FPGAAcquisitionDevice::InitializeIntegrationMap(const DiffractionExperiment HW_LoadIntegrationMap(modules); } +void FPGAAcquisitionDevice::SetInternalGeneratorFrame(const std::vector &v) { + if (v.size() == RAW_MODULE_SIZE) { + for (int m = 0; m < FRAME_GENERATOR_MODULES; m++) { + memcpy(internal_pkt_gen_frame.data() + m * RAW_MODULE_SIZE, + v.data(), RAW_MODULE_SIZE * sizeof(uint16_t)); + } + } else if (v.size() == RAW_MODULE_SIZE * FRAME_GENERATOR_MODULES) { + memcpy(internal_pkt_gen_frame.data(), v.data(), FRAME_GENERATOR_MODULES * RAW_MODULE_SIZE * sizeof(uint16_t)); + } else + throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, + "Error in size of custom internal generator frame"); + + if (FRAME_GENERATOR_MODULES > buffer_device.size()) + throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, + "Not enough host/FPGA buffers to load all integration map values"); + + for (int m = 0; m < FRAME_GENERATOR_MODULES; m++) + memcpy(buffer_device[m], internal_pkt_gen_frame.data() + m * RAW_MODULE_SIZE, RAW_MODULE_SIZE * sizeof(uint16_t)); + + HW_LoadInternalGeneratorFrame(FRAME_GENERATOR_MODULES); +} + void FPGAAcquisitionDevice::InitializeCalibration(const DiffractionExperiment &experiment, const JFCalibration &calib) { auto offset = experiment.GetFirstModuleOfDataStream(data_stream); @@ -279,23 +301,19 @@ JFJochProtoBuf::FPGAStatus FPGAAcquisitionDevice::GetStatus() const { return ret; } -void FPGAAcquisitionDevice::SetCustomInternalGeneratorFrame(const std::vector &v) { - if (v.size() != RAW_MODULE_SIZE) - throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, - "Error in size of custom internal generator frame"); - for (int m = 0; m < FRAME_GENERATOR_MODULES; m++) { - for (int i = 0; i < RAW_MODULE_SIZE; i++) - internal_pkt_gen_frame[m * RAW_MODULE_SIZE + i] = v[i]; - } -} - std::vector FPGAAcquisitionDevice::GetInternalGeneratorFrame() const { return internal_pkt_gen_frame; } +void FPGAAcquisitionDevice::SetInternalGeneratorFrame() { + std::vector tmp(RAW_MODULE_SIZE); + for (int i = 0; i < RAW_MODULE_SIZE; i++) + tmp[i] = i % 65536; + SetInternalGeneratorFrame(tmp); +} + FPGAAcquisitionDevice::FPGAAcquisitionDevice(uint16_t data_stream) : AcquisitionDevice(data_stream), internal_pkt_gen_frame(RAW_MODULE_SIZE * FRAME_GENERATOR_MODULES) { - for (int i = 0; i < RAW_MODULE_SIZE * FRAME_GENERATOR_MODULES; i++) - internal_pkt_gen_frame[i] = i % 65536; -} \ No newline at end of file +} + diff --git a/receiver/FPGAAcquisitionDevice.h b/receiver/FPGAAcquisitionDevice.h index c59af2b3..e8466533 100644 --- a/receiver/FPGAAcquisitionDevice.h +++ b/receiver/FPGAAcquisitionDevice.h @@ -28,6 +28,7 @@ class FPGAAcquisitionDevice : public AcquisitionDevice { virtual void HW_LoadCalibration(uint32_t modules, uint32_t storage_cells) = 0; virtual void HW_LoadIntegrationMap(uint32_t modules) = 0; + virtual void HW_LoadInternalGeneratorFrame(uint32_t modules) = 0; virtual bool HW_ReadMailbox(uint32_t values[16]) = 0; virtual bool HW_SendWorkRequest(uint32_t handle) = 0; void StartSendingWorkRequests() override; @@ -44,7 +45,8 @@ public: JFJochProtoBuf::FPGAStatus GetStatus() const override; void InitializeCalibration(const DiffractionExperiment &experiment, const JFCalibration &calib) override; void InitializeIntegrationMap(const DiffractionExperiment &experiment, const std::vector &v) override; - void SetCustomInternalGeneratorFrame(const std::vector &v); + void SetInternalGeneratorFrame(const std::vector &v); + void SetInternalGeneratorFrame(); std::vector GetInternalGeneratorFrame() const override; }; diff --git a/receiver/HLSSimulatedDevice.cpp b/receiver/HLSSimulatedDevice.cpp index c69728d3..fdb0fdf4 100644 --- a/receiver/HLSSimulatedDevice.cpp +++ b/receiver/HLSSimulatedDevice.cpp @@ -139,7 +139,9 @@ void HLSSimulatedDevice::FPGA_StartAction(const DiffractionExperiment &experimen idle = false; if (experiment.IsUsingInternalPacketGen()) { frame_generator(din_frame_generator, - reinterpret_cast *>(internal_pkt_gen_frame.data()), + hbm.data(), + hbm.data(), + hbm_if_size, experiment.GetFrameNum() + DELAY_FRAMES_STOP_AND_QUIT + 1, experiment.GetModulesNum(data_stream), mac_addr, @@ -483,6 +485,34 @@ void HLSSimulatedDevice::HW_LoadIntegrationMap(uint32_t modules) { throw std::runtime_error("Datamover queue is not empty"); } +void HLSSimulatedDevice::HW_LoadInternalGeneratorFrame(uint32_t modules) { + if (logger) + logger->Info("Load to frame generator"); + + auto in_mem_location32 = (uint32_t *) calibration_addr_bram; + + for (int i = 0; i < modules; i++) { + in_mem_location32[2 * i ] = ((uint64_t) buffer_device[i]) & UINT32_MAX; + in_mem_location32[2 * i + 1] = ((uint64_t) buffer_device[i]) >> 32; + } + + load_calibration(hbm.data(), + hbm.data(), + modules, + 0, + hbm_if_size, + LOAD_CALIBRATION_DEST_FRAME_GEN, + datamover_in.GetCtrlStream(), + datamover_in.GetDataStream(), + calibration_addr_bram); + if (logger) + logger->Info("Load to frame generator done"); + + if (!datamover_in.GetDataStream().empty()) + throw std::runtime_error("Datamover queue is not empty"); +} + + uint32_t HLSSimulatedDevice::GetCompletedDescriptors() const { return datamover_out.GetCompletedDescriptors(); } \ No newline at end of file diff --git a/receiver/HLSSimulatedDevice.h b/receiver/HLSSimulatedDevice.h index 0d96ae58..15015273 100644 --- a/receiver/HLSSimulatedDevice.h +++ b/receiver/HLSSimulatedDevice.h @@ -22,7 +22,7 @@ class HLSSimulatedDevice : public FPGAAcquisitionDevice { volatile bool idle; - constexpr static const size_t hbm_if_count = 18; + constexpr static const size_t hbm_if_count = 20; constexpr static const size_t hbm_if_size = 32*1024*1024LU; std::vector> hbm; @@ -53,6 +53,7 @@ class HLSSimulatedDevice : public FPGAAcquisitionDevice { bool HW_SendWorkRequest(uint32_t handle) override; void HW_LoadCalibration(uint32_t modules, uint32_t storage_cells) override; void HW_LoadIntegrationMap(uint32_t modules) override; + void HW_LoadInternalGeneratorFrame(uint32_t modules) override; void HW_GetStatus(ActionStatus *status) const override; void HLSMainThread() ; void RunFrameGenerator(const FrameGeneratorConfig& config); diff --git a/receiver/PCIExpressDevice.cpp b/receiver/PCIExpressDevice.cpp index 8c8ce5af..9be789fc 100644 --- a/receiver/PCIExpressDevice.cpp +++ b/receiver/PCIExpressDevice.cpp @@ -92,12 +92,6 @@ bool PCIExpressDevice::HW_SendWorkRequest(uint32_t handle) { } void PCIExpressDevice::FPGA_StartAction(const DiffractionExperiment &experiment) { - if (experiment.IsUsingInternalPacketGen()) { - if (ioctl(fd, IOCTL_JFJOCH_SET_INT_PKT, internal_pkt_gen_frame.data()) != 0) - throw JFJochException(JFJochExceptionCategory::PCIeError, - "Failed loading internal packet generator frame", errno); - } - if (ioctl(fd, IOCTL_JFJOCH_START) != 0) throw JFJochException(JFJochExceptionCategory::PCIeError, "Failed starting action", errno); @@ -222,12 +216,6 @@ std::string PCIExpressDevice::GetIPv4Address() const { return IPv4AddressToStr(tmp); } -void PCIExpressDevice::HW_ReadInternalPacketGen(uint16_t *tmp) const { - if (ioctl(fd, IOCTL_JFJOCH_GET_INT_PKT, tmp) != 0) - throw JFJochException(JFJochExceptionCategory::PCIeError, - "Failed getting internal packet generator frame", errno); -} - void PCIExpressDevice::HW_LoadCalibration(uint32_t in_modules, uint32_t in_storage_cells) { ActionConfig config{ .nmodules = in_modules, @@ -266,3 +254,12 @@ void PCIExpressDevice::WriteRegister(uint32_t addr, uint32_t val) { throw JFJochException(JFJochExceptionCategory::PCIeError, "Failed writing to register", errno); } + +void PCIExpressDevice::HW_LoadInternalGeneratorFrame(uint32_t in_modules) { + ActionConfig config{ + .nmodules = in_modules + }; + if (ioctl(fd, IOCTL_JFJOCH_LOAD_INT_GEN, &config) != 0) + throw JFJochException(JFJochExceptionCategory::PCIeError, "Failed uploading internal generator frame", errno); +} + diff --git a/receiver/PCIExpressDevice.h b/receiver/PCIExpressDevice.h index f8c1c84d..f2cd98c9 100644 --- a/receiver/PCIExpressDevice.h +++ b/receiver/PCIExpressDevice.h @@ -16,6 +16,7 @@ class PCIExpressDevice : public FPGAAcquisitionDevice { void HW_ReadActionRegister(ActionConfig *job) override; void HW_LoadCalibration(uint32_t modules, uint32_t storage_cells) override; void HW_LoadIntegrationMap(uint32_t modules) override; + void HW_LoadInternalGeneratorFrame(uint32_t modules) override; void FPGA_EndAction() override; void Reset(); @@ -31,7 +32,6 @@ public: void Cancel() override; void HW_GetStatus(ActionStatus *status) const override; void HW_GetEnvParams(ActionEnvParams *status) const override; - void HW_ReadInternalPacketGen(uint16_t *tmp) const; uint32_t GetNumKernelBuffers() const; int32_t GetNUMANode() const override; diff --git a/receiver/jfjoch_action_test.cpp b/receiver/jfjoch_action_test.cpp index 315f9b4f..74b9d5de 100644 --- a/receiver/jfjoch_action_test.cpp +++ b/receiver/jfjoch_action_test.cpp @@ -157,7 +157,7 @@ int main(int argc, char **argv) { for (int i = 0; i < nstreams; i++) { pcie_devices.push_back(std::make_unique(dev_name[i], i)); - pcie_devices[i]->SetCustomInternalGeneratorFrame(input); + pcie_devices[i]->SetInternalGeneratorFrame(input); pcie_devices[i]->EnableLogging(&logger); pcie_devices[i]->SetDefaultMAC(); pcie_devices[i]->SetIPv4Address((i << 24) + 0x010a0a0a); diff --git a/receiver/jfjoch_receiver.cpp b/receiver/jfjoch_receiver.cpp index 17303dad..d13c7df0 100644 --- a/receiver/jfjoch_receiver.cpp +++ b/receiver/jfjoch_receiver.cpp @@ -53,7 +53,7 @@ AcquisitionDevice *SetupAcquisitionDevice(const nlohmann::json &input, uint16_t auto filename = input["custom_test_frame"].get(); std::fstream file(filename.c_str(), std::fstream::in | std::fstream::binary); file.read((char *) tmp.data(), RAW_MODULE_SIZE * sizeof(uint16_t)); - pci_dev->SetCustomInternalGeneratorFrame(tmp); + pci_dev->SetInternalGeneratorFrame(tmp); } ret = pci_dev; } diff --git a/tests/FPGAIntegrationTest.cpp b/tests/FPGAIntegrationTest.cpp index b1ed2346..26c270e8 100644 --- a/tests/FPGAIntegrationTest.cpp +++ b/tests/FPGAIntegrationTest.cpp @@ -19,6 +19,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator", "[FPGA][Full]") { x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0); HLSSimulatedDevice test(0, 64); + test.SetInternalGeneratorFrame(); REQUIRE_NOTHROW(test.StartAction(x)); REQUIRE_NOTHROW(test.WaitForActionComplete()); @@ -55,7 +56,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_custom_frame", "[FPGA][Ful x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0); HLSSimulatedDevice test(0, 64); - test.SetCustomInternalGeneratorFrame(test_frame); + test.SetInternalGeneratorFrame(test_frame); REQUIRE_NOTHROW(test.StartAction(x)); REQUIRE_NOTHROW(test.WaitForActionComplete()); @@ -427,7 +428,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_convert_full_range", "[FPG } HLSSimulatedDevice test(0, 64); - + test.SetInternalGeneratorFrame(); REQUIRE_NOTHROW(test.InitializeCalibration(x, c)); REQUIRE_NOTHROW(test.StartAction(x)); REQUIRE_NOTHROW(test.WaitForActionComplete()); @@ -489,7 +490,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_apply_pixel_mask", "[FPGA] HLSSimulatedDevice test(0, 64); - test.SetCustomInternalGeneratorFrame(test_frame); + test.SetInternalGeneratorFrame(test_frame); REQUIRE_NOTHROW(test.InitializeCalibration(x, c)); REQUIRE_NOTHROW(test.StartAction(x)); @@ -855,7 +856,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_15_storage_cell_convert_G0 std::vector data(RAW_MODULE_SIZE); for (auto &i: data) i = 16000; - REQUIRE_NOTHROW(test.SetCustomInternalGeneratorFrame(data)); + REQUIRE_NOTHROW(test.SetInternalGeneratorFrame(data)); JFCalibration c(x); for (int i = 0; i < nstoragecells; i++) { @@ -903,7 +904,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_8_storage_cell_convert_G0" std::vector data(RAW_MODULE_SIZE); for (auto &i: data) i = 16000; - REQUIRE_NOTHROW(test.SetCustomInternalGeneratorFrame(data)); + REQUIRE_NOTHROW(test.SetInternalGeneratorFrame(data)); JFCalibration c(x); for (int i = 0; i < nstoragecells; i++) { @@ -951,7 +952,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_16_storage_cell_convert_G0 std::vector data(RAW_MODULE_SIZE); for (auto &i: data) i = 16000; - REQUIRE_NOTHROW(test.SetCustomInternalGeneratorFrame(data)); + REQUIRE_NOTHROW(test.SetInternalGeneratorFrame(data)); JFCalibration c(x); for (int i = 0; i < nstoragecells; i++) { @@ -991,7 +992,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_storage_cell_convert_G1", std::vector data(RAW_MODULE_SIZE); for (auto &i: data) i = 16384 | 10; - REQUIRE_NOTHROW(test.SetCustomInternalGeneratorFrame(data)); + REQUIRE_NOTHROW(test.SetInternalGeneratorFrame(data)); JFCalibration c(x); for (int i = 0; i < 16; i++) { @@ -1038,7 +1039,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_integration", "[FPGA][Full for (int i = 2; i < RAW_MODULE_SIZE; i++) frame[i] = 32754; - test.SetCustomInternalGeneratorFrame(frame); + test.SetInternalGeneratorFrame(frame); std::vector integration_map(nmodules * RAW_MODULE_SIZE, 54); for (int i = 0; i < RAW_MODULE_SIZE/2; i++) { diff --git a/tests/JFJochReceiverIntegrationTest.cpp b/tests/JFJochReceiverIntegrationTest.cpp index 82b9c648..bad52103 100644 --- a/tests/JFJochReceiverIntegrationTest.cpp +++ b/tests/JFJochReceiverIntegrationTest.cpp @@ -21,6 +21,7 @@ TEST_CASE("JFJochReceiverTest_Raw", "[JFJochReceiver]") { for (int i = 0; i < x.GetDataStreamsNum(); i++) { HLSSimulatedDevice *test; test = new HLSSimulatedDevice(i, 64); + test->SetInternalGeneratorFrame(); aq_devices.emplace_back(test); }