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build: no fused multiply-add contraction in device code either

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nvcc contracts a*b+c into an FMA by default, and decides it separately for every architecture it
compiles for. The same source therefore ran to different bits on a T4 (sm_75) and an RTX 5080
(sm_120), and a run that crossed a knife edge came out differently on the two machines: a rotation
set made again after a near-tie overturn merged with multiplicity 19.0 / R_meas 75.1% on the T4
server and 20.1 / 82.2% here, the delta-CC1/2 frame rejection removing 33 frames on one and 14 on
the other. A build here with only compute_75 code reproduced the server's numbers to the digit.

With --fmad=false for all CUDA sources the sm_75 and sm_120 builds give the same p.hkl on that set.
The host side has been built with -ffp-contract=off for the same reason; this extends it to the
device. Kernel time on a large HDF5 set: 48.3 -> 48.6 s (+0.7%), no measurable wall change.

This changes the bits of every GPU run, so every battery row moves; it is not an exact change.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01EizBKhTqrAYago9KJG3dA3
This commit is contained in:
leonarski_f
2026-10-13 07:40:28 +02:00
co-authored by Claude Opus 5.5
parent 5636208278
commit 7ed9705038
1 changed files with 6 additions and 1 deletions
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CMakeLists.txt
+6 -1
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@@ -47,11 +47,16 @@ ENDIF()
# came out differently from the same source and data. Off, every x86-64 level computes the same bits
# (measured: identical p.mtz on nine battery sets, no measurable time cost), and aarch64, where FMA is
# always there and GCC contracts by default, follows the same arithmetic. MSVC does not contract under
# its default /fp:precise. Host code of .cu sources gets it through nvcc; device code is not affected.
# its default /fp:precise. Host code of .cu sources gets it through nvcc.
IF (NOT MSVC)
ADD_COMPILE_OPTIONS($<$<COMPILE_LANGUAGE:C,CXX>:-ffp-contract=off>)
ADD_COMPILE_OPTIONS($<$<COMPILE_LANGUAGE:CUDA>:-Xcompiler=-ffp-contract=off>)
ENDIF()
# The same for device code. nvcc contracts by default and does it separately for every architecture
# it compiles for, so a T4 (sm_75) and an RTX 5080 (sm_120) ran the same kernels to different bits
# and a run that hit a knife edge came out differently on the two machines. Off, the architectures
# compute the same bits (measured: identical p.hkl from sm_75 and sm_120 builds, no measurable time cost).
ADD_COMPILE_OPTIONS($<$<COMPILE_LANGUAGE:CUDA>:--fmad=false>)
SET(JFJOCH_WRITER_ONLY OFF CACHE BOOL "Compile HDF5 writer only")
SET(JFJOCH_INSTALL_DRIVER_SOURCE OFF CACHE BOOL "Install kernel driver source (ignored if building writer only; necessary for RPM building)")