diff --git a/fpga/hls/load_calibration.cpp b/fpga/hls/load_calibration.cpp
index 5ff81bd0..5e72f199 100644
--- a/fpga/hls/load_calibration.cpp
+++ b/fpga/hls/load_calibration.cpp
@@ -49,16 +49,18 @@ int load_calibration(ap_uint<256> *d_hbm_p0,
 #pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
 		max_read_burst_length=2  max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
 
-	if (modules > MAX_MODULES_FPGA)
+	if ((modules == 0) || (modules > MAX_MODULES_FPGA))
 		return 1;
 
     if (destination == LOAD_CALIBRATION_DEST_CALIB) {
-        if (storage_cells > 16)
+        if ((storage_cells == 0) || (storage_cells > 16))
             return 1;
 
         for (int c = 0; c < 3; c++) {
             for (int m = 0; m < modules; m++) {
 #pragma HLS PIPELINE OFF
+                if (in_mem_location[c * modules + m] == 0)
+                    return 2;
                 setup_datamover(datamover_in_cmd, in_mem_location[c * modules + m], RAW_MODULE_SIZE * sizeof(int16_t));
                 size_t offset_hbm_0 = (2 * c) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
                 size_t offset_hbm_1 = (2 * c + 1) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
@@ -69,6 +71,8 @@ int load_calibration(ap_uint<256> *d_hbm_p0,
         for (int c = 0; c < 3; c++) {
             for (int m = 0; m < modules * storage_cells; m++) {
 #pragma HLS PIPELINE OFF
+                if (in_mem_location[3 * modules + c * modules * storage_cells + m] == 0)
+                    return 2;
                 setup_datamover(datamover_in_cmd, in_mem_location[3 * modules + c * modules * storage_cells + m],
                                 RAW_MODULE_SIZE * sizeof(int16_t));
                 size_t offset_hbm_0 = (6 + 2 * c) * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
@@ -81,6 +85,8 @@ int load_calibration(ap_uint<256> *d_hbm_p0,
         // load maps
         for (int m = 0; m < modules; m++) {
 #pragma HLS PIPELINE OFF
+            if (in_mem_location[m] == 0)
+                return 2;
             setup_datamover(datamover_in_cmd, in_mem_location[m], RAW_MODULE_SIZE * sizeof(int16_t));
             size_t offset_hbm_0 = 16 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
             size_t offset_hbm_1 = 17 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
@@ -89,6 +95,8 @@ int load_calibration(ap_uint<256> *d_hbm_p0,
         // load weights
         for (int m = 0; m < modules; m++) {
 #pragma HLS PIPELINE OFF
+            if (in_mem_location[modules + m] == 0)
+                return 2;
             setup_datamover(datamover_in_cmd, in_mem_location[modules + m], RAW_MODULE_SIZE * sizeof(int16_t));
             size_t offset_hbm_0 = 18 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
             size_t offset_hbm_1 = 19 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
@@ -97,6 +105,8 @@ int load_calibration(ap_uint<256> *d_hbm_p0,
     } else if (destination == LOAD_CALIBRATION_DEST_FRAME_GEN) {
         for (int m = 0; m < modules; m++) {
 #pragma HLS PIPELINE OFF
+            if (in_mem_location[m] == 0)
+                return 2;
             setup_datamover(datamover_in_cmd, in_mem_location[m], RAW_MODULE_SIZE * sizeof(int16_t));
             size_t offset_hbm_0 = 20 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;
             size_t offset_hbm_1 = 21 * hbm_size_bytes / 32 + m * RAW_MODULE_SIZE * sizeof(int16_t) / 64;