From 7a026b89d049e93bc3557499f437fe4fcdd9fc42 Mon Sep 17 00:00:00 2001
From: Filip Leonarski <filip.leonarski@psi.ch>
Date: Thu, 14 Sep 2023 23:48:02 +0200
Subject: [PATCH] FPGAIntegrationTest: Use blocking mode for one remaining test

---
 tests/FPGAIntegrationTest.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/FPGAIntegrationTest.cpp b/tests/FPGAIntegrationTest.cpp
index 0a862276..e6a481e4 100644
--- a/tests/FPGAIntegrationTest.cpp
+++ b/tests/FPGAIntegrationTest.cpp
@@ -961,7 +961,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_16_storage_cell_convert_G0
     REQUIRE(x.GetImageNum() == ntrigger * nstoragecells);
 
     HLSSimulatedDevice test(0, ntrigger * nstoragecells);
-
+    test.SetFPGANonBlockingMode(false);
     std::vector<double> tmp(3 * RAW_MODULE_SIZE, 50);
     JFModuleGainCalibration gain(tmp);