Version 1.0.0-rc.12

fpga/scripts/synth_hls_function.tcl

@@ -7,7 +7,9 @@ set_top $env(HLS_TOP_FUNCTION)
 add_files $env(SRC_DIR)/$env(HLS_FILE)
 
 if { [info exists ::env(HLS_TB_FILE)] } {
-    add_files -tb $env(SRC_DIR)/$env(HLS_TB_FILE)
+    if {$env(HLS_TB_FILE) != ""} {
+        add_files -tb $env(SRC_DIR)/$env(HLS_TB_FILE)
+    }
 }
 
 open_solution solution1
@@ -19,6 +21,12 @@ create_clock -period 3.2 -name default
 config_interface -m_axi_addr64=true
 config_schedule -enable_dsp_full_reg=true
 
+if { [info exists ::env(HLS_TB_FILE)] } {
+    if {$env(HLS_TB_FILE) != ""} {
+        csim_design
+    }
+}
+
 csynth_design
 
 config_export -vendor {psi.ch} -version 1.0 -ipname $env(HLS_TOP_FUNCTION) -format ip_catalog -rtl verilog