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FPGA: Spot finder 2nd version

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This commit is contained in:
leonarski_f
2023-10-03 22:11:21 +02:00
parent 81c1502d52
commit 5460c10f76
4 changed files with 237 additions and 61 deletions
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tests/FPGASpotFindingUnitTest.cpp
+64 -14
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@@ -158,7 +158,8 @@ bool Isigma_cpu(double val, double sum, double sum2, float threshold) {
}
bool Isigma_fpga(ap_int<16> val, ap_int<SUM_BITWIDTH> sum, ap_uint<SUM2_BITWIDTH> sum2, float threshold) {
return check_threshold(val, sum, sum2, fpga_strong_pixel_threshold(threshold), -1);
return check_threshold(val, sum, sum2, (FPGA_NBX *2 + 1) * (FPGA_NBX *2 + 1),
fpga_strong_pixel_threshold(threshold), -1);
}
TEST_CASE("FPGA_spot_check_threshold","[FPGA][SpotFinder]") {
@@ -183,7 +184,7 @@ TEST_CASE("FPGA_spot_check_threshold","[FPGA][SpotFinder]") {
TEST_CASE("FPGA_spot_finder_update_sum","[FPGA][SpotFinder]") {
STREAM_512 input;
STREAM_512 output;
hls::stream<spot_finder_packet> output;
hls::stream<ap_uint<(SUM_BITWIDTH*32)>> sum_out;
hls::stream<ap_uint<SUM2_BITWIDTH*32>> sum2_out;
@@ -264,13 +265,18 @@ TEST_CASE("FPGA_spot_finder_update_sum","[FPGA][SpotFinder]") {
}
TEST_CASE("FPGA_spot_finder_line_sum","[FPGA][SpotFinder]") {
STREAM_512 input;
STREAM_512 output;
hls::stream<spot_finder_packet> input;
hls::stream<spot_finder_packet> stream_0;
hls::stream<spot_finder_packet> output;
hls::stream<ap_uint<SUM_BITWIDTH*32>> sum_in;
hls::stream<ap_uint<SUM2_BITWIDTH*32>> sum2_in;
hls::stream<ap_uint<MASK_SUM_BITWIDTH*32>> valid_in;
hls::stream<ap_uint<SUM_BITWIDTH*32>> sum_stream;
hls::stream<ap_uint<SUM2_BITWIDTH*32>> sum2_stream;
hls::stream<ap_uint<MASK_SUM_BITWIDTH*32>> valid_stream;
hls::stream<ap_uint<SUM_BITWIDTH*32>> sum_out;
hls::stream<ap_uint<SUM2_BITWIDTH*32>> sum2_out;
hls::stream<ap_uint<MASK_SUM_BITWIDTH*32>> valid_out;
@@ -279,33 +285,77 @@ TEST_CASE("FPGA_spot_finder_line_sum","[FPGA][SpotFinder]") {
ap_int<SUM2_BITWIDTH> sum2_unpacked[32];
ap_int<MASK_SUM_BITWIDTH> valid_unpacked[32];
input << packet_512_t{.user = 0};
input << spot_finder_packet{.user = 0};
for (int i = 0; i < 32; i++)
input << packet_512_t{.data = 0, .user = 0};
input << spot_finder_packet{.data = 0, .user = 0};
input << packet_512_t{.user = 1};
input << spot_finder_packet{.user = 1};
for (int i = 0; i < 32; i++) {
for (int j = 0; j < 32; j++) {
sum_unpacked[j] = i * 32 + j;
sum2_unpacked[j] = 8934 + (i * 32 + j);
valid_unpacked[j] = i;
valid_unpacked[j] = 1;
}
sum_in << pack32(sum_unpacked);
sum2_in << pack32(sum2_unpacked);
valid_in << pack32(valid_unpacked);
}
spot_finder_line_sum(input, output, sum_in, sum2_in, valid_in, sum_out, sum2_out, valid_out);
spot_finder_line_sum(input, stream_0, sum_in, sum2_in, valid_in, sum_stream, sum2_stream, valid_stream);
REQUIRE(input.size() == 0);
REQUIRE(stream_0.size() == 32 + 2);
REQUIRE(sum_stream.size() == 33);
REQUIRE(sum2_stream.size() == 33);
REQUIRE(valid_stream.size() == 33);
spot_finder_line_sum_align(stream_0, output, sum_stream, sum2_stream, valid_stream, sum_out, sum2_out, valid_out);
REQUIRE(stream_0.size() == 0);
REQUIRE(output.size() == 32 + 2);
REQUIRE(sum_out.size() == 33);
REQUIRE(sum2_out.size() == 33);
REQUIRE(valid_out.size() == 33);
REQUIRE(sum_out.size() == 32);
REQUIRE(sum2_out.size() == 32);
REQUIRE(valid_out.size() == 32);
std::vector<int64_t> sum_output(RAW_MODULE_COLS);
std::vector<int64_t> sum2_output(RAW_MODULE_COLS);
std::vector<int64_t> valid_output(RAW_MODULE_COLS);
for (int i = 0; i < 32; i++) {
ap_uint<32 * SUM_BITWIDTH> sum_tmp;
sum_out >> sum_tmp;
unpack32(sum_tmp, sum_unpacked);
for (int j = 0; j < 32; j++)
sum_output[i * 32 + j] = sum_unpacked[j];
ap_uint<32 * SUM2_BITWIDTH> sum2_tmp;
sum2_out >> sum2_tmp;
unpack32(sum2_tmp, sum2_unpacked);
for (int j = 0; j < 32; j++)
sum2_output[i * 32 + j] = sum2_unpacked[j];
ap_uint<32 * MASK_SUM_BITWIDTH> valid_tmp;
valid_out >> valid_tmp;
unpack32(valid_tmp, valid_unpacked);
for (int j = 0; j < 32; j++)
valid_output[i * 32 + j] = valid_unpacked[j];
}
}
CHECK(sum_output[0] == sum_consecutive(0, FPGA_NBX+1));
CHECK(sum_output[1] == sum_consecutive(0, FPGA_NBX+2));
CHECK(sum_output[2] == sum_consecutive(0, FPGA_NBX+3));
CHECK(sum_output[FPGA_NBX] == sum_consecutive(0, FPGA_NBX*2+1));
CHECK(sum_output[FPGA_NBX+1] == sum_consecutive(1, FPGA_NBX*2+1));
CHECK(sum_output[FPGA_NBX+5] == sum_consecutive(5, FPGA_NBX*2+1));
CHECK(sum_output[1023] == sum_consecutive(1023-FPGA_NBX, FPGA_NBX+1));
CHECK(sum2_output[0] == sum_consecutive(8934, FPGA_NBX+1));
CHECK(valid_output[0] == FPGA_NBX+1);
CHECK(valid_output[1] == FPGA_NBX+2);
CHECK(valid_output[1022] == FPGA_NBX+2);
CHECK(valid_output[1023] == FPGA_NBX+1);
}