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Force CPU azimuthal integration in FPGA workflow

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Add AzimuthalIntegrationSettings::ForceCPUinFPGAWorkflow so the FPGA
data-acquisition path can compute azimuthal integration on the CPU instead
of the FPGA. This removes the FPGA bin-count limit (FPGA_INTEGRATION_BIN_COUNT)
and adds per-bin standard deviation.

- MXAnalysisAfterFPGA runs AzIntEngineCPU on the assembled image; the FPGA
  integration-map load and per-module read-back are skipped when forced.
- JFJochReceiverFPGA rejects bin counts above the FPGA limit at acquisition
  start (unless CPU is forced) with an actionable error.
- Wire force_cpu through the broker (both directions) and the frontend.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
leonarski_f
2026-06-15 16:43:48 +02:00
co-authored by Claude Opus 4.8
parent ea575f790a
commit 51451f167b
16 changed files with 255 additions and 19 deletions
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docs/python_client/docs/AzimIntSettings.md
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@@ -11,6 +11,7 @@ Name | Type | Description | Notes
**low_q_recip_a** | **float** | |
**q_spacing** | **float** | |
**azimuthal_bins** | **int** | Numer of azimuthal (phi) bins; 1 &#x3D; standard 1D azimuthal integration | [optional] [default to 1]
**force_cpu** | **bool** | Force CPU processing of azimuthal integration in the FPGA data acquisition workflow. This allows to extend number of azimuthal integration bins, as well as to calculate standard deviation of the azimuthal integration results. | [optional] [default to False]
## Example