From 3f3ce6f354ae5d5cd5bb7471ba2fa3f4936f1f56 Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Fri, 22 Sep 2023 20:31:16 +0200 Subject: [PATCH] FPGA: fix integration bug --- fpga/hls/integration.cpp | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/fpga/hls/integration.cpp b/fpga/hls/integration.cpp index a30d5665..68fc091a 100644 --- a/fpga/hls/integration.cpp +++ b/fpga/hls/integration.cpp @@ -20,19 +20,19 @@ void integration(STREAM_512 &data_in, #pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8 - ap_int<29> result[64][FPGA_INTEGRATION_BIN_COUNT]; + ap_int<30> sum[64][FPGA_INTEGRATION_BIN_COUNT]; // log2(32768*512*1024/64) = 28 + sign 1 bit -#pragma HLS BIND_STORAGE variable=result type=ram_t2p impl=bram -#pragma HLS ARRAY_PARTITION variable=result type=complete dim=1 - ap_uint<13> sum[64][FPGA_INTEGRATION_BIN_COUNT]; // log2(512*1024/64) = 13 #pragma HLS BIND_STORAGE variable=sum type=ram_t2p impl=bram #pragma HLS ARRAY_PARTITION variable=sum type=complete dim=1 + ap_uint<14> count[64][FPGA_INTEGRATION_BIN_COUNT]; // log2(512*1024/64) = 13 +#pragma HLS BIND_STORAGE variable=count type=ram_t2p impl=bram +#pragma HLS ARRAY_PARTITION variable=count type=complete dim=1 for (int j = 0; j < FPGA_INTEGRATION_BIN_COUNT; j++) { #pragma HLS PIPELINE II=1 for (int i = 0; i < 64; i++) { - result[i][j] = 0; sum[i][j] = 0; + count[i][j] = 0; } } @@ -57,15 +57,15 @@ void integration(STREAM_512 &data_in, for (int k = 0; k < 2; k++) { data_in >> packet_in; data_out << packet_in; - bins_0 = d_hbm_p0[offset_hbm_0 + cmpl.module * (RAW_MODULE_SIZE / 32 / 2) + i * 2 + k]; - bins_1 = d_hbm_p1[offset_hbm_1 + cmpl.module * (RAW_MODULE_SIZE / 32 / 2) + i * 2 + k]; + bins_0 = d_hbm_p0[offset_hbm_0 + cmpl.module * RAW_MODULE_SIZE * sizeof(int16_t) / 64 + i * 2 + k]; + bins_1 = d_hbm_p1[offset_hbm_1 + cmpl.module * RAW_MODULE_SIZE * sizeof(int16_t) / 64 + i * 2 + k]; unpack_2xhbm_to_32x16bit(bins_0, bins_1, in_bin); unpack32(packet_in.data, in_val); for (int j = 0; j < 32; j++) { if ((in_val[j] != INT16_MAX) && (in_val[j] != INT16_MIN) && (in_bin[j] < FPGA_INTEGRATION_BIN_COUNT)) { - result[k * 32 + j][in_bin[j]] += in_val[j]; - sum[k * 32 +j][in_bin[j]] += 1; + sum[k * 32 + j][in_bin[j]] += in_val[j]; + count[k * 32 + j][in_bin[j]] += 1; } } } @@ -76,16 +76,17 @@ void integration(STREAM_512 &data_in, ap_uint<512> val = 0; for (int k = 0; k < 4; k++) { - ap_int<35> main_result = 0; - ap_uint<19> main_sum = 0; + ap_int<64> main_sum = 0; + ap_int<64> main_count = 0; for (int j = 0; j < 64; j++) { - main_result += result[j][4 * i + k]; main_sum += sum[j][4 * i + k]; - + main_count += count[j][4 * i + k]; + sum[j][4 * i + k] = 0; + count[j][4 * i + k] = 0; } - val(128 * k + 34, 128 * k) = main_result; - val(128 * k + 18 + 64, 128 * k + 64) = main_sum; + val(128 * k + 63, 128 * k) = main_sum; + val(128 * k + 127, 128 * k + 64) = main_count; } result_out << val;