diff --git a/fpga/hls/host_writer.cpp b/fpga/hls/host_writer.cpp
index 83ebf926..6e0f0471 100644
--- a/fpga/hls/host_writer.cpp
+++ b/fpga/hls/host_writer.cpp
@@ -144,6 +144,7 @@ void host_writer(STREAM_512 &data_in,
 
     packet_512_t packet_in;
     data_in >> packet_in;
+    ap_uint<5> nmodules              = ACT_REG_NMODULES(packet_in.data);
     ap_uint<32> data_collection_mode = ACT_REG_MODE(packet_in.data);
     ap_uint<32> data_collection_id = data_collection_mode(31, 16); // upper 16-bit of mode
 
@@ -171,9 +172,9 @@ void host_writer(STREAM_512 &data_in,
         // Process one UDP packet per iteration
 #pragma HLS PIPELINE II=128
         ap_uint<64> frame_number = addr_frame_number(addr);
-        ap_uint<4> module = addr_module(addr);
+        ap_uint<4> module_number = addr_module(addr);
         ap_uint<7> eth_packet = addr_eth_packet(addr);
-        ap_uint<5> id = module * 2 + (frame_number % 2);
+        ap_uint<5> id = module_number * 2 + (frame_number % 2);
 
         if (curr_frame[id] != frame_number) {
             if (packet_mask[id] != 0) {
@@ -186,13 +187,16 @@ void host_writer(STREAM_512 &data_in,
                 ap_uint<64>  comp_bunchid      = jf_bunchid[id];
                 ap_uint<32>  comp_exptime      = exptime[id];
 
-                write_completion(m_axis_completion, comp_handle, module,
+                write_completion(m_axis_completion, comp_handle, module_number,
                                  comp_frame, comp_packet_mask, comp_packet_count,
                                  comp_debug, comp_timestamp, comp_bunchid,
                                  comp_exptime, data_collection_id);
             }
-
-            if (s_axis_work_request.empty() && mode_nonblocking) {
+            if (module_number >= nmodules) {
+                req_handle = HANDLE_SKIP_FRAME;
+                req_host_offset = 0;
+                internal_err_reg[5] = 1;
+            } else if (s_axis_work_request.empty() && mode_nonblocking) {
                 req_handle = HANDLE_SKIP_FRAME;
                 req_host_offset = 0;
             } else {
@@ -253,9 +257,9 @@ void host_writer(STREAM_512 &data_in,
         std::this_thread::sleep_for(std::chrono::milliseconds(100));
 #endif
 
-    for (ap_uint<8> m = 0; m < MAX_MODULES_FPGA * 2; m++) {
+    for (ap_uint<8> m = 0; m < nmodules * 2; m++) {
 #pragma HLS PIPELINE II=16
-        if (packet_mask[m] > 0)
+        if (packet_mask[m] != 0)
             write_completion(m_axis_completion, handle[m], m / 2, curr_frame[m],
                              packet_mask[m], packet_count[m],
                              debug[m], timestamp[m], jf_bunchid[m],