From 6e85a30930a733d4c36116a37bbd554794f94a42 Mon Sep 17 00:00:00 2001 From: leonarski_f Date: Sun, 28 Jan 2024 20:11:39 +0100 Subject: [PATCH] FPGA: Change FIFO size to improve placing --- fpga/scripts/jfjoch.tcl | 2 ++ fpga/scripts/mac_100g_pcie.tcl | 6 +++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/fpga/scripts/jfjoch.tcl b/fpga/scripts/jfjoch.tcl index 1bea0e48..2aca9982 100644 --- a/fpga/scripts/jfjoch.tcl +++ b/fpga/scripts/jfjoch.tcl @@ -242,6 +242,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { # Create instance: axis_eth_in_fifo, and set properties set axis_eth_in_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_eth_in_fifo ] set_property -dict [ list \ + CONFIG.FIFO_DEPTH {8192} \ + CONFIG.FIFO_MEMORY_TYPE {ultra} \ CONFIG.HAS_AEMPTY {1} \ CONFIG.HAS_AFULL {1} \ ] $axis_eth_in_fifo diff --git a/fpga/scripts/mac_100g_pcie.tcl b/fpga/scripts/mac_100g_pcie.tcl index 3ebf33e2..617acc61 100644 --- a/fpga/scripts/mac_100g_pcie.tcl +++ b/fpga/scripts/mac_100g_pcie.tcl @@ -57,7 +57,7 @@ proc create_hier_cell_mac_100g { parentCell nameHier } { # Create instance: axis_data_fifo_rx_0, and set properties set axis_data_fifo_rx_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_rx_0 ] set_property -dict [ list \ - CONFIG.FIFO_DEPTH {8192} \ + CONFIG.FIFO_DEPTH {2048} \ CONFIG.FIFO_MEMORY_TYPE {ultra} \ ] $axis_data_fifo_rx_0 @@ -73,8 +73,8 @@ proc create_hier_cell_mac_100g { parentCell nameHier } { # Create instance: axis_data_fifo_rx_2, and set properties set axis_data_fifo_rx_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_rx_2 ] set_property -dict [ list \ - CONFIG.FIFO_DEPTH {2048} \ - CONFIG.FIFO_MEMORY_TYPE {ultra} \ + CONFIG.FIFO_DEPTH {512} \ + CONFIG.FIFO_MEMORY_TYPE {block} \ ] $axis_data_fifo_rx_2 # Create instance: axis_data_fifo_tx, and set properties