From 0f7c14c2671b2f21ac59c72c4ff2d41715b02426 Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Mon, 25 Sep 2023 22:23:06 +0200 Subject: [PATCH] FPGA: integration calculates sum^2 --- fpga/hls/hls_jfjoch.h | 4 ++-- fpga/hls/host_writer.cpp | 24 +++++++------------ fpga/hls/integration.cpp | 42 ++++++++++++++++++++------------- receiver/AcquisitionDevice.h | 4 +++- receiver/HLSSimulatedDevice.cpp | 2 +- tests/FPGAIntegrationTest.cpp | 6 ++++- 6 files changed, 44 insertions(+), 38 deletions(-) diff --git a/fpga/hls/hls_jfjoch.h b/fpga/hls/hls_jfjoch.h index a59ff03f..85f25ed8 100644 --- a/fpga/hls/hls_jfjoch.h +++ b/fpga/hls/hls_jfjoch.h @@ -132,7 +132,7 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out, ap_uint<32> hbm_size_bytes); void host_writer(STREAM_512 &data_in, - hls::stream> &integration_in, + hls::stream> &integration_in, hls::stream &s_axis_completion, hls::stream > &host_memory_out, hls::stream &datamover_out_cmd, @@ -179,7 +179,7 @@ void stream_merge(AXI_STREAM &input_0, void integration(STREAM_512 &data_in, STREAM_512 &data_out, - hls::stream> &result_out, + hls::stream> &result_out, hls::stream &s_axis_completion, hls::stream &m_axis_completion, ap_uint<256> *d_hbm_p0, diff --git a/fpga/hls/host_writer.cpp b/fpga/hls/host_writer.cpp index 1ce49307..346d9c46 100644 --- a/fpga/hls/host_writer.cpp +++ b/fpga/hls/host_writer.cpp @@ -74,7 +74,7 @@ inline ap_uint<1> read_request(hls::stream > &s_axis_work_request, } void host_writer(STREAM_512 &data_in, - hls::stream> &integration_in, + hls::stream> &integration_in, hls::stream &s_axis_completion, hls::stream > &host_memory_out, hls::stream &datamover_out_cmd, @@ -125,8 +125,7 @@ void host_writer(STREAM_512 &data_in, while (!cmpl.last) { read_request(s_axis_work_request, req_handle, req_host_offset); setup_datamover(datamover_out_cmd, req_host_offset, RAW_MODULE_SIZE * sizeof(uint16_t) - + (FPGA_INTEGRATION_BIN_COUNT/4)*64 - + 64); + + (FPGA_INTEGRATION_BIN_COUNT)*64); packet_512_t packet_out; packet_out.strb = UINT64_MAX; @@ -143,23 +142,16 @@ void host_writer(STREAM_512 &data_in, host_memory_out << packet_out; } - for (int i = 0; i < FPGA_INTEGRATION_BIN_COUNT/4; i++) { + for (int i = 0; i < FPGA_INTEGRATION_BIN_COUNT; i++) { #pragma HLS PIPELINE II=1 - integration_in >> packet_out.data; + ap_uint<192> tmp; + integration_in >> tmp; + packet_out.data = tmp; + if (i == FPGA_INTEGRATION_BIN_COUNT - 1) + packet_out.last = 1; host_memory_out << packet_out; } - packet_out.last = 1; - packet_out.data = 0; - packet_out.data(63, 0) = cmpl.frame_number; - packet_out.data(127, 64) = cmpl.bunchid; - packet_out.data(195, 128) = cmpl.exptime; - packet_out.data(255, 196) = cmpl.timestamp; - packet_out.data(319, 256) = ap_uint<64>(cmpl.debug); - packet_out.data(383, 320) = ap_uint<64>(cmpl.module); - packet_out.data(447, 384) = ap_uint<64>(cmpl.packet_count); - host_memory_out << packet_out; - write_completion(m_axis_completion, req_handle, cmpl.module, diff --git a/fpga/hls/integration.cpp b/fpga/hls/integration.cpp index 2d22af86..ab6abcb4 100644 --- a/fpga/hls/integration.cpp +++ b/fpga/hls/integration.cpp @@ -4,7 +4,7 @@ void integration(STREAM_512 &data_in, STREAM_512 &data_out, - hls::stream> &result_out, + hls::stream> &result_out, hls::stream &s_axis_completion, hls::stream &m_axis_completion, ap_uint<256> *d_hbm_p0, @@ -30,10 +30,16 @@ void integration(STREAM_512 &data_in, #pragma HLS BIND_STORAGE variable=count type=ram_t2p impl=bram #pragma HLS ARRAY_PARTITION variable=count type=complete dim=1 + ap_uint<44> sum2[64][FPGA_INTEGRATION_BIN_COUNT]; + // log2(32768*32768*512*1024/64) = 43 +#pragma HLS BIND_STORAGE variable=sum2 type=ram_t2p impl=bram +#pragma HLS ARRAY_PARTITION variable=sum2 type=complete dim=1 + for (int j = 0; j < FPGA_INTEGRATION_BIN_COUNT; j++) { #pragma HLS PIPELINE II=1 for (int i = 0; i < 64; i++) { sum[i][j] = 0; + sum2[i][j] = 0; count[i][j] = 0; } } @@ -64,32 +70,34 @@ void integration(STREAM_512 &data_in, unpack32(packet_in.data, in_val); for (int j = 0; j < 32; j++) { + ap_uint<44> tmp = in_val[j] * in_val[j]; if ((in_val[j] != INT16_MAX) && (in_val[j] != INT16_MIN) && (in_bin[j] < FPGA_INTEGRATION_BIN_COUNT)) { sum[k * 32 + j][in_bin[j]] += in_val[j]; + sum2[k * 32 + j][in_bin[j]] += tmp; count[k * 32 + j][in_bin[j]] += 1; } } } } - for (int i = 0; i < FPGA_INTEGRATION_BIN_COUNT/4; i++) { -#pragma HLS PIPELINE II=4 - ap_uint<512> val = 0; + for (int i = 0; i < FPGA_INTEGRATION_BIN_COUNT; i++) { +#pragma HLS PIPELINE II=1 + ap_uint<192> val = 0; + ap_int<38> main_sum = 0; + ap_int<52> main_sum2 = 0; + ap_int<22> main_count = 0; + for (int j = 0; j < 64; j++) { + main_sum += sum[j][i]; + main_sum2 += sum2[j][i]; + main_count += count[j][i]; + sum[j][i] = 0; + sum2[j][i] = 0; + count[j][i] = 0; - for (int k = 0; k < 4; k++) { - ap_int<64> main_sum = 0; - ap_int<64> main_count = 0; - - for (int j = 0; j < 64; j++) { - main_sum += sum[j][4 * i + k]; - main_count += count[j][4 * i + k]; - sum[j][4 * i + k] = 0; - count[j][4 * i + k] = 0; - } - val(128 * k + 63, 128 * k) = main_sum; - val(128 * k + 127, 128 * k + 64) = main_count; } - + val(63, 0 ) = main_count; + val(127, 64) = main_sum; + val(191, 128) = main_sum2; result_out << val; } s_axis_completion >> cmpl; diff --git a/receiver/AcquisitionDevice.h b/receiver/AcquisitionDevice.h index 44fc7c9f..c82699e1 100644 --- a/receiver/AcquisitionDevice.h +++ b/receiver/AcquisitionDevice.h @@ -21,8 +21,10 @@ #include "Completion.h" struct IntegrationResult { - int64_t sum; int64_t count; + int64_t sum; + int64_t sum2; + int64_t reserved[5]; }; class AcquisitionDevice { diff --git a/receiver/HLSSimulatedDevice.cpp b/receiver/HLSSimulatedDevice.cpp index 67054b61..c69728d3 100644 --- a/receiver/HLSSimulatedDevice.cpp +++ b/receiver/HLSSimulatedDevice.cpp @@ -232,7 +232,7 @@ void HLSSimulatedDevice::HLSMainThread() { hls::stream compl0, compl1, compl2, compl3; hls::stream> hbm_handles; - hls::stream> integration_result; + hls::stream> integration_result; hls::stream > udp_metadata; ap_uint<1> idle_data_collection; diff --git a/tests/FPGAIntegrationTest.cpp b/tests/FPGAIntegrationTest.cpp index c0b1e0c8..b1ed2346 100644 --- a/tests/FPGAIntegrationTest.cpp +++ b/tests/FPGAIntegrationTest.cpp @@ -1063,14 +1063,18 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_integration", "[FPGA][Full auto integration_result = test.GetIntegrationResult(0, 0); CHECK(integration_result[0].sum == 32754LU * (RAW_MODULE_SIZE / 2 - 1)); + CHECK(integration_result[0].sum2 == 32754LU * 32754LU * (RAW_MODULE_SIZE / 2 - 1)); CHECK(integration_result[0].count == RAW_MODULE_SIZE / 2 - 1); CHECK(integration_result[1].sum == 0); + CHECK(integration_result[1].sum2 == 0); CHECK(integration_result[1].count == 0); CHECK(integration_result[FPGA_INTEGRATION_BIN_COUNT - 1].sum == 32754LU * (RAW_MODULE_SIZE / 2 - 2)); + CHECK(integration_result[FPGA_INTEGRATION_BIN_COUNT - 1].sum2 == 32754LU * 32754LU * (RAW_MODULE_SIZE / 2 - 2)); CHECK(integration_result[FPGA_INTEGRATION_BIN_COUNT - 1].count == RAW_MODULE_SIZE / 2 - 2); integration_result = test.GetIntegrationResult(0, 1); - CHECK(integration_result[54].sum == 32754 * (RAW_MODULE_SIZE - 2)); + CHECK(integration_result[54].sum == 32754LU * (RAW_MODULE_SIZE - 2)); + CHECK(integration_result[54].sum2 == 32754LU * 32754LU * (RAW_MODULE_SIZE - 2)); CHECK(integration_result[54].count == RAW_MODULE_SIZE - 2); integration_result = test.GetIntegrationResult(0, 2);