From 05000bab1fe3df548d606807e6fa0ce427c9b57f Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Mon, 11 Sep 2023 20:16:35 +0200 Subject: [PATCH] FPGA: remove transfer to HBM for the time being --- fpga/hls/CMakeLists.txt | 16 +-- fpga/hls/save_to_hbm.cpp | 210 -------------------------------- fpga/hls/transfer_hbm.cpp | 53 -------- fpga/hls/writer_split.cpp | 53 -------- fpga/scripts/bd_pcie.tcl | 7 -- fpga/scripts/jfjoch.tcl | 125 ++----------------- receiver/HLSSimulatedDevice.cpp | 63 +--------- receiver/HLSSimulatedDevice.h | 2 - tests/FPGAIntegrationTest.cpp | 79 ------------ 9 files changed, 12 insertions(+), 596 deletions(-) delete mode 100644 fpga/hls/save_to_hbm.cpp delete mode 100644 fpga/hls/transfer_hbm.cpp delete mode 100644 fpga/hls/writer_split.cpp diff --git a/fpga/hls/CMakeLists.txt b/fpga/hls/CMakeLists.txt index 22067450..098f9084 100644 --- a/fpga/hls/CMakeLists.txt +++ b/fpga/hls/CMakeLists.txt @@ -12,11 +12,7 @@ ADD_LIBRARY( HLSSimulation STATIC icmp.cpp arp.cpp ip_header_checksum.h udp.cpp - sls_detector.cpp - save_to_hbm.cpp - writer_split.cpp - transfer_hbm.cpp - load_from_hbm.cpp) + sls_detector.cpp) TARGET_INCLUDE_DIRECTORIES(HLSSimulation PUBLIC ../include) TARGET_LINK_LIBRARIES(HLSSimulation CommonFunctions) @@ -49,10 +45,6 @@ MAKE_HLS_MODULE(ethernet.cpp ethernet) MAKE_HLS_MODULE(arp.cpp arp) MAKE_HLS_MODULE(udp.cpp udp) MAKE_HLS_MODULE(sls_detector.cpp sls_detector) -MAKE_HLS_MODULE(save_to_hbm.cpp save_to_hbm) -MAKE_HLS_MODULE(writer_split.cpp writer_split) -MAKE_HLS_MODULE(transfer_hbm.cpp transfer_hbm) -MAKE_HLS_MODULE(load_from_hbm.cpp load_from_hbm) SET (HLS_IPS psi_ch_hls_data_collection_fsm_1_0.zip psi_ch_hls_timer_host_1_0.zip @@ -66,11 +58,7 @@ SET (HLS_IPS psi_ch_hls_data_collection_fsm_1_0.zip psi_ch_hls_udp_1_0.zip psi_ch_hls_sls_detector_1_0.zip psi_ch_hls_icmp_1_0.zip - psi_ch_hls_host_writer_1_0.zip - psi_ch_hls_save_to_hbm_1_0.zip - psi_ch_hls_load_from_hbm_1_0.zip - psi_ch_hls_writer_split_1_0.zip - psi_ch_hls_transfer_hbm_1_0.zip) + psi_ch_hls_host_writer_1_0.zip) SET (HLS_IPS ${HLS_IPS} PARENT_SCOPE) ADD_CUSTOM_TARGET(hls DEPENDS ${HLS_IPS}) diff --git a/fpga/hls/save_to_hbm.cpp b/fpga/hls/save_to_hbm.cpp deleted file mode 100644 index c44e4dce..00000000 --- a/fpga/hls/save_to_hbm.cpp +++ /dev/null @@ -1,210 +0,0 @@ -// Copyright (2019-2022) Paul Scherrer Institute -// SPDX-License-Identifier: CERN-OHL-S-2.0 or GPL-3.0-or-later - -#include "hls_jfjoch.h" - -#ifndef __SYNTHESIS__ -#include -#endif - -#define PACKET_SIZE 8192 - -inline void write_completion(hls::stream &m_axis_completion, - const ap_uint<32> &handle, - const ap_uint<5> &module_number, - const ap_uint<64> &frame_num, - const ap_uint<128> &packet_mask, - const ap_uint<16> &packet_count, - const ap_uint<32> &debug, - const ap_uint<64> ×tamp, - const ap_uint<64> &bunchid, - const ap_uint<32> &exptime, - const ap_uint<32> &data_collection_id, - const ap_uint<1> &flushing) { -#pragma HLS INLINE - axis_completion cmpl; - cmpl.handle = handle; - cmpl.module = module_number; - cmpl.frame_number = frame_num; - cmpl.packet_mask = packet_mask; - cmpl.packet_count = packet_count; - cmpl.debug = debug; - cmpl.timestamp = timestamp; - cmpl.bunchid = bunchid; - cmpl.exptime = exptime; - cmpl.data_collection_id = data_collection_id; - cmpl.flushing = flushing; - cmpl.last = 0; -} - -void save_to_hbm(STREAM_512 &data_in, - hls::stream &addr_in, - hls::stream &completion_out, - hls::burst_maxi d_hbm_p0, hls::burst_maxi d_hbm_p1, - volatile uint64_t &packets_processed, - volatile ap_uint<1> &idle, - ap_uint<8> &err_reg) { -#pragma HLS INTERFACE ap_ctrl_none port=return -#pragma HLS INTERFACE register both axis port=data_in -#pragma HLS INTERFACE register both axis port=addr_in -#pragma HLS INTERFACE register both axis port=completion_out -#pragma HLS INTERFACE register ap_vld port=packets_processed -#pragma HLS INTERFACE register ap_vld port=err_reg -#pragma HLS INTERFACE register ap_none port=idle - -#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \ - max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 -#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \ - max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2 - - ap_uint<128> packet_mask[MAX_MODULES_FPGA*2]; -#pragma HLS RESOURCE variable=packet_mask core=RAM_1P - ap_uint<16> packet_count[MAX_MODULES_FPGA*2]; -#pragma HLS RESOURCE variable=packet_count core=RAM_1P - ap_uint<32> handle[MAX_MODULES_FPGA*2]; -#pragma HLS RESOURCE variable=handle core=RAM_1P - ap_uint<64> curr_frame[MAX_MODULES_FPGA*2]; -#pragma HLS RESOURCE variable=curr_frame core=RAM_1P - ap_uint<32> debug[MAX_MODULES_FPGA*2]; -#pragma HLS RESOURCE variable=debug core=RAM_1P - ap_uint<64> timestamp[MAX_MODULES_FPGA*2]; -#pragma HLS RESOURCE variable=timestamp core=RAM_1P - ap_uint<32> exptime[MAX_MODULES_FPGA*2]; -#pragma HLS RESOURCE variable=exptime core=RAM_1P - ap_uint<64> jf_bunchid[MAX_MODULES_FPGA*2]; -#pragma HLS RESOURCE variable=jf_bunchid core=RAM_1P - - idle = 1; - - for (int i = 0; i < MAX_MODULES_FPGA*2; i++) { -#pragma HLS UNROLL - curr_frame[i] = UINT64_MAX; - handle[i] = 0; - packet_mask[i] = 0; - packet_count[i] = 0; - debug[i] = 0; - timestamp[i] = 0; - exptime[i] = 0; - jf_bunchid[i] = 0; - } - - uint32_t handle_val = 0; - - axis_addr addr; - addr_in >> addr; - - packet_512_t packet_in; - data_in >> packet_in; - - ap_uint<5> nmodules = ACT_REG_NMODULES(packet_in.data); - ap_uint<32> data_collection_mode = ACT_REG_MODE(packet_in.data); - ap_uint<32> data_collection_id = data_collection_mode(31, 16); // upper 16-bit of mode - ap_uint<32> hbm_size_256b = ACT_REG_HBM_SIZE_256b(packet_in.data); - ap_uint<32> offset_hbm_0 = 12 * hbm_size_256b; - ap_uint<32> offset_hbm_1 = 14 * hbm_size_256b; - ap_uint<32> hbm_size = hbm_size_256b * 32 * 2 / (RAW_MODULE_SIZE * 2); - - ap_uint<1> mode_nonblocking = (data_collection_mode & MODE_NONBLOCKING_ON_WR) ? 1 : 0; - - ap_uint<8> internal_err_reg = 0; - err_reg = internal_err_reg; - - idle = 0; - uint64_t total_counter = 0; - packets_processed = 0; - addr_in >> addr; - - Loop_good_packet: - while (!addr.last) { - // Process one UDP packet per iteration -#pragma HLS PIPELINE II=128 - ap_uint<64> frame_number = addr.frame_number; - ap_uint<4> module_number = addr.module; - ap_uint<7> eth_packet = addr.eth_packet; - ap_uint<5> id = module_number * 2 + (frame_number % 2); - - if (curr_frame[id] != frame_number) { - if (packet_mask[id] != 0) { - ap_uint<32> comp_handle = handle[id]; - ap_uint<64> comp_frame = curr_frame[id]; - ap_uint<256> comp_packet_mask = packet_mask[id]; - ap_uint<16> comp_packet_count = packet_count[id]; - ap_uint<32> comp_debug = debug[id]; - ap_uint<64> comp_timestamp = timestamp[id]; - ap_uint<64> comp_bunchid = jf_bunchid[id]; - ap_uint<32> comp_exptime = exptime[id]; - - write_completion(completion_out, comp_handle, module_number, - comp_frame, comp_packet_mask, comp_packet_count, - comp_debug, comp_timestamp, comp_bunchid, - comp_exptime, data_collection_id, 0); - } - - handle[id] = handle_val; - curr_frame[id] = frame_number; - - debug[id] = addr.debug; - timestamp[id] = addr.timestamp; - jf_bunchid[id] = addr.bunchid; - exptime[id] = addr.exptime; - - packet_mask[id] = ap_uint<128>(1) << eth_packet; - packet_count[id] = 1; - - if (hbm_size == 1024) - handle_val = (handle_val + 1) % 1024; - else if (hbm_size == 512) - handle_val = (handle_val + 1) % 512; - else if (hbm_size == 64) - handle_val = (handle_val + 1) % 64; - else - handle_val = (handle_val + 1) % 32; - - } else { - packet_count[id]++; - packet_mask[id] |= ap_uint<128>(1) << eth_packet; - } - - size_t out_frame_addr = (handle[id] * 128 + eth_packet) * 128; - - for (int i = 0; i < 128; i++) { - if (i % 16 == 0) { - d_hbm_p0.write_request(offset_hbm_0 + out_frame_addr + i, 16); - d_hbm_p1.write_request(offset_hbm_1 + out_frame_addr + i, 16); - } - - data_in >> packet_in; - d_hbm_p0.write(packet_in.data(255, 0)); - d_hbm_p1.write(packet_in.data(511, 256)); - - if (i % 16 == 15) { - d_hbm_p0.write_response(); - d_hbm_p1.write_response(); - } - } - if (packet_in.last != 1) - internal_err_reg[1] = 1; - - total_counter++; - packets_processed = total_counter; - addr_in >> addr; - err_reg = internal_err_reg; - } - - for (ap_uint<8> m = 0; m < nmodules * 2; m++) { -#pragma HLS PIPELINE II=16 - if (packet_mask[m] != 0) - write_completion(completion_out, handle[m], m / 2, curr_frame[m], - packet_mask[m], packet_count[m], - debug[m], timestamp[m], jf_bunchid[m], - exptime[m], data_collection_id, 1); - } - - data_in >> packet_in; - - axis_completion cmpl; - cmpl.last = 1; - completion_out << cmpl; - - idle = 1; -} diff --git a/fpga/hls/transfer_hbm.cpp b/fpga/hls/transfer_hbm.cpp deleted file mode 100644 index 66955206..00000000 --- a/fpga/hls/transfer_hbm.cpp +++ /dev/null @@ -1,53 +0,0 @@ -// Copyright (2019-2023) Paul Scherrer Institute -// SPDX-License-Identifier: GPL-3.0-or-later - -#include "hls_jfjoch.h" - -void transfer_hbm(ap_uint<256> *d_hbm_p0, - ap_uint<256> *uram, - uint32_t hbm_offset, - bool hbm_to_uram, - uint8_t stride, - uint8_t uram_offset) { -#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \ - max_read_burst_length=16 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=9 -#pragma HLS INTERFACE m_axi port=uram bundle=uram depth=512 offset=off \ - max_read_burst_length=16 max_write_burst_length=16 latency=8 num_write_outstanding=2 num_read_outstanding=2 -#pragma HLS interface s_axilite port=hbm_offset -#pragma HLS interface s_axilite port=hbm_to_uram -#pragma HLS interface s_axilite port=stride -#pragma HLS interface s_axilite port=uram_offset -#pragma HLS INTERFACE s_axilite port=return - - if ((stride != 1) && (stride != 2)) - return; - - if (uram_offset >= stride) - return; - - if (stride == 2) { - if (hbm_to_uram) { - for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 32 / 2; i++) { -#pragma HLS PIPELINE II=1 - uram[2 * i + uram_offset] = d_hbm_p0[hbm_offset + i]; - } - } else { - for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 32 / 2; i++) { -#pragma HLS PIPELINE II=1 - d_hbm_p0[hbm_offset + i] = uram[2 * i + uram_offset]; - } - } - } else { - if (hbm_to_uram) { - for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 32; i++) { -#pragma HLS PIPELINE II=1 - uram[i + uram_offset] = d_hbm_p0[hbm_offset + i]; - } - } else { - for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 32; i++) { -#pragma HLS PIPELINE II=1 - d_hbm_p0[hbm_offset + i] = uram[i + uram_offset]; - } - } - } -} diff --git a/fpga/hls/writer_split.cpp b/fpga/hls/writer_split.cpp deleted file mode 100644 index f16e3f87..00000000 --- a/fpga/hls/writer_split.cpp +++ /dev/null @@ -1,53 +0,0 @@ -// Copyright (2019-2023) Paul Scherrer Institute -// SPDX-License-Identifier: GPL-3.0-or-later - -#include "hls_jfjoch.h" - -void writer_split(STREAM_512 &data_in, - STREAM_512 &data_out_1, - STREAM_512 &data_out_2, - hls::stream &addr_in, - hls::stream &addr_out_1, - hls::stream &addr_out_2) { -#pragma HLS INTERFACE register both axis port=data_in -#pragma HLS INTERFACE register both axis port=data_out_1 -#pragma HLS INTERFACE register both axis port=data_out_2 - -#pragma HLS INTERFACE register both axis port=addr_in -#pragma HLS INTERFACE register both axis port=addr_out_1 -#pragma HLS INTERFACE register both axis port=addr_out_2 - -#pragma HLS INTERFACE ap_ctrl_none port=return - packet_512_t packet; - axis_addr addr; - - addr_in >> addr; - addr_out_1 << addr; - addr_out_2 << addr; - - data_in >> packet; - data_out_1 << packet; - data_out_2 << packet; - - addr_in >> addr; - addr_out_1 << addr; - addr_out_2 << addr; - - Loop_good_packet: - while (!addr.last) { -#pragma HLS PIPELINE II=128 - for (int i = 0; i < 128; i++) { - data_in >> packet; - data_out_1 << packet; - data_out_2 << packet; - } - addr_in >> addr; - addr_out_1 << addr; - addr_out_2 << addr; - } - - data_in >> packet; - data_out_1 << packet; - data_out_2 << packet; -} - diff --git a/fpga/scripts/bd_pcie.tcl b/fpga/scripts/bd_pcie.tcl index b08632ea..f679a389 100644 --- a/fpga/scripts/bd_pcie.tcl +++ b/fpga/scripts/bd_pcie.tcl @@ -393,10 +393,6 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p9 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_9] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p9] connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p10 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_10] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p10] connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p11 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_11] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p11] - connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p12 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_12] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p12] - connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p13 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_13] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p13] - connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p14 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_14] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p14] - connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p15 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_15] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p15] connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_data [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_data] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_data] connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_cmd] connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_h2c_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_h2c_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_h2c_cmd] @@ -446,12 +442,9 @@ proc create_root_design { parentCell } { assign_bd_address -offset 0x00060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_calibration_addr/S_AXI/Mem0] -force assign_bd_address -offset 0x00070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/axi_firewall_0/S_AXI_CTL/Control] -force assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/xdma_0/S_AXI_LITE/CTL0] -force - assign_bd_address -offset 0x000A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/transfer_hbm_0/s_axi_control/Reg] -force assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_0/S_AXI/Mem0] -force - assign_bd_address -offset 0x00200000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_hbm_transfer_1/S_AXI/Mem0] -force assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jungfraujoch_0/internal_packet_generator_0/Data_m_axi_frame] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_1/S_AXI/Mem0] -force - assign_bd_address -offset 0x00200000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jungfraujoch_0/transfer_hbm_0/Data_m_axi_uram] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_hbm_transfer_0/S_AXI/Mem0] -force assign_bd_address diff --git a/fpga/scripts/jfjoch.tcl b/fpga/scripts/jfjoch.tcl index 28c24353..e81593ab 100644 --- a/fpga/scripts/jfjoch.tcl +++ b/fpga/scripts/jfjoch.tcl @@ -4,10 +4,10 @@ # Hierarchical cell: jungfraujoch proc create_hier_cell_jungfraujoch { parentCell nameHier } { - variable script_folder + variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_jungfraujoch() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_jungfraujoch_0() - Empty argument(s)!"} return } @@ -64,14 +64,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p11 - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p12 - - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p13 - - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p14 - - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_d_hbm_p15 - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_c2h_data create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_c2h_datamover_cmd @@ -111,24 +103,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { CONFIG.SINGLE_PORT_BRAM {1} \ ] $axi_bram_ctrl_calibration_addr - # Create instance: axi_bram_ctrl_hbm_transfer_0, and set properties - set axi_bram_ctrl_hbm_transfer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_hbm_transfer_0 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - CONFIG.PROTOCOL {AXI4} \ - CONFIG.READ_LATENCY {1} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_hbm_transfer_0 - - # Create instance: axi_bram_ctrl_hbm_transfer_1, and set properties - set axi_bram_ctrl_hbm_transfer_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_hbm_transfer_1 ] - set_property -dict [ list \ - CONFIG.DATA_WIDTH {256} \ - CONFIG.PROTOCOL {AXI4} \ - CONFIG.READ_LATENCY {1} \ - CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_hbm_transfer_1 - # Create instance: axi_bram_ctrl_internal_packet_generator_0, and set properties set axi_bram_ctrl_internal_packet_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_internal_packet_generator_0 ] set_property -dict [ list \ @@ -172,24 +146,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { CONFIG.HAS_AFULL {1} \ ] $axis_addr_fifo_2 - # Create instance: axis_addr_fifo_3, and set properties - set axis_addr_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_addr_fifo_3 ] - set_property -dict [ list \ - CONFIG.FIFO_DEPTH {16} \ - CONFIG.FIFO_MEMORY_TYPE {block} \ - CONFIG.HAS_AEMPTY {0} \ - CONFIG.HAS_AFULL {0} \ - ] $axis_addr_fifo_3 - - # Create instance: axis_addr_fifo_4, and set properties - set axis_addr_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_addr_fifo_4 ] - set_property -dict [ list \ - CONFIG.FIFO_DEPTH {16} \ - CONFIG.FIFO_MEMORY_TYPE {block} \ - CONFIG.HAS_AEMPTY {0} \ - CONFIG.HAS_AFULL {0} \ - ] $axis_addr_fifo_4 - # Create instance: axis_data_fifo_0, and set properties set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ] set_property -dict [ list \ @@ -236,18 +192,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { CONFIG.HAS_AFULL {1} \ ] $axis_data_fifo_5 - # Create instance: axis_data_fifo_6, and set properties - set axis_data_fifo_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_6 ] - set_property -dict [ list \ - CONFIG.FIFO_DEPTH {4096} \ - ] $axis_data_fifo_6 - - # Create instance: axis_data_fifo_7, and set properties - set axis_data_fifo_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_7 ] - set_property -dict [ list \ - CONFIG.FIFO_DEPTH {4096} \ - ] $axis_data_fifo_7 - # Create instance: axis_data_fifo_c2h_cmd, and set properties set axis_data_fifo_c2h_cmd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_c2h_cmd ] set_property -dict [ list \ @@ -375,26 +319,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { # Create instance: data_collection_fsm_0, and set properties set data_collection_fsm_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:data_collection_fsm:1.0 data_collection_fsm_0 ] - # Create instance: hbm_transfer_uram, and set properties - set hbm_transfer_uram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 hbm_transfer_uram ] - set_property -dict [ list \ - CONFIG.Assume_Synchronous_Clk {true} \ - CONFIG.EN_SAFETY_CKT {false} \ - CONFIG.Enable_B {Use_ENB_Pin} \ - CONFIG.Memory_Type {True_Dual_Port_RAM} \ - CONFIG.Operating_Mode_A {NO_CHANGE} \ - CONFIG.Operating_Mode_B {NO_CHANGE} \ - CONFIG.PRIM_type_to_Implement {URAM} \ - CONFIG.Port_A_Write_Rate {50} \ - CONFIG.Port_B_Clock {100} \ - CONFIG.Port_B_Enable_Rate {100} \ - CONFIG.Port_B_Write_Rate {50} \ - CONFIG.Read_Width_B {256} \ - CONFIG.Use_Byte_Write_Enable {true} \ - CONFIG.Use_RSTB_Pin {true} \ - CONFIG.Write_Width_B {256} \ - ] $hbm_transfer_uram - # Create instance: host_writer_0, and set properties set host_writer_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:host_writer:1.0 host_writer_0 ] @@ -438,12 +362,6 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { # Create instance: network_stack create_hier_cell_network_stack $hier_obj network_stack - # Create instance: one, and set properties - set one [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one ] - - # Create instance: save_to_hbm_0, and set properties - set save_to_hbm_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:save_to_hbm:1.0 save_to_hbm_0 ] - # Create instance: smartconnect_0, and set properties set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] set_property -dict [ list \ @@ -452,43 +370,28 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { CONFIG.NUM_SI {1} \ ] $smartconnect_0 - # Create instance: smartconnect_1, and set properties - set smartconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_1 ] - # Create instance: timer_hbm_0, and set properties set timer_hbm_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:timer_hbm:1.0 timer_hbm_0 ] # Create instance: timer_host_0, and set properties set timer_host_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:timer_host:1.0 timer_host_0 ] - # Create instance: transfer_hbm_0, and set properties - set transfer_hbm_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:transfer_hbm:1.0 transfer_hbm_0 ] - - # Create instance: writer_split_0, and set properties - set writer_split_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:writer_split:1.0 writer_split_0 ] - # Create interface connections connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins eth_out] [get_bd_intf_pins network_stack/M00_AXIS] connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins eth_in] [get_bd_intf_pins network_stack/eth_in] connect_bd_intf_net -intf_net S_AXIS_1 [get_bd_intf_pins s_axis_h2c_data] [get_bd_intf_pins axis_data_fifo_h2c_data/S_AXIS] connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_calibration_addr/BRAM_PORTA] [get_bd_intf_pins calibration_addr_bram/BRAM_PORTB] - connect_bd_intf_net -intf_net axi_bram_ctrl_hbm_transfer_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_hbm_transfer_0/BRAM_PORTA] [get_bd_intf_pins hbm_transfer_uram/BRAM_PORTB] - connect_bd_intf_net -intf_net axi_bram_ctrl_hbm_transfer_1_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_hbm_transfer_1/BRAM_PORTA] [get_bd_intf_pins hbm_transfer_uram/BRAM_PORTA] connect_bd_intf_net -intf_net axi_bram_ctrl_internal_packet_generator_1_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_1/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTB] connect_bd_intf_net -intf_net axi_bram_ctrl_internal_packet_generator_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_0/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTA] connect_bd_intf_net -intf_net axis_addr_fifo_0_M_AXIS [get_bd_intf_pins axis_addr_fifo_0/M_AXIS] [get_bd_intf_pins internal_packet_generator_0/addr_in] connect_bd_intf_net -intf_net axis_addr_fifo_2_M_AXIS [get_bd_intf_pins axis_addr_fifo_1/M_AXIS] [get_bd_intf_pins jf_conversion_0/addr_in] - connect_bd_intf_net -intf_net axis_addr_fifo_2_M_AXIS1 [get_bd_intf_pins axis_addr_fifo_2/M_AXIS] [get_bd_intf_pins writer_split_0/addr_in] - connect_bd_intf_net -intf_net axis_addr_fifo_3_M_AXIS1 [get_bd_intf_pins axis_addr_fifo_3/M_AXIS] [get_bd_intf_pins save_to_hbm_0/addr_in] - connect_bd_intf_net -intf_net axis_addr_fifo_4_M_AXIS [get_bd_intf_pins axis_addr_fifo_4/M_AXIS] [get_bd_intf_pins host_writer_0/addr_in] + connect_bd_intf_net -intf_net axis_addr_fifo_2_M_AXIS1 [get_bd_intf_pins axis_addr_fifo_2/M_AXIS] [get_bd_intf_pins host_writer_0/addr_in] connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins load_calibration_0/data_in] connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins internal_packet_generator_0/data_in] connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins axis_data_fifo_2/M_AXIS] [get_bd_intf_pins timer_hbm_0/data_in] connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins axis_data_fifo_3/M_AXIS] [get_bd_intf_pins jf_conversion_0/data_in] connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS1 [get_bd_intf_pins axis_data_fifo_4/M_AXIS] [get_bd_intf_pins timer_host_0/data_in] - connect_bd_intf_net -intf_net axis_data_fifo_5_M_AXIS [get_bd_intf_pins axis_data_fifo_5/M_AXIS] [get_bd_intf_pins writer_split_0/data_in] - connect_bd_intf_net -intf_net axis_data_fifo_6_M_AXIS [get_bd_intf_pins axis_data_fifo_6/M_AXIS] [get_bd_intf_pins save_to_hbm_0/data_in] - connect_bd_intf_net -intf_net axis_data_fifo_7_M_AXIS [get_bd_intf_pins axis_data_fifo_7/M_AXIS] [get_bd_intf_pins host_writer_0/data_in] + connect_bd_intf_net -intf_net axis_data_fifo_5_M_AXIS [get_bd_intf_pins axis_data_fifo_5/M_AXIS] [get_bd_intf_pins host_writer_0/data_in] connect_bd_intf_net -intf_net axis_data_fifo_c2h_cmd_M_AXIS [get_bd_intf_pins m_axis_c2h_datamover_cmd] [get_bd_intf_pins axis_data_fifo_c2h_cmd/M_AXIS] connect_bd_intf_net -intf_net axis_data_fifo_c2h_data_M_AXIS [get_bd_intf_pins m_axis_c2h_data] [get_bd_intf_pins axis_data_fifo_c2h_data/M_AXIS] connect_bd_intf_net -intf_net axis_data_fifo_h2c_cmd_M_AXIS [get_bd_intf_pins m_axis_h2c_datamover_cmd] [get_bd_intf_pins axis_data_fifo_h2c_cmd/M_AXIS] @@ -514,7 +417,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_intf_net -intf_net internal_packet_generator_0_m_axi_frame [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_1/S_AXI] [get_bd_intf_pins internal_packet_generator_0/m_axi_frame] connect_bd_intf_net -intf_net jf_conversion_0_addr_out [get_bd_intf_pins axis_register_slice_addr_1/S_AXIS] [get_bd_intf_pins jf_conversion_0/addr_out] connect_bd_intf_net -intf_net jf_conversion_0_data_out [get_bd_intf_pins axis_data_fifo_4/S_AXIS] [get_bd_intf_pins jf_conversion_0/data_out] - connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p0 [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/S00_AXI] + connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p0 [get_bd_intf_pins m_axi_d_hbm_p0] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p0] connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p1] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p1] connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p2 [get_bd_intf_pins m_axi_d_hbm_p2] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p2] connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p3 [get_bd_intf_pins m_axi_d_hbm_p3] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p3] @@ -533,23 +436,12 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_intf_net -intf_net network_stack_udp_addr_out [get_bd_intf_pins axis_udp_addr_fifo_0/S_AXIS] [get_bd_intf_pins network_stack/udp_addr_out] connect_bd_intf_net -intf_net network_stack_udp_out [get_bd_intf_pins axis_udp_fifo_0/S_AXIS] [get_bd_intf_pins network_stack/udp_out] connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins smartconnect_0/S00_AXI] - connect_bd_intf_net -intf_net save_to_hbm_0_m_axi_d_hbm_p0 [get_bd_intf_pins m_axi_d_hbm_p12] [get_bd_intf_pins save_to_hbm_0/m_axi_d_hbm_p0] - connect_bd_intf_net -intf_net save_to_hbm_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p13] [get_bd_intf_pins save_to_hbm_0/m_axi_d_hbm_p1] connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins action_config_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI] connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins mailbox_0/S0_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI] connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_bram_ctrl_calibration_addr/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI] connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI] - connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins smartconnect_0/M04_AXI] [get_bd_intf_pins transfer_hbm_0/s_axi_control] - connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_bram_ctrl_hbm_transfer_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI] - connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/M00_AXI] connect_bd_intf_net -intf_net timer_hbm_0_data_out [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins timer_hbm_0/data_out] connect_bd_intf_net -intf_net timer_host_0_data_out [get_bd_intf_pins axis_register_slice_data_1/S_AXIS] [get_bd_intf_pins timer_host_0/data_out] - connect_bd_intf_net -intf_net transfer_hbm_0_m_axi_d_hbm_p0 [get_bd_intf_pins smartconnect_1/S01_AXI] [get_bd_intf_pins transfer_hbm_0/m_axi_d_hbm_p0] - connect_bd_intf_net -intf_net transfer_hbm_0_m_axi_uram [get_bd_intf_pins axi_bram_ctrl_hbm_transfer_0/S_AXI] [get_bd_intf_pins transfer_hbm_0/m_axi_uram] - connect_bd_intf_net -intf_net writer_split_0_addr_out_1 [get_bd_intf_pins axis_addr_fifo_3/S_AXIS] [get_bd_intf_pins writer_split_0/addr_out_1] - connect_bd_intf_net -intf_net writer_split_0_addr_out_2 [get_bd_intf_pins axis_addr_fifo_4/S_AXIS] [get_bd_intf_pins writer_split_0/addr_out_2] - connect_bd_intf_net -intf_net writer_split_0_data_out_1 [get_bd_intf_pins axis_data_fifo_6/S_AXIS] [get_bd_intf_pins writer_split_0/data_out_1] - connect_bd_intf_net -intf_net writer_split_0_data_out_2 [get_bd_intf_pins axis_data_fifo_7/S_AXIS] [get_bd_intf_pins writer_split_0/data_out_2] # Create port connections connect_bd_net -net action_config_0_clear_counters [get_bd_pins action_config_0/clear_counters] [get_bd_pins network_stack/clear_counters] @@ -563,7 +455,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net action_config_0_nmodules [get_bd_pins action_config_0/nmodules] [get_bd_pins data_collection_fsm_0/nmodules] connect_bd_net -net action_config_0_nstorage_cells [get_bd_pins action_config_0/nstorage_cells] [get_bd_pins data_collection_fsm_0/nstorage_cells] connect_bd_net -net action_config_0_one_over_energy [get_bd_pins action_config_0/one_over_energy] [get_bd_pins data_collection_fsm_0/one_over_energy] - connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_calibration_addr/s_axi_aclk] [get_bd_pins axi_bram_ctrl_hbm_transfer_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_hbm_transfer_1/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_addr_fifo_2/s_axis_aclk] [get_bd_pins axis_addr_fifo_3/s_axis_aclk] [get_bd_pins axis_addr_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_7/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_register_slice_addr_0/aclk] [get_bd_pins axis_register_slice_addr_1/aclk] [get_bd_pins axis_register_slice_data_0/aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins internal_packet_generator_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins timer_hbm_0/ap_clk] [get_bd_pins timer_host_0/ap_clk] [get_bd_pins transfer_hbm_0/ap_clk] [get_bd_pins writer_split_0/ap_clk] + connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_calibration_addr/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_addr_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_register_slice_addr_0/aclk] [get_bd_pins axis_register_slice_addr_1/aclk] [get_bd_pins axis_register_slice_data_0/aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins internal_packet_generator_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins network_stack/axiclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins timer_hbm_0/ap_clk] [get_bd_pins timer_host_0/ap_clk] connect_bd_net -net axis_addr_fifo_2_almost_empty [get_bd_pins action_config_0/calib_addr_fifo_empty] [get_bd_pins axis_addr_fifo_1/almost_empty] connect_bd_net -net axis_addr_fifo_2_almost_full [get_bd_pins action_config_0/calib_addr_fifo_full] [get_bd_pins axis_addr_fifo_1/almost_full] connect_bd_net -net axis_addr_fifo_4_almost_empty [get_bd_pins action_config_0/last_addr_fifo_empty] [get_bd_pins axis_addr_fifo_2/almost_empty] @@ -602,9 +494,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net network_stack_packets_sls_ap_vld [get_bd_pins action_config_0/packets_sls_valid] [get_bd_pins network_stack/packets_sls_ap_vld] connect_bd_net -net network_stack_packets_udp [get_bd_pins action_config_0/packets_udp] [get_bd_pins network_stack/packets_udp] connect_bd_net -net network_stack_packets_udp_ap_vld [get_bd_pins action_config_0/packets_udp_valid] [get_bd_pins network_stack/packets_udp_ap_vld] - connect_bd_net -net one_dout [get_bd_pins one/dout] [get_bd_pins save_to_hbm_0/completion_out_TREADY] - connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axi_bram_ctrl_hbm_transfer_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_hbm_transfer_1/s_axi_aresetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_addr_fifo_2/s_axis_aresetn] [get_bd_pins axis_addr_fifo_3/s_axis_aresetn] [get_bd_pins axis_addr_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_7/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_register_slice_addr_0/aresetn] [get_bd_pins axis_register_slice_addr_1/aresetn] [get_bd_pins axis_register_slice_data_0/aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] - connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_calibration_addr/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins internal_packet_generator_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins save_to_hbm_0/ap_rst_n] [get_bd_pins timer_hbm_0/ap_rst_n] [get_bd_pins timer_host_0/ap_rst_n] [get_bd_pins transfer_hbm_0/ap_rst_n] [get_bd_pins writer_split_0/ap_rst_n] + connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_addr_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_register_slice_addr_0/aresetn] [get_bd_pins axis_register_slice_addr_1/aresetn] [get_bd_pins axis_register_slice_data_0/aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_calibration_addr/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins internal_packet_generator_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins timer_hbm_0/ap_rst_n] [get_bd_pins timer_host_0/ap_rst_n] connect_bd_net -net timer_hbm_0_counter [get_bd_pins action_config_0/stalls_hbm] [get_bd_pins timer_hbm_0/counter] connect_bd_net -net timer_hbm_0_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm_0/counter_ap_vld] connect_bd_net -net timer_host_0_counter [get_bd_pins action_config_0/stalls_host] [get_bd_pins timer_host_0/counter] diff --git a/receiver/HLSSimulatedDevice.cpp b/receiver/HLSSimulatedDevice.cpp index 9333020b..8d98d8f2 100644 --- a/receiver/HLSSimulatedDevice.cpp +++ b/receiver/HLSSimulatedDevice.cpp @@ -208,21 +208,13 @@ void HLSSimulatedDevice::HLSMainThread() { STREAM_512 raw3; STREAM_512 raw4; - hls::stream > pedestalG0_subtracted; - STREAM_512 converted_1; STREAM_512 converted_2; - STREAM_512 converted_3; - STREAM_512 converted_4; - STREAM_512 converted_5; hls::stream addr0; hls::stream addr1; hls::stream addr2; hls::stream addr3; - hls::stream addr4; - hls::stream addr5; - hls::stream addr6; hls::stream > udp_metadata; ap_uint<1> idle_data_collection; @@ -315,26 +307,9 @@ void HLSSimulatedDevice::HLSMainThread() { // Timer procedure - count how many times write_data is not accepting input (to help track down latency issues) hls_cores.emplace_back([&] { timer_host(converted_1, converted_2, counter_host); }); - // Temporary - split streams so data can be written to both HBM and internal memory - hls_cores.emplace_back([&] { writer_split(converted_2, converted_3, converted_4, - addr3, addr4, addr5); }); - - hls::stream save_to_hbm_completion; - ap_uint<8> save_to_hbm_err_reg; - uint64_t save_to_hbm_packets_processed; - ap_uint<1> save_to_hbm_idle; - - // 3. Write images to HBM - hls_cores.emplace_back([&] { save_to_hbm(converted_3, addr4, save_to_hbm_completion, - hbm.data(), - hbm.data(), - save_to_hbm_packets_processed, - save_to_hbm_idle, - save_to_hbm_err_reg); }); - - // 4. Prepare data to write to host memory + // 3. Prepare data to write to host memory hls_cores.emplace_back([&] { - host_writer(converted_4, addr5, datamover_out.GetDataStream(), + host_writer(converted_2, addr3, datamover_out.GetDataStream(), datamover_out.GetCtrlStream(), work_request_stream, completion_stream, packets_processed, host_writer_idle, err_reg); }); @@ -353,12 +328,6 @@ void HLSSimulatedDevice::HLSMainThread() { if (!addr3.empty()) throw std::runtime_error("Addr3 queue not empty"); - if (!addr4.empty()) - throw std::runtime_error("Addr4 queue not empty"); - - if (!addr5.empty()) - throw std::runtime_error("Addr5 queue not empty"); - if (!raw1.empty()) throw std::runtime_error("Raw1 queue not empty"); @@ -371,21 +340,12 @@ void HLSSimulatedDevice::HLSMainThread() { if (!raw4.empty()) throw std::runtime_error("Raw4 queue not empty"); - if (!pedestalG0_subtracted.empty()) - throw std::runtime_error("PedestalG0_subtracted queue not empty"); - if (!converted_1.empty()) throw std::runtime_error("Converted_1 queue not empty"); if (!converted_2.empty()) throw std::runtime_error("Converted_2 queue not empty"); - if (!converted_3.empty()) - throw std::runtime_error("Converted_3 queue not empty"); - - if (!converted_4.empty()) - throw std::runtime_error("Converted_4 queue not empty"); - if (!datamover_in.GetDataStream().empty()) throw std::runtime_error("Datamover queue is not empty"); @@ -406,22 +366,3 @@ void HLSSimulatedDevice::HW_GetStatus(ActionStatus *status) const { status->max_modules = max_modules; status->hbm_size_bytes = hbm_if_size; } - -void HLSSimulatedDevice::HBMTransfer(void *uram, uint64_t hbm_interface, uint64_t hbm_offset, bool hbm_to_uram, - uint8_t stride, uint8_t uram_offset) { - if (hbm_interface >= hbm_if_count) - throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "HBM interface out of bounds"); - if (hbm_offset > hbm_if_size - (RAW_MODULE_SIZE * sizeof(uint16_t))) - throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "HBM offset out of bounds"); - if ((stride != 1) && (stride != 2) && (stride != 4)) - throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "Only stride of 1, 2 and 4 allowed"); - if (uram_offset >= stride) - throw JFJochException(JFJochExceptionCategory::InputParameterInvalid, "UltraRAM stride out of bounds"); - - transfer_hbm((ap_uint<256> *) hbm.data(), - (ap_uint<256> *) uram, - (hbm_interface * hbm_if_size + hbm_offset) / 32, - hbm_to_uram, - stride, - uram_offset); -} \ No newline at end of file diff --git a/receiver/HLSSimulatedDevice.h b/receiver/HLSSimulatedDevice.h index 3fa13a0b..e3d7185e 100644 --- a/receiver/HLSSimulatedDevice.h +++ b/receiver/HLSSimulatedDevice.h @@ -61,8 +61,6 @@ public: void CreateFinalPacket(const DiffractionExperiment& experiment); AXI_STREAM &OutputStream(); void Cancel() override; - - void HBMTransfer(void *uram, uint64_t hbm_interface, uint64_t hbm_offset, bool hbm_to_uram, uint8_t stride, uint8_t uram_offset); }; diff --git a/tests/FPGAIntegrationTest.cpp b/tests/FPGAIntegrationTest.cpp index 609186e1..4b1ed31c 100644 --- a/tests/FPGAIntegrationTest.cpp +++ b/tests/FPGAIntegrationTest.cpp @@ -1041,82 +1041,3 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_storage_cell_convert_G1", } } -TEST_CASE("HLS_C_transfer_hbm_1_interface", "[FPGA][Full]") { - std::vector test_frame_1(RAW_MODULE_SIZE); - std::vector test_frame_2(RAW_MODULE_SIZE); - - std::mt19937 g1(1387); - std::uniform_int_distribution dist(0, 65535); - - for (auto &i: test_frame_1) - i = dist(g1); - - HLSSimulatedDevice test(0, 64); - - REQUIRE(test_frame_1 != test_frame_2); - - test.HBMTransfer(test_frame_1.data(), 14, 16*1024, false, 1, 0); - test.HBMTransfer(test_frame_2.data(), 14, 16*1024, true, 1, 0); - - REQUIRE(test_frame_1 == test_frame_2); -} - -TEST_CASE("HLS_C_transfer_hbm_2_interfaces", "[FPGA][Full]") { - std::vector test_frame_1(RAW_MODULE_SIZE); - std::vector test_frame_2(RAW_MODULE_SIZE); - - std::mt19937 g1(1388); - std::uniform_int_distribution dist(0, 65535); - - for (auto &i: test_frame_1) - i = dist(g1); - - HLSSimulatedDevice test(0, 64); - - REQUIRE(test_frame_1 != test_frame_2); - - test.HBMTransfer(test_frame_1.data(), 14, 16*1024, false, 2, 0); - test.HBMTransfer(test_frame_1.data(), 15, 16*1024, false, 2, 1); - test.HBMTransfer(test_frame_2.data(), 14, 16*1024, true, 2, 0); - test.HBMTransfer(test_frame_2.data(), 15, 16*1024, true, 2, 1); - - REQUIRE(test_frame_1 == test_frame_2); -} - -TEST_CASE("HLS_C_Simulation_internal_packet_generator_write_to_hbm", "[FPGA][Full]") { - const uint16_t nmodules = 1; - - DiffractionExperiment x((DetectorGeometry(nmodules))); - - x.Mode(DetectorMode::Raw); - x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0); - - HLSSimulatedDevice test(0, 64); - test.SetFPGANonBlockingMode(false); - - std::vector test_frame_1(RAW_MODULE_SIZE); - std::vector test_frame_2(RAW_MODULE_SIZE); - - std::mt19937 g1(1387); - std::uniform_int_distribution dist(0, 65535); - - for (auto &i: test_frame_1) - i = dist(g1); - - REQUIRE_NOTHROW(test.SetCustomInternalGeneratorFrame(test_frame_1)); - REQUIRE_NOTHROW(test.StartAction(x)); - REQUIRE_NOTHROW(test.WaitForActionComplete()); - - REQUIRE(test.OutputStream().size() == 1); - - JFJochProtoBuf::AcquisitionDeviceStatistics device_statistics; - REQUIRE_NOTHROW(test.SaveStatistics(x, device_statistics)); - REQUIRE(device_statistics.bytes_received() == 128 * nmodules * 4 * JUNGFRAU_PACKET_SIZE_BYTES); - - REQUIRE(test_frame_1 != test_frame_2); - - test.HBMTransfer(test_frame_2.data(), 12, 2*512*1024, true, 2, 0); - test.HBMTransfer(test_frame_2.data(), 14, 2*512*1024, true, 2, 1); - - REQUIRE(test_frame_1 == test_frame_2); -}