diff --git a/fpga/hls/internal_packet_generator.cpp b/fpga/hls/internal_packet_generator.cpp index c7e82c81..6f280deb 100644 --- a/fpga/hls/internal_packet_generator.cpp +++ b/fpga/hls/internal_packet_generator.cpp @@ -6,14 +6,15 @@ void internal_packet_generator(STREAM_512 &data_in, STREAM_512 &data_out, hls::stream > &addr_in, hls::stream > &addr_out, - ap_uint<512> module_cache[RAW_MODULE_SIZE * sizeof(uint16_t) / 512 * 8], + ap_uint<512> *frame, volatile ap_uint<1> &in_cancel) { #pragma HLS INTERFACE ap_ctrl_none port=return #pragma HLS INTERFACE register both axis port=data_in #pragma HLS INTERFACE register both axis port=data_out #pragma HLS INTERFACE register both axis port=addr_in #pragma HLS INTERFACE register both axis port=addr_out -#pragma HLS INTERFACE bram port=module_cache storage_type=ram_1p +#pragma HLS INTERFACE m_axi port=frame bundle=frame depth=512 offset=off \ + max_read_burst_length=16 max_write_burst_length=16 latency=2 num_write_outstanding=8 num_read_outstanding=9 #pragma HLS INTERFACE ap_none register port=in_cancel @@ -59,7 +60,7 @@ void internal_packet_generator(STREAM_512 &data_in, STREAM_512 &data_out, packet_out.user = 0; packet_out.id = 0; packet_out.last = (axis_packet == 127) ? 1 : 0; - packet_out.data = module_cache[i]; + packet_out.data = frame[i]; data_out << packet_out; } if (module_number == modules - 1) { diff --git a/fpga/scripts/bd_pcie.tcl b/fpga/scripts/bd_pcie.tcl index e35a86c0..2637e8ad 100644 --- a/fpga/scripts/bd_pcie.tcl +++ b/fpga/scripts/bd_pcie.tcl @@ -644,7 +644,8 @@ proc create_root_design { parentCell } { assign_bd_address -offset 0x00070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/axi_firewall_0/S_AXI_CTL/Control] -force assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/xdma_0/S_AXI_LITE/CTL0] -force assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force - assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator/S_AXI/Mem0] -force + assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jungfraujoch_0/internal_packet_generator_0/Data_m_axi_frame] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_1/S_AXI/Mem0] -force assign_bd_address -offset 0x00010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_1/action_config_0/s_axi/reg0] -force assign_bd_address -offset 0x00020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs mac_100g_1/cmac_usplus_0/s_axi/Reg] -force @@ -655,6 +656,7 @@ proc create_root_design { parentCell } { assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_1/xdma_0/S_AXI_LITE/CTL0] -force assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_1/axi_bram_ctrl_internal_packet_generator/S_AXI/Mem0] -force + assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/internal_packet_generator_0/Data_m_axi_frame] [get_bd_addr_segs jungfraujoch_1/axi_bram_ctrl_internal_packet_generator_1/S_AXI/Mem0] -force assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p0] [get_bd_addr_segs gain_uram_0/axi_bram_ctrl_0/S_AXI/Mem0] -force assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p1] [get_bd_addr_segs gain_uram_1/axi_bram_ctrl_0/S_AXI/Mem0] -force diff --git a/fpga/scripts/bd_pcie_100g.tcl b/fpga/scripts/bd_pcie_100g.tcl index f280b43a..d910915a 100644 --- a/fpga/scripts/bd_pcie_100g.tcl +++ b/fpga/scripts/bd_pcie_100g.tcl @@ -441,7 +441,8 @@ proc create_root_design { parentCell } { assign_bd_address -offset 0x00070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/axi_firewall_0/S_AXI_CTL/Control] -force assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/xdma_0/S_AXI_LITE/CTL0] -force assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force - assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator/S_AXI/Mem0] -force + assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_0/S_AXI/Mem0] -force + assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jungfraujoch_0/internal_packet_generator_0/Data_m_axi_frame] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_1/S_AXI/Mem0] -force assign_bd_address set_property -dict [ list \ diff --git a/fpga/scripts/jfjoch.tcl b/fpga/scripts/jfjoch.tcl index cf859ec1..ba039c77 100644 --- a/fpga/scripts/jfjoch.tcl +++ b/fpga/scripts/jfjoch.tcl @@ -90,6 +90,10 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } + set_property -dict [ list \ + CONFIG.DESIGN_NUMBER {0} \ + CONFIG.MAX_MODULES_FPGA_PARAM {0x00000010} \ + ] $action_config_0 # Create instance: axi_bram_ctrl_calibration_addr, and set properties set axi_bram_ctrl_calibration_addr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_calibration_addr ] @@ -99,14 +103,23 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { CONFIG.SINGLE_PORT_BRAM {1} \ ] $axi_bram_ctrl_calibration_addr - # Create instance: axi_bram_ctrl_internal_packet_generator, and set properties - set axi_bram_ctrl_internal_packet_generator [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_internal_packet_generator ] + # Create instance: axi_bram_ctrl_internal_packet_generator_0, and set properties + set axi_bram_ctrl_internal_packet_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_internal_packet_generator_0 ] set_property -dict [ list \ CONFIG.DATA_WIDTH {512} \ CONFIG.PROTOCOL {AXI4} \ CONFIG.READ_LATENCY {1} \ CONFIG.SINGLE_PORT_BRAM {1} \ - ] $axi_bram_ctrl_internal_packet_generator + ] $axi_bram_ctrl_internal_packet_generator_0 + + # Create instance: axi_bram_ctrl_internal_packet_generator_1, and set properties + set axi_bram_ctrl_internal_packet_generator_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_internal_packet_generator_1 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_LATENCY {1} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_internal_packet_generator_1 # Create instance: axis_addr_fifo_0, and set properties set axis_addr_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_addr_fifo_0 ] @@ -368,7 +381,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins eth_in] [get_bd_intf_pins network_stack/eth_in] connect_bd_intf_net -intf_net S_AXIS_1 [get_bd_intf_pins s_axis_h2c_data] [get_bd_intf_pins axis_data_fifo_h2c_data/S_AXIS] connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_calibration_addr/BRAM_PORTA] [get_bd_intf_pins calibration_addr_bram/BRAM_PORTB] - connect_bd_intf_net -intf_net axi_bram_ctrl_1_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTB] + connect_bd_intf_net -intf_net axi_bram_ctrl_internal_packet_generator_1_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_1/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTB] + connect_bd_intf_net -intf_net axi_bram_ctrl_internal_packet_generator_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_0/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTA] connect_bd_intf_net -intf_net axis_addr_fifo_0_M_AXIS [get_bd_intf_pins axis_addr_fifo_0/M_AXIS] [get_bd_intf_pins internal_packet_generator_0/addr_in] connect_bd_intf_net -intf_net axis_addr_fifo_2_M_AXIS [get_bd_intf_pins axis_addr_fifo_1/M_AXIS] [get_bd_intf_pins jf_conversion_0/addr_in] connect_bd_intf_net -intf_net axis_addr_fifo_3_M_AXIS [get_bd_intf_pins axis_addr_fifo_2/M_AXIS] [get_bd_intf_pins host_writer_0/addr_in] @@ -400,7 +414,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_intf_net -intf_net host_writer_0_m_axis_completion [get_bd_intf_pins axis_work_completion_fifo_0/S_AXIS] [get_bd_intf_pins host_writer_0/m_axis_completion] connect_bd_intf_net -intf_net internal_packet_generator_0_addr_out [get_bd_intf_pins axis_register_slice_addr_0/S_AXIS] [get_bd_intf_pins internal_packet_generator_0/addr_out] connect_bd_intf_net -intf_net internal_packet_generator_0_data_out [get_bd_intf_pins axis_register_slice_data_0/S_AXIS] [get_bd_intf_pins internal_packet_generator_0/data_out] - connect_bd_intf_net -intf_net internal_packet_generator_0_module_cache_PORTA [get_bd_intf_pins internal_packet_generator_0/module_cache_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTA] + connect_bd_intf_net -intf_net internal_packet_generator_0_m_axi_frame [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_1/S_AXI] [get_bd_intf_pins internal_packet_generator_0/m_axi_frame] connect_bd_intf_net -intf_net jf_conversion_0_addr_out [get_bd_intf_pins axis_register_slice_addr_1/S_AXIS] [get_bd_intf_pins jf_conversion_0/addr_out] connect_bd_intf_net -intf_net jf_conversion_0_data_out [get_bd_intf_pins axis_data_fifo_4/S_AXIS] [get_bd_intf_pins jf_conversion_0/data_out] connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p0 [get_bd_intf_pins m_axi_d_hbm_p0] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p0] @@ -425,7 +439,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins action_config_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI] connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins mailbox_0/S0_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI] connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_bram_ctrl_calibration_addr/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI] - connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI] connect_bd_intf_net -intf_net timer_hbm_0_data_out [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins timer_hbm_0/data_out] connect_bd_intf_net -intf_net timer_host_0_data_out [get_bd_intf_pins axis_register_slice_data_1/S_AXIS] [get_bd_intf_pins timer_host_0/data_out] @@ -440,7 +454,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net action_config_0_nmodules [get_bd_pins action_config_0/nmodules] [get_bd_pins data_collection_fsm_0/nmodules] connect_bd_net -net action_config_0_nstorage_cells [get_bd_pins action_config_0/nstorage_cells] [get_bd_pins data_collection_fsm_0/nstorage_cells] connect_bd_net -net action_config_0_one_over_energy [get_bd_pins action_config_0/one_over_energy] [get_bd_pins data_collection_fsm_0/one_over_energy] - connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_calibration_addr/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_addr_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_register_slice_addr_0/aclk] [get_bd_pins axis_register_slice_addr_1/aclk] [get_bd_pins axis_register_slice_data_0/aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins internal_packet_generator_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins network_stack/axiclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins timer_hbm_0/ap_clk] [get_bd_pins timer_host_0/ap_clk] + connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_calibration_addr/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_addr_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_register_slice_addr_0/aclk] [get_bd_pins axis_register_slice_addr_1/aclk] [get_bd_pins axis_register_slice_data_0/aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins internal_packet_generator_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins network_stack/axiclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins timer_hbm_0/ap_clk] [get_bd_pins timer_host_0/ap_clk] connect_bd_net -net axis_addr_fifo_2_almost_empty [get_bd_pins action_config_0/calib_addr_fifo_empty] [get_bd_pins axis_addr_fifo_1/almost_empty] connect_bd_net -net axis_addr_fifo_2_almost_full [get_bd_pins action_config_0/calib_addr_fifo_full] [get_bd_pins axis_addr_fifo_1/almost_full] connect_bd_net -net axis_addr_fifo_4_almost_empty [get_bd_pins action_config_0/last_addr_fifo_empty] [get_bd_pins axis_addr_fifo_2/almost_empty] @@ -480,7 +494,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { connect_bd_net -net network_stack_packets_udp [get_bd_pins action_config_0/packets_udp] [get_bd_pins network_stack/packets_udp] connect_bd_net -net network_stack_packets_udp_ap_vld [get_bd_pins action_config_0/packets_udp_valid] [get_bd_pins network_stack/packets_udp_ap_vld] connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_addr_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_register_slice_addr_0/aresetn] [get_bd_pins axis_register_slice_addr_1/aresetn] [get_bd_pins axis_register_slice_data_0/aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] - connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_calibration_addr/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator/s_axi_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins internal_packet_generator_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins timer_hbm_0/ap_rst_n] [get_bd_pins timer_host_0/ap_rst_n] + connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_calibration_addr/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins internal_packet_generator_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins timer_hbm_0/ap_rst_n] [get_bd_pins timer_host_0/ap_rst_n] connect_bd_net -net timer_hbm_0_counter [get_bd_pins action_config_0/stalls_hbm] [get_bd_pins timer_hbm_0/counter] connect_bd_net -net timer_hbm_0_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm_0/counter_ap_vld] connect_bd_net -net timer_host_0_counter [get_bd_pins action_config_0/stalls_host] [get_bd_pins timer_host_0/counter]