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v1.0.0-rc.36

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leonarski_f
2025-05-05 19:32:22 +02:00
parent 759243d1bf
commit 040cf08386
333 changed files with 22724 additions and 15251 deletions
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114
tests/FPGAIntegrationTest.cpp
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@@ -14,7 +14,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator", "[FPGA][Full]") {
Logger logger(Catch::getResultCapture().getCurrentTestName());
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0);
@@ -48,7 +48,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_custom_frame", "[FPGA][Ful
const uint16_t nmodules = 32;
const size_t nframes = 2;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
std::vector<uint16_t> test_frame(nmodules*RAW_MODULE_SIZE);
@@ -92,7 +92,7 @@ TEST_CASE("HLS_C_Simulation_check_raw", "[FPGA][Full]") {
LoadBinaryFile("../../tests/test_data/mod5_raw0.bin", raw_frames.data(), RAW_MODULE_SIZE);
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[4096];
x.Mode(DetectorMode::Raw);
@@ -127,7 +127,7 @@ TEST_CASE("HLS_C_Simulation_check_missing_modules", "[FPGA][Full]") {
const uint64_t nframes = AcquisitionCounters::ThresholdFramesLost + 5;
std::vector<uint16_t> raw_frames(nframes * RAW_MODULE_SIZE, 0);
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.PedestalG0Frames(0).ImagesPerTrigger(nframes).NumTriggers(1);
@@ -153,7 +153,7 @@ TEST_CASE("HLS_C_Simulation_check_cancel", "[FPGA][Full]") {
Logger logger(Catch::getResultCapture().getCurrentTestName());
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[4096];
@@ -178,7 +178,7 @@ TEST_CASE("HLS_C_Simulation_check_cancel_conversion", "[FPGA][Full]") {
Logger logger(Catch::getResultCapture().getCurrentTestName());
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[4096];
@@ -203,7 +203,7 @@ TEST_CASE("HLS_C_Simulation_check_delay", "[FPGA][Full]") {
std::vector<uint16_t> raw_frames(RAW_MODULE_SIZE*20);
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[4096];
@@ -247,7 +247,7 @@ TEST_CASE("HLS_C_Simulation_check_lost_frame_raw", "[FPGA][Full]") {
std::vector<uint16_t> raw_frames(RAW_MODULE_SIZE*20);
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[4096];
@@ -278,7 +278,7 @@ TEST_CASE("HLS_C_Simulation_check_lost_frame_conversion", "[FPGA][Full]") {
std::vector<uint16_t> raw_frames(RAW_MODULE_SIZE*20);
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[4096];
@@ -309,7 +309,7 @@ TEST_CASE("HLS_C_Simulation_check_single_packet_raw", "[FPGA][Full]") {
std::vector<uint16_t> raw_frames(RAW_MODULE_SIZE*20);
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[4096];
uint16_t wrong[4096];
@@ -373,7 +373,7 @@ TEST_CASE("HLS_C_Simulation_check_single_packet_conv", "[FPGA][Full]") {
std::vector<uint16_t> raw_frames(RAW_MODULE_SIZE*20);
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[4096];
int16_t wrong[4096];
@@ -440,7 +440,7 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range", "[FPGA][Full]") {
std::vector<double> energy_values = {6.0, 12.4, 17.7, 5, 4.5, 3.7};
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion);
HLSSimulatedDevice test(0, 64);
@@ -489,7 +489,7 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_HG0", "[FPGA][Full]") {
std::vector<double> energy_values = {6.0, 12.4, 17.7, 5, 4.5, 3.7, 2.0, 1.0, 0.5, 0.1};
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion).UsingGainHG0(true);
HLSSimulatedDevice test(0, 64);
@@ -571,7 +571,7 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_fixedG1", "[FPGA][Full]") {
}
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion).FixedGainG1(true);
HLSSimulatedDevice test(0, 64);
@@ -622,7 +622,7 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_I32", "[FPGA][Full]") {
std::vector<double> energy_values = {6.0, 12.4, 17.7, 5, 4.5, 3.7, 3.0};
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion);
HLSSimulatedDevice test(0, 64);
@@ -673,7 +673,7 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_sum4", "[FPGA][Full]") {
std::vector<double> energy_values = {6.0, 12.4, 17.7, 5, 4.5, 3.7};
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion);
HLSSimulatedDevice test(0, 64);
@@ -728,7 +728,7 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_U16", "[FPGA][Full]") {
std::vector<double> energy_values = {6.0, 12.4, 17.7, 5, 4.5, 3.7};
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion);
HLSSimulatedDevice test(0, 64);
@@ -782,7 +782,7 @@ TEST_CASE("HLS_C_Simulation_check_poisson_full_range", "[FPGA][Full]") {
const uint16_t nmodules = 1;
for (int sqrtmult: {1, 2,4,8}) {
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw).PixelSigned(true).BitDepthImage(16);
HLSSimulatedDevice test(0, 64);
@@ -829,7 +829,7 @@ TEST_CASE("HLS_C_Simulation_check_threshold_full_range", "[FPGA][Full]") {
const uint16_t nmodules = 1;
for (int threshold: {1, 2,4,8}) {
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw).PixelSigned(true).BitDepthImage(16);
HLSSimulatedDevice test(0, 64);
@@ -881,7 +881,7 @@ TEST_CASE("HLS_C_Simulation_check_convert_full_range_poisson", "[FPGA][Full]") {
std::vector<double> energy_values = {6.0, 12.4, 17.7, 5, 4.5, 3.7};
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.LossyCompressionPoisson(2);
x.Mode(DetectorMode::Conversion);
HLSSimulatedDevice test(0, 64);
@@ -930,7 +930,7 @@ TEST_CASE("HLS_C_Simulation_no_conversion_U16", "[FPGA][Full]") {
data[211] = UINT16_MAX;
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion).JungfrauConvPhotonCnt(false);
HLSSimulatedDevice test(0, 64);
@@ -965,7 +965,7 @@ TEST_CASE("HLS_C_Simulation_no_conversion_U32", "[FPGA][Full]") {
data[211] = UINT16_MAX;
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion).JungfrauConvPhotonCnt(false);
HLSSimulatedDevice test(0, 64);
@@ -1001,7 +1001,7 @@ TEST_CASE("HLS_C_Simulation_no_conversion_I32", "[FPGA][Full]") {
data[211] = UINT16_MAX;
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion).JungfrauConvPhotonCnt(false);
HLSSimulatedDevice test(0, 64);
@@ -1034,7 +1034,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_convert_full_range", "[FPG
double energy = 6.0;
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
std::vector<uint16_t> data(RAW_MODULE_SIZE);
JFModulePedestal pedestal_g0, pedestal_g1, pedestal_g2;
@@ -1090,7 +1090,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_mask", "[FPGA][Full]") {
double energy = 6.0;
const uint16_t nmodules = 2;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
std::vector<uint16_t> data(RAW_MODULE_SIZE);
@@ -1139,7 +1139,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_convert_full_range_adu_his
double energy = 6.0;
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules, 2, 8, 36, true)));
DiffractionExperiment x(DetJF(nmodules, 2, 8, 36, true));
std::vector<uint16_t> data(RAW_MODULE_SIZE);
JFModulePedestal pedestal_g0, pedestal_g1, pedestal_g2;
@@ -1209,7 +1209,7 @@ TEST_CASE("HLS_C_Simulation_check_2_trigger_convert", "[FPGA][Full]") {
LoadBinaryFile("../../tests/test_data/mod5_conv0.bin", conv_frames.data(), RAW_MODULE_SIZE);
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[4096];
@@ -1266,7 +1266,7 @@ TEST_CASE("HLS_C_Simulation_check_detect_last_frame", "[FPGA][Full]") {
Logger logger(Catch::getResultCapture().getCurrentTestName());
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[4096];
@@ -1289,7 +1289,7 @@ TEST_CASE("HLS_C_Simulation_check_wrong_packet_size", "[FPGA][Full]") {
Logger logger(Catch::getResultCapture().getCurrentTestName());
const uint16_t nmodules = 1;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
uint16_t data[8192];
@@ -1336,7 +1336,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_15_storage_cell_convert_G0
const uint16_t ntrigger = 2;
const uint16_t nstoragecells = 15;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion);
x.PedestalG0Frames(0).NumTriggers(ntrigger).ImagesPerTrigger(nstoragecells).UseInternalPacketGenerator(true)
@@ -1386,7 +1386,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_8_storage_cell_convert_G0"
const uint16_t ntrigger = 2;
const uint16_t nstoragecells = 8;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion);
x.PedestalG0Frames(0).NumTriggers(ntrigger).ImagesPerTrigger(nstoragecells).UseInternalPacketGenerator(true)
@@ -1437,7 +1437,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_16_storage_cell_convert_G0
const uint16_t ntrigger = 4;
const uint16_t nstoragecells = 16;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion);
x.PedestalG0Frames(0).NumTriggers(ntrigger).ImagesPerTrigger(nstoragecells).UseInternalPacketGenerator(true)
@@ -1483,7 +1483,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_storage_cell_convert_G1",
Logger logger(Catch::getResultCapture().getCurrentTestName());
const uint16_t nmodules = 2;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Conversion);
x.PedestalG0Frames(0).NumTriggers(1).ImagesPerTrigger(16).UseInternalPacketGenerator(true)
@@ -1531,7 +1531,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_integration", "[FPGA][Full
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(1).PedestalG0Frames(0);
@@ -1590,7 +1590,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_integration_mask", "[FPGA]
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(1).PedestalG0Frames(0).ApplyPixelMask(false);
@@ -1643,7 +1643,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_count_threshol
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(1).PedestalG0Frames(0);
@@ -1695,7 +1695,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_mask", "[FPGA]
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(1).PedestalG0Frames(0);
@@ -1768,7 +1768,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_overload", "[F
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(1).PedestalG0Frames(0).PixelSigned(true);
@@ -1818,7 +1818,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_min_pix_per_sp
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(1).PedestalG0Frames(0);
@@ -1880,7 +1880,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_d_min_max", "[
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(1).PedestalG0Frames(0);
@@ -1936,7 +1936,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_snr_threshold"
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(1).PedestalG0Frames(0);
@@ -1995,7 +1995,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_pixel_threshold_summation"
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(1).PedestalG0Frames(0).Summation(4).PixelValueLowThreshold(4).AutoSummation(true);
@@ -2030,7 +2030,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_32bit", "[FPGA][Full]") {
const uint16_t nmodules = 1;
const size_t nframes = 2;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
std::vector<uint16_t> test_frame(nmodules*RAW_MODULE_SIZE);
@@ -2080,7 +2080,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_summation", "[FPGA][Full]"
const uint16_t nmodules = 1;
const size_t nframes = 16;
const size_t nsummation = 16;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
std::vector<uint16_t> test_frame(nmodules*RAW_MODULE_SIZE);
@@ -2128,7 +2128,7 @@ TEST_CASE("HLS_C_Simulation_count_sat_and_err_pixels", "[FPGA][Full]") {
const uint16_t nmodules = 3;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0).PixelSigned(true);
@@ -2170,7 +2170,7 @@ TEST_CASE("HLS_C_Simulation_pixel_count_mask", "[FPGA][Full]") {
const uint16_t nmodules = 3;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0).PixelSigned(true);
@@ -2219,7 +2219,7 @@ TEST_CASE("HLS_C_Simulation_count_pixel_sum", "[FPGA][Full]") {
const uint16_t nmodules = 3;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0).PixelSigned(true);
@@ -2254,7 +2254,7 @@ TEST_CASE("HLS_C_Simulation_check_bunchid", "[FPGA][Full]") {
const uint64_t bunchid = 0xAAAAAAAA87345600;
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.PedestalG0Frames(0).ImagesPerTrigger(3).NumTriggers(1);
@@ -2281,7 +2281,7 @@ TEST_CASE("HLS_C_Simulation_check_raw_eiger", "[FPGA][Full]") {
RawToEigerInput<4>(raw_frame_eiger.data(), raw_frame.data());
const uint16_t nmodules = 1;
DetectorSetup detector((DetectorGeometry(nmodules)), DetectorType::EIGER);
DetectorSetup detector(DetEIGER(nmodules));
DiffractionExperiment x(detector);
x.Mode(DetectorMode::Raw);
@@ -2329,7 +2329,7 @@ TEST_CASE("HLS_C_Simulation_check_raw_eiger_8bit", "[FPGA][Full]") {
const uint16_t nmodules = 1;
DetectorSetup detector((DetectorGeometry(nmodules)), DetectorType::EIGER);
DetectorSetup detector(DetEIGER(nmodules));
RawToEigerInput<8>(raw_frame_eiger.data(), raw_frame.data());
DiffractionExperiment x(detector);
@@ -2391,7 +2391,7 @@ TEST_CASE("HLS_C_Simulation_check_raw_eiger_32bit", "[FPGA][Full]") {
const uint16_t nmodules = 1;
DetectorSetup detector((DetectorGeometry(nmodules)), DetectorType::EIGER);
DetectorSetup detector(DetEIGER(nmodules));
RawToEigerInput<2>(raw_frame_eiger.data(), raw_frame.data());
DiffractionExperiment x(detector);
@@ -2456,7 +2456,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_eiger", "[FPGA][Full]") {
const uint16_t nmodules = 4;
DiffractionExperiment x(DetectorSetup(DetectorGeometry(nmodules), DetectorType::EIGER));
DiffractionExperiment x(DetEIGER(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0);
@@ -2495,13 +2495,13 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_eiger_8bit", "[FPGA][Full]
const uint16_t nmodules = 4;
DiffractionExperiment x(DetectorSetup(DetectorGeometry(nmodules), DetectorType::EIGER));
DiffractionExperiment x(DetEIGER(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0);
x.EigerBitDepth(8);
REQUIRE(x.GetByteDepthReadout() == 1);
REQUIRE(x.GetBitDepthReadout() == 8);
REQUIRE(x.GetByteDepthImage() == 2);
HLSSimulatedDevice test(0, 64);
@@ -2539,7 +2539,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_eiger_32bit", "[FPGA][Full
RawToEigerInput<2>(raw_frame_eiger.data(), raw_frame.data());
DiffractionExperiment x(DetectorSetup(DetectorGeometry(nmodules), DetectorType::EIGER));
DiffractionExperiment x(DetEIGER(nmodules));
x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0);
x.EigerBitDepth(32);
@@ -2576,7 +2576,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_roi_calc", "[FPGA][Full]")
const uint16_t nmodules = 4;
const size_t nimages = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(nimages).PedestalG0Frames(0);
@@ -2643,7 +2643,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_4_images", "[FPGA][Full]")
const uint16_t nmodules = 4;
const uint16_t nimages = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
DiffractionExperiment x(DetJF(nmodules));
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(nimages).PedestalG0Frames(0).InternalPacketGeneratorImages(nimages);