064ec37e9a
- Refactored site specific stuff into a site module - PSI specific stuff is now in the PSI directory. - The old version has been tagged with pre-ansto
45 lines
1.8 KiB
C
Executable File
45 lines
1.8 KiB
C
Executable File
#ifndef VMIO10_DEF_ID
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#define VMIO10_DEF_ID "V01A"
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/*=================================================== [...SINQHM]VMIO10_DEF.H
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**
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** Definition Include file for VMIO10 VME Module.
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**
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** The module has 2 Z8536-CIO chips, each of which has 2 I/O ports (A and B)
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** and 3 counter/timer registers. Hence, the module has 4 I/O ports and
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** 6 counter/timers. Just to confuse things, we call the 4 ports A, B, C and D!
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** Ports A & B are associated with the first Z8536-CIO and Ports C & D are
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** associated with the second Z8536-CIO.
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**------------------------------------------------------------------------------
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** VME offsets for the first Z8536-CIO.
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*/
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#define VMIO_PORT_AB 0x01
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#define VMIO_PORT_B 0x11
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#define VMIO_PORT_A 0x21
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#define VMIO_AB_CNTL 0x31
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/*
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** VME offsets for the second Z8536-CIO.
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*/
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#define VMIO_PORT_CD 0x09
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#define VMIO_PORT_D 0x19
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#define VMIO_PORT_C 0x29
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#define VMIO_CD_CNTL 0x39
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/*
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** Z8536-CIO register definitions
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*/
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#define Z8536_MICR 0x00 /* Master Interrupt Control Register */
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#define Z8536_MCCR 0x01 /* Master Config Control Register */
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#define Z8536_DPPR_A 0x22 /* Data Path Polarity Register - Port A */
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#define Z8536_DPPR_B 0x2a /* Data Path Polarity Register - Port B */
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#define Z8536_DPPR_C 0x05 /* Data Path Polarity Register - Port C */
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#define Z8536_DDR_A 0x23 /* Data Direction Register - Port A */
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#define Z8536_DDR_B 0x2b /* Data Direction Register - Port B */
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#define Z8536_DDR_C 0x06 /* Data Direction Register - Port C */
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#define Z8536_SIOCR_A 0x24 /* Special I/O Control Register - Port A */
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#define Z8536_SIOCR_B 0x2c /* Special I/O Control Register - Port B */
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#define Z8536_SIOCR_C 0x07 /* Special I/O Control Register - Port C */
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/*======================================================= End of VMIO10_DEF.H */
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#endif
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