831 lines
25 KiB
C
831 lines
25 KiB
C
/* vim: ts=8 sts=2 sw=2 cindent
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*/
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#include "hctr.h"
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <ctype.h>
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#ifdef REGISTER_LEVEL_PROGRAMMING
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#define DAQmxFailed(e) ((e) != 0)
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#define DAQmxGetExtendedErrorInfo(b, l) snprintf(b, l, "BAD")
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#include <osiBus.h>
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#include <tTIO.h>
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typedef unsigned long uInt32;
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/**
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* This structure contains the data for the PCI-6602 card
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*/
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typedef struct card_t
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{
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iBus* bus;
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tAddressSpace Bar1;
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tAddressSpace Bar2;
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tTIO *tio_1;
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tTIO *tio_2;
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unsigned char dio_mask;
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unsigned char dev_mask;
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} CARD;
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#else
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#include <NIDAQmx.h>
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#define DAQmxErrChk(functionCall) \
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do { if( DAQmxFailed(error=(functionCall)) ) \
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goto Error; } while(0)
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#endif
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/**
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* This structure encapsulates the data that is private to
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* the implementation of the NI DAQ counter interface
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*/
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typedef struct counter_private_t
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{
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/** extended 64-bit counter value */
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unsigned long long count64;
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/** NIDAQ device number of card */
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int device_number;
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/** NI counter number on card */
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int counter_number;
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/** true if using external sync else timer based sampling */
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bool sync;
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/** sync line number on the card */
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int sync_line_number;
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/** output line number on the card */
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int output_line_number;
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/** Actual physical counter value, as returned by read function */
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uInt32 count32;
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#ifdef REGISTER_LEVEL_PROGRAMMING
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CARD* card;
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#else
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/** NIDAQ opaque task handle */
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TaskHandle taskHandle;
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/** NIDAQ opaque task handle for digital output */
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TaskHandle taskHandle_dout;
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#endif
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} COUNTER_PRIVATE;
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typedef struct mapping_t {
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int cntr_num;
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int sync_num;
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int outp_num;
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} MAPPING;
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static MAPPING mapping[8] = {
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{ 0, 37, 36 },
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{ 1, 33, 32 },
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{ 2, 29, 28 },
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{ 3, 25, 24 },
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{ 4, 21, 20 },
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{ 5, 17, 16 },
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{ 6, 13, 12 },
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{ 7, 9, 8 }
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};
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#ifdef REGISTER_LEVEL_PROGRAMMING
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static void initMite(iBus *bus);
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static CARD* card[10];
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#else
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static int make_dout_task(pHCTR ptr);
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#endif
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int hctr_ctor(const char* device_name, pHCTR* ptr)
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{
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pHCTR hctr = NULL;
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#ifdef REGISTER_LEVEL_PROGRAMMING
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CARD* pci = NULL;
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#endif
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int error = 0;
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bool flag = false;
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char text_string[] = "dev1/ctr0";
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const char *name;
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const char *text;
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hctr = (COUNTER_PRIVATE*) malloc(sizeof(COUNTER_PRIVATE));
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*ptr = hctr;
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memset(*ptr, 0, sizeof(COUNTER_PRIVATE));
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name = device_name;
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text = text_string;
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while (name && *name)
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{
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if (isspace(*name))
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++name;
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else if (*name >= '0' && *name <= '7')
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{
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if (flag)
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{
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(*ptr)->counter_number = *name - '0';
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(*ptr)->sync_line_number = mapping[(*ptr)->counter_number].sync_num;
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(*ptr)->output_line_number = mapping[(*ptr)->counter_number].outp_num;
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}
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else
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{
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(*ptr)->device_number = *name - '0';
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flag = true;
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}
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}
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else if (tolower(*name) != *text)
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{
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/* TODO error */
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printf("Device name error: %s (%d,%d)\n",
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device_name,
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(*ptr)->counter_number,
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(*ptr)->device_number);
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break;
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}
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++name;
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++text;
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}
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#ifdef REGISTER_LEVEL_PROGRAMMING
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if (card[hctr->device_number] == NULL)
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{
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char local_name[40] = "PXI6::1::INSTR";
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FILE* fd = fopen("/proc/nirlpk/lsdaq", "r");
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if (fd)
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{
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bool found = false;
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int count = 0;
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char line[100];
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while (fgets(line, 100, fd))
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{
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if (strstr(line, "0x1310"))
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{
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++count;
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name = strstr(line, "PXI");
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if (name && count == hctr->device_number)
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{
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found = true;
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strcpy(local_name, name);
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break;
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}
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}
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if (!found)
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{
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// TODO error
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}
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}
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fclose(fd);
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}
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card[hctr->device_number] = (CARD*) malloc(sizeof(CARD));
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memset(card[hctr->device_number], 0, sizeof(CARD));
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pci = card[hctr->device_number];
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hctr->card = pci;
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pci->bus = acquireBoard((tChar*) local_name /* "PXI6::1::INSTR" */);
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if(pci->bus == NULL)
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{
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printf("Error accessing the PCI device \"%s\". Exiting.\n",
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local_name);
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error = 1;
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goto Error;
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}
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//Intitialise Mite Chip.
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initMite(pci->bus);
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pci->Bar1 = pci->bus->createAddressSpace(kPCI_BAR1);
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pci->Bar2 = pci->bus->createAddressSpace(kPCI_BAR1);
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pci->tio_1 = new tTIO(pci->Bar1);
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pci->tio_2 = new tTIO(pci->Bar2);
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pci->tio_2->setAddressOffset(0x800);
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//
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//Set all counter outputs to 'input' so we don't accidentally double drive an IO pin
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pci->tio_1->IO_Pin_8_9_Configuration_Register.writeIO_Pin_8_Select(0); //0='input'
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pci->tio_1->IO_Pin_12_13_Configuration_Register.writeIO_Pin_12_Select(0); //0='input'
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pci->tio_1->IO_Pin_16_17_Configuration_Register.writeIO_Pin_16_Select(0); //0='input'
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pci->tio_1->IO_Pin_20_21_Configuration_Register.writeIO_Pin_20_Select(0); //0='input'
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pci->tio_1->IO_Pin_24_25_Configuration_Register.writeIO_Pin_24_Select(0); //0='input'
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pci->tio_1->IO_Pin_28_29_Configuration_Register.writeIO_Pin_28_Select(0); //0='input'
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pci->tio_1->IO_Pin_32_33_Configuration_Register.writeIO_Pin_32_Select(0); //0='input'
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pci->tio_1->IO_Pin_36_37_Configuration_Register.writeIO_Pin_36_Select(0); //0='input'
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pci->tio_2->IO_Pin_8_9_Configuration_Register.writeIO_Pin_8_Select(0); //0='input'
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pci->tio_2->IO_Pin_12_13_Configuration_Register.writeIO_Pin_12_Select(0); //0='input'
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pci->tio_2->IO_Pin_16_17_Configuration_Register.writeIO_Pin_16_Select(0); //0='input'
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pci->tio_2->IO_Pin_20_21_Configuration_Register.writeIO_Pin_20_Select(0); //0='input'
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pci->tio_2->IO_Pin_24_25_Configuration_Register.writeIO_Pin_24_Select(0); //0='input'
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pci->tio_2->IO_Pin_28_29_Configuration_Register.writeIO_Pin_28_Select(0); //0='input'
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pci->tio_2->IO_Pin_32_33_Configuration_Register.writeIO_Pin_32_Select(0); //0='input'
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pci->tio_2->IO_Pin_36_37_Configuration_Register.writeIO_Pin_36_Select(0); //0='input'
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//Bind the first TIO to counters 0-3 on the IO connector, and
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//bind the second TIO to counters 4-7
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pci->tio_1->Clock_Configuration_Register.writeCntr_Swap(0);
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pci->tio_2->Clock_Configuration_Register.writeCntr_Swap(1);
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}
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else
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{
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pci = card[hctr->device_number];
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hctr->card = pci;
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}
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// Mark the counter on this card as in-use
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if (pci->dev_mask & (1 << hctr->counter_number))
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{
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// TODO error
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}
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pci->dev_mask |= 1 << hctr->counter_number;
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/*
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* Set up the counter object
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*/
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switch (hctr->counter_number)
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{
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case 0:
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//Disarm
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pci->tio_1->G0_Command_Register.writeG0_Disarm(1);
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//load initial value of zero
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pci->tio_1->G0_Load_A_Registers.writeG0_Load_A(0x00000000);
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pci->tio_1->G0_Command_Register.writeG0_Load(1);
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//set source to external default source pin
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pci->tio_1->G0_Input_Select_Register.writeG0_Source_Select(1);
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//set gate to no gate
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pci->tio_1->G0_Input_Select_Register.writeG0_Gate_Select(30);
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pci->tio_1->G0_Mode_Register.writeG0_Gate_Polarity(1);
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pci->tio_1->G0_Mode_Register.writeG0_Trigger_Mode_For_Edge_Gate(3);
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//set counting direction to up
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pci->tio_1->G0_Command_Register.writeG0_Up_Down(1);
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//arm counter
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pci->tio_1->G0_Command_Register.writeG0_Arm(1);
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break;
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case 1:
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//Disarm
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pci->tio_1->G1_Command_Register.writeG1_Disarm(1);
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//load initial value of zero
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pci->tio_1->G1_Load_A_Registers.writeG1_Load_A(0x00000000);
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pci->tio_1->G1_Command_Register.writeG1_Load(1);
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//set source to external default source pin
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pci->tio_1->G1_Input_Select_Register.writeG1_Source_Select(1);
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//set gate to no gate
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pci->tio_1->G1_Input_Select_Register.writeG1_Gate_Select(30);
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pci->tio_1->G1_Mode_Register.writeG1_Gate_Polarity(1);
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pci->tio_1->G1_Mode_Register.writeG1_Trigger_Mode_For_Edge_Gate(3);
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//set counting direction to up
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pci->tio_1->G1_Command_Register.writeG1_Up_Down(1);
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//arm counter
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pci->tio_1->G1_Command_Register.writeG1_Arm(1);
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break;
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case 2:
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//Disarm
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pci->tio_1->G2_Command_Register.writeG2_Disarm(1);
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//load initial value of zero
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pci->tio_1->G2_Load_A_Registers.writeG2_Load_A(0x00000000);
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pci->tio_1->G2_Command_Register.writeG2_Load(1);
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//set source to external default source pin
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pci->tio_1->G2_Input_Select_Register.writeG2_Source_Select(1);
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//set gate to no gate
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pci->tio_1->G2_Input_Select_Register.writeG2_Gate_Select(30);
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pci->tio_1->G2_Mode_Register.writeG2_Gate_Polarity(1);
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pci->tio_1->G2_Mode_Register.writeG2_Trigger_Mode_For_Edge_Gate(3);
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//set counting direction to up
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pci->tio_1->G2_Command_Register.writeG2_Up_Down(1);
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//arm counter
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pci->tio_1->G2_Command_Register.writeG2_Arm(1);
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break;
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case 3:
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//Disarm
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pci->tio_1->G3_Command_Register.writeG3_Disarm(1);
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//load initial value of zero
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pci->tio_1->G3_Load_A_Registers.writeG3_Load_A(0x00000000);
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pci->tio_1->G3_Command_Register.writeG3_Load(1);
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//set source to external default source pin
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pci->tio_1->G3_Input_Select_Register.writeG3_Source_Select(1);
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//set gate to no gate
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pci->tio_1->G3_Input_Select_Register.writeG3_Gate_Select(30);
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pci->tio_1->G3_Mode_Register.writeG3_Gate_Polarity(1);
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pci->tio_1->G3_Mode_Register.writeG3_Trigger_Mode_For_Edge_Gate(3);
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//set counting direction to up
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pci->tio_1->G3_Command_Register.writeG3_Up_Down(1);
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//arm counter
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pci->tio_1->G3_Command_Register.writeG3_Arm(1);
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break;
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case 4:
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//Disarm
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pci->tio_2->G0_Command_Register.writeG0_Disarm(1);
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//load initial value of zero
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pci->tio_2->G0_Load_A_Registers.writeG0_Load_A(0x00000000);
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pci->tio_2->G0_Command_Register.writeG0_Load(1);
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//set source to external default source pin
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pci->tio_2->G0_Input_Select_Register.writeG0_Source_Select(1);
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//set gate to no gate
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pci->tio_2->G0_Input_Select_Register.writeG0_Gate_Select(30);
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pci->tio_2->G0_Mode_Register.writeG0_Gate_Polarity(1);
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pci->tio_2->G0_Mode_Register.writeG0_Trigger_Mode_For_Edge_Gate(3);
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//set counting direction to up
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pci->tio_2->G0_Command_Register.writeG0_Up_Down(1);
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//arm counter
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pci->tio_2->G0_Command_Register.writeG0_Arm(1);
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break;
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case 5:
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//Disarm
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pci->tio_2->G1_Command_Register.writeG1_Disarm(1);
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//load initial value of zero
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pci->tio_2->G1_Load_A_Registers.writeG1_Load_A(0x00000000);
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pci->tio_2->G1_Command_Register.writeG1_Load(1);
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//set source to external default source pin
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pci->tio_2->G1_Input_Select_Register.writeG1_Source_Select(1);
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//set gate to no gate
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pci->tio_2->G1_Input_Select_Register.writeG1_Gate_Select(30);
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pci->tio_2->G1_Mode_Register.writeG1_Gate_Polarity(1);
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pci->tio_2->G1_Mode_Register.writeG1_Trigger_Mode_For_Edge_Gate(3);
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//set counting direction to up
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pci->tio_2->G1_Command_Register.writeG1_Up_Down(1);
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//arm counter
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pci->tio_2->G1_Command_Register.writeG1_Arm(1);
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break;
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case 6:
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//Disarm
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pci->tio_2->G2_Command_Register.writeG2_Disarm(1);
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//load initial value of zero
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pci->tio_2->G2_Load_A_Registers.writeG2_Load_A(0x00000000);
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pci->tio_2->G2_Command_Register.writeG2_Load(1);
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//set source to external default source pin
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pci->tio_2->G2_Input_Select_Register.writeG2_Source_Select(1);
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//set gate to no gate
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pci->tio_2->G2_Input_Select_Register.writeG2_Gate_Select(30);
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pci->tio_2->G2_Mode_Register.writeG2_Gate_Polarity(1);
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pci->tio_2->G2_Mode_Register.writeG2_Trigger_Mode_For_Edge_Gate(3);
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//set counting direction to up
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pci->tio_2->G2_Command_Register.writeG2_Up_Down(1);
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//arm counter
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pci->tio_2->G2_Command_Register.writeG2_Arm(1);
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break;
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case 7:
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//Disarm
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pci->tio_2->G3_Command_Register.writeG3_Disarm(1);
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//load initial value of zero
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pci->tio_2->G3_Load_A_Registers.writeG3_Load_A(0x00000000);
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pci->tio_2->G3_Command_Register.writeG3_Load(1);
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//set source to external default source pin
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pci->tio_2->G3_Input_Select_Register.writeG3_Source_Select(1);
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//set gate to no gate
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pci->tio_2->G3_Input_Select_Register.writeG3_Gate_Select(30);
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pci->tio_2->G3_Mode_Register.writeG3_Gate_Polarity(1);
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pci->tio_2->G3_Mode_Register.writeG3_Trigger_Mode_For_Edge_Gate(3);
|
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//set counting direction to up
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pci->tio_2->G3_Command_Register.writeG3_Up_Down(1);
|
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//arm counter
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pci->tio_2->G3_Command_Register.writeG3_Arm(1);
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break;
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}
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#else
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/*********************************************/
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// Create a DAQmx task to hold the counter
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/*********************************************/
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DAQmxErrChk (DAQmxCreateTask("",&(*ptr)->taskHandle));
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|
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/*********************************************/
|
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// Create a DAQmx counter within the task
|
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/*********************************************/
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DAQmxErrChk (
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DAQmxCreateCICountEdgesChan((*ptr)->taskHandle,
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device_name,
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"",
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DAQmx_Val_Rising,
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(*ptr)->count32,
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DAQmx_Val_CountUp));
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|
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/*********************************************/
|
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// Start the DAQmx task
|
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/*********************************************/
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DAQmxErrChk (DAQmxStartTask((*ptr)->taskHandle));
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#endif
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return 0;
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Error:
|
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free(*ptr);
|
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*ptr = NULL;
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return error;
|
|
}
|
|
|
|
int hctr_read(pHCTR hctr, unsigned long long* value)
|
|
{
|
|
int error = 0;
|
|
*value = 0;
|
|
uInt32 counterValue1;
|
|
#ifdef REGISTER_LEVEL_PROGRAMMING
|
|
uInt32 counterValue2;
|
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CARD* pci = hctr->card;
|
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|
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//read counter value
|
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//Use this method to read the value of an armed counter
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//during non-buffered counting. Since the value of the counter may
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//change during the read, we make sure that the value is stable.
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switch (hctr->counter_number)
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{
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case 0:
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counterValue1 = pci->tio_1->G0_Save_Registers.readRegister();
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counterValue2 = pci->tio_1->G0_Save_Registers.readRegister();
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if (counterValue1 != counterValue2)
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counterValue1 = pci->tio_1->G0_Save_Registers.readRegister();
|
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break;
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case 1:
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counterValue1 = pci->tio_1->G1_Save_Registers.readRegister();
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counterValue2 = pci->tio_1->G1_Save_Registers.readRegister();
|
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if (counterValue1 != counterValue2)
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counterValue1 = pci->tio_1->G1_Save_Registers.readRegister();
|
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break;
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case 2:
|
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counterValue1 = pci->tio_1->G2_Save_Registers.readRegister();
|
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counterValue2 = pci->tio_1->G2_Save_Registers.readRegister();
|
|
if (counterValue1 != counterValue2)
|
|
counterValue1 = pci->tio_1->G2_Save_Registers.readRegister();
|
|
break;
|
|
case 3:
|
|
counterValue1 = pci->tio_1->G3_Save_Registers.readRegister();
|
|
counterValue2 = pci->tio_1->G3_Save_Registers.readRegister();
|
|
if (counterValue1 != counterValue2)
|
|
counterValue1 = pci->tio_1->G3_Save_Registers.readRegister();
|
|
break;
|
|
case 4:
|
|
counterValue1 = pci->tio_2->G0_Save_Registers.readRegister();
|
|
counterValue2 = pci->tio_2->G0_Save_Registers.readRegister();
|
|
if (counterValue1 != counterValue2)
|
|
counterValue1 = pci->tio_2->G0_Save_Registers.readRegister();
|
|
break;
|
|
case 5:
|
|
counterValue1 = pci->tio_2->G1_Save_Registers.readRegister();
|
|
counterValue2 = pci->tio_2->G1_Save_Registers.readRegister();
|
|
if (counterValue1 != counterValue2)
|
|
counterValue1 = pci->tio_2->G1_Save_Registers.readRegister();
|
|
break;
|
|
case 6:
|
|
counterValue1 = pci->tio_2->G2_Save_Registers.readRegister();
|
|
counterValue2 = pci->tio_2->G2_Save_Registers.readRegister();
|
|
if (counterValue1 != counterValue2)
|
|
counterValue1 = pci->tio_2->G2_Save_Registers.readRegister();
|
|
break;
|
|
case 7:
|
|
counterValue1 = pci->tio_2->G3_Save_Registers.readRegister();
|
|
counterValue2 = pci->tio_2->G3_Save_Registers.readRegister();
|
|
if (counterValue1 != counterValue2)
|
|
counterValue1 = pci->tio_2->G3_Save_Registers.readRegister();
|
|
break;
|
|
}
|
|
#else
|
|
DAQmxErrChk (DAQmxReadCounterScalarU32(hctr->taskHandle,
|
|
1.0,
|
|
&counterValue1,
|
|
NULL));
|
|
Error:
|
|
if (error)
|
|
counterValue1 = hctr->count32;
|
|
#endif
|
|
hctr->count64 += counterValue1 - hctr->count32;
|
|
hctr->count32 = counterValue1;
|
|
*value = hctr->count64;
|
|
return error;
|
|
}
|
|
|
|
/*
|
|
* Select the source
|
|
*/
|
|
int hctr_source(pHCTR hctr, int value)
|
|
{
|
|
int error = 0;
|
|
#ifdef REGISTER_LEVEL_PROGRAMMING
|
|
CARD* pci = hctr->card;
|
|
int src = 1;
|
|
if (value == 3)
|
|
//set source to internal time base 3, the 80Mhz internal clock
|
|
src = 30;
|
|
else if (value == 2)
|
|
//set source to internal time base 2, the l00Khz internal clock
|
|
src = 18;
|
|
else if (value == 1)
|
|
//set source to internal time base 1, the 20Mhz internal clock
|
|
src = 0;
|
|
else
|
|
//set source to external default source pin
|
|
src = 1;
|
|
switch (hctr->counter_number)
|
|
{
|
|
case 0:
|
|
pci->tio_1->G0_Input_Select_Register.writeG0_Source_Select(src);
|
|
break;
|
|
case 1:
|
|
pci->tio_1->G1_Input_Select_Register.writeG1_Source_Select(src);
|
|
break;
|
|
case 2:
|
|
pci->tio_1->G2_Input_Select_Register.writeG2_Source_Select(src);
|
|
break;
|
|
case 3:
|
|
pci->tio_1->G3_Input_Select_Register.writeG3_Source_Select(src);
|
|
break;
|
|
case 4:
|
|
pci->tio_2->G0_Input_Select_Register.writeG0_Source_Select(src);
|
|
break;
|
|
case 5:
|
|
pci->tio_2->G1_Input_Select_Register.writeG1_Source_Select(src);
|
|
break;
|
|
case 6:
|
|
pci->tio_2->G2_Input_Select_Register.writeG2_Source_Select(src);
|
|
break;
|
|
case 7:
|
|
pci->tio_2->G3_Input_Select_Register.writeG3_Source_Select(src);
|
|
break;
|
|
}
|
|
#else
|
|
// TODO
|
|
// DAQmxGetDevCIPhysicalChans
|
|
// DAQmxSetCICountEdgesTerm
|
|
//Error:
|
|
#endif
|
|
return error;
|
|
}
|
|
|
|
/*
|
|
* Set the output line corresponding to the counter
|
|
*/
|
|
int hctr_outp(pHCTR hctr, int value)
|
|
{
|
|
int error = 0;
|
|
#ifdef REGISTER_LEVEL_PROGRAMMING
|
|
CARD* pci = hctr->card;
|
|
u16 data;
|
|
if (value < 0)
|
|
{
|
|
// set the disabled line to input
|
|
value = 0;
|
|
pci->dio_mask &= ~(1 << hctr->counter_number);
|
|
pci->tio_1->DIO_Control_Register.writeDIO_Pins_Dir(pci->dio_mask);
|
|
}
|
|
else
|
|
{
|
|
pci->dio_mask |= 1 << hctr->counter_number;
|
|
pci->tio_1->DIO_Control_Register.writeDIO_Pins_Dir(pci->dio_mask);
|
|
data = pci->tio_1->DIO_Output_Register.readDIO_Parallel_Data_Out();
|
|
printf("data %04x", data);
|
|
if (value > 0)
|
|
data |= 1 << hctr->counter_number;
|
|
else
|
|
data &= ~(1 << hctr->counter_number);
|
|
pci->tio_1->DIO_Output_Register.writeDIO_Parallel_Data_Out(data);
|
|
printf(" => %04x", data);
|
|
data = pci->tio_1->DIO_Output_Register.readDIO_Parallel_Data_Out();
|
|
printf(" => %04x\n", data);
|
|
}
|
|
#else
|
|
uInt8 data;
|
|
if (value < 0)
|
|
{
|
|
// set the disabled line to logic low
|
|
if (hctr->taskHandle_dout != 0) {
|
|
data = 0;
|
|
DAQmxWriteDigitalLines(hctr->taskHandle_dout,
|
|
1,
|
|
1,
|
|
10.0,
|
|
DAQmx_Val_GroupByChannel,
|
|
&data,
|
|
NULL,
|
|
NULL);
|
|
/*********************************************/
|
|
// DAQmx Stop Code
|
|
/*********************************************/
|
|
DAQmxStopTask(hctr->taskHandle_dout);
|
|
DAQmxClearTask(hctr->taskHandle_dout);
|
|
hctr->taskHandle_dout = 0;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (hctr->taskHandle_dout == 0)
|
|
DAQmxErrChk (make_dout_task(hctr));
|
|
if (value > 0)
|
|
data = 1;
|
|
else
|
|
data = 0;
|
|
DAQmxErrChk (
|
|
DAQmxWriteDigitalScalarU32(hctr->taskHandle_dout,
|
|
1,
|
|
10.0,
|
|
data,
|
|
NULL));
|
|
}
|
|
Error:
|
|
#endif
|
|
return error;
|
|
}
|
|
|
|
/*
|
|
* Set up to read the counter synchronized to an external signal
|
|
*/
|
|
void hctr_sync(pHCTR hctr, bool external)
|
|
{
|
|
#if REGISTER_LEVEL_PROGRAMMING
|
|
CARD* pci = hctr->card;
|
|
// TODO
|
|
#else
|
|
int error = 0;
|
|
char device_name[40];
|
|
if (hctr->sync != external)
|
|
{
|
|
hctr->sync = external;
|
|
/*********************************************/
|
|
// DAQmx Stop Code
|
|
/*********************************************/
|
|
DAQmxStopTask(hctr->taskHandle);
|
|
DAQmxClearTask(hctr->taskHandle);
|
|
/*********************************************/
|
|
// Create a DAQmx task to hold the counter
|
|
/*********************************************/
|
|
DAQmxErrChk (DAQmxCreateTask("",&hctr->taskHandle));
|
|
|
|
/*********************************************/
|
|
// Create a DAQmx counter within the task
|
|
/*********************************************/
|
|
hctr->count32 = 0;
|
|
snprintf(device_name, sizeof(device_name), "dev%d/ctr%d",
|
|
hctr->device_number, hctr->counter_number);
|
|
DAQmxErrChk (
|
|
DAQmxCreateCICountEdgesChan(hctr->taskHandle,
|
|
device_name,
|
|
"",
|
|
DAQmx_Val_Rising,
|
|
hctr->count32,
|
|
DAQmx_Val_CountUp));
|
|
|
|
if (external)
|
|
{
|
|
char str[40];
|
|
snprintf(str, sizeof(str), "dev%d/PFI%d",
|
|
hctr->device_number, hctr->sync_line_number);
|
|
DAQmxErrChk (
|
|
DAQmxCfgSampClkTiming(hctr->taskHandle,
|
|
str,
|
|
10000,
|
|
DAQmx_Val_Rising,
|
|
DAQmx_Val_ContSamps,
|
|
10000));
|
|
}
|
|
/*********************************************/
|
|
// Start the DAQmx task
|
|
/*********************************************/
|
|
DAQmxErrChk (DAQmxStartTask(hctr->taskHandle));
|
|
|
|
}
|
|
Error:
|
|
#endif
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Shut down the counter
|
|
*/
|
|
int hctr_dtor(pHCTR* hctr)
|
|
{
|
|
if (hctr && *hctr)
|
|
{
|
|
#ifdef REGISTER_LEVEL_PROGRAMMING
|
|
CARD* pci = (*hctr)->card;
|
|
switch ((*hctr)->counter_number)
|
|
{
|
|
case 0:
|
|
pci->tio_1->G0_Command_Register.writeG0_Disarm(1);
|
|
break;
|
|
case 1:
|
|
pci->tio_1->G1_Command_Register.writeG1_Disarm(1);
|
|
break;
|
|
case 2:
|
|
pci->tio_1->G2_Command_Register.writeG2_Disarm(1);
|
|
break;
|
|
case 3:
|
|
pci->tio_1->G3_Command_Register.writeG3_Disarm(1);
|
|
break;
|
|
case 4:
|
|
pci->tio_2->G0_Command_Register.writeG0_Disarm(1);
|
|
break;
|
|
case 5:
|
|
pci->tio_2->G1_Command_Register.writeG1_Disarm(1);
|
|
break;
|
|
case 6:
|
|
pci->tio_2->G2_Command_Register.writeG2_Disarm(1);
|
|
break;
|
|
case 7:
|
|
pci->tio_2->G3_Command_Register.writeG3_Disarm(1);
|
|
break;
|
|
}
|
|
|
|
pci->dev_mask &= ~(1 << (*hctr)->counter_number);
|
|
if (pci->dev_mask == 0)
|
|
{
|
|
delete pci->tio_1;
|
|
delete pci->tio_2;
|
|
pci->bus->destroyAddressSpace(pci->Bar1);
|
|
pci->bus->destroyAddressSpace(pci->Bar2);
|
|
|
|
releaseBoard(pci->bus);
|
|
card[(*hctr)->device_number] = NULL;
|
|
free(pci);
|
|
}
|
|
#else
|
|
if ((*hctr)->taskHandle!=0)
|
|
{
|
|
/*********************************************/
|
|
// DAQmx Stop Code
|
|
/*********************************************/
|
|
DAQmxStopTask((*hctr)->taskHandle);
|
|
DAQmxClearTask((*hctr)->taskHandle);
|
|
(*hctr)->taskHandle = 0;
|
|
}
|
|
if ((*hctr)->taskHandle_dout!=0)
|
|
{
|
|
/*********************************************/
|
|
// DAQmx Stop Code
|
|
/*********************************************/
|
|
DAQmxStopTask((*hctr)->taskHandle_dout);
|
|
DAQmxClearTask((*hctr)->taskHandle_dout);
|
|
(*hctr)->taskHandle_dout = 0;
|
|
}
|
|
|
|
#endif
|
|
|
|
/* release the storage */
|
|
free(*hctr);
|
|
*hctr = NULL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
bool hctr_failed(int error)
|
|
{
|
|
if (DAQmxFailed(error))
|
|
return true;
|
|
else
|
|
return false;
|
|
}
|
|
|
|
void hctr_errmsg(char* buff, int len)
|
|
{
|
|
*buff = '\0';
|
|
DAQmxGetExtendedErrorInfo(buff, len);
|
|
}
|
|
|
|
#ifdef REGISTER_LEVEL_PROGRAMMING
|
|
//
|
|
//Tell the MITE to link the BAR1 address to the DAQ Board
|
|
//You must initialize the MITE before you write to the rest of the PCI board
|
|
void initMite(iBus *bus)
|
|
{
|
|
tAddressSpace Bar0;
|
|
u32 physicalBar1;
|
|
|
|
//Skip MITE initialization for PCMCIA boards
|
|
//(which do not have a MITE DMA controller)
|
|
if(!bus->get(kIsPciPxiBus,0)) return;
|
|
|
|
Bar0 = bus->createAddressSpace(kPCI_BAR0);
|
|
|
|
//Get the physical address of the DAQ board
|
|
physicalBar1 = bus->get(kBusAddressPhysical,kPCI_BAR1);
|
|
|
|
// ***** 6602/6608 specific MITE initialization *****
|
|
// Hit the IO Window Base/Size Register 1 (IOWBSR1) in the MITE. We set the
|
|
// address, enable the window and set the size of the window:
|
|
Bar0.write32(0xC4, (physicalBar1 & 0xffffff00L) | 0x8C);
|
|
|
|
// Write to the IO Window Control Register 1 (IOWCR1) to make the IO window
|
|
// go to RAM memory space instead of the config space
|
|
Bar0.write32(0xF4, 0);
|
|
|
|
// ***** End of 6602/6608 specific code *****
|
|
|
|
bus->destroyAddressSpace(Bar0);
|
|
}
|
|
#else
|
|
int make_dout_task(pHCTR ptr)
|
|
{
|
|
int error = 0;
|
|
char port_range[40];
|
|
/*********************************************/
|
|
// Create a DAQmx task to hold the counter
|
|
/*********************************************/
|
|
DAQmxErrChk (DAQmxCreateTask("",&ptr->taskHandle_dout));
|
|
|
|
/*********************************************/
|
|
// Create the digital channel within the task
|
|
/*********************************************/
|
|
snprintf(port_range, sizeof(port_range), "DEV%d/LINE%d",
|
|
ptr->device_number, ptr->counter_number);
|
|
DAQmxErrChk (DAQmxCreateDOChan(ptr->taskHandle_dout,
|
|
port_range,
|
|
"",
|
|
DAQmx_Val_ChanPerLine));
|
|
|
|
/*********************************************/
|
|
// Start the DAQmx task
|
|
/*********************************************/
|
|
DAQmxErrChk (DAQmxStartTask(ptr->taskHandle_dout));
|
|
return error;
|
|
|
|
Error:
|
|
return error;
|
|
}
|
|
#endif
|