1000 lines
28 KiB
C
1000 lines
28 KiB
C
/* vim: ts=8 sts=2 sw=2 cindent
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*/
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#include "hware.h"
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <ctype.h>
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#ifndef SIMULATE_HARDWARE
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#define DEFAULT_DEVICE "dev1/ctr0"
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#ifdef REGISTER_LEVEL_PROGRAMMING
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#define DEVICE_ID_NUMBER "0x1310"
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#define DAQmxFailed(e) ((e) != 0)
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#define DAQmxGetExtendedErrorInfo(b, l) snprintf(b, l, "BAD")
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#include <osiBus.h>
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#include <tTIO.h>
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typedef unsigned long uInt32;
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/**
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* This structure contains the data for the PCI-6602 card
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*/
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typedef struct card_t
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{
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iBus* bus;
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tAddressSpace Bar1;
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tAddressSpace Bar2;
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tTIO *tio_1;
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tTIO *tio_2;
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unsigned char dio_mask;
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unsigned char dev_mask;
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} CARD;
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#else
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#include <NIDAQmx.h>
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#define DAQmxErrChk(functionCall) \
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do { if( DAQmxFailed(error=(functionCall)) ) \
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goto Error; } while(0)
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#endif
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/**
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* This structure encapsulates the data that is private to
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* the implementation of the device
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*/
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typedef struct device_private_t
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{
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/** extended 64-bit counter value */
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unsigned long long count64;
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/** NIDAQ device number of card */
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int card_number;
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/** NI channel number on card */
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int channel_number;
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/** true if using external sync else timer based sampling */
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bool sync;
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/** sync line number on the card */
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int sync_line_number;
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/** output line number on the card */
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int output_line_number;
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/** Actual physical counter value, as returned by read function */
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uInt32 count32;
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#ifdef REGISTER_LEVEL_PROGRAMMING
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CARD* card;
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#else
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/** NIDAQ opaque task handle */
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TaskHandle taskHandle;
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/** NIDAQ opaque task handle for digital output */
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TaskHandle taskHandle_dout;
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#endif
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} DEVICE_PRIVATE;
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#ifdef REGISTER_LEVEL_PROGRAMMING
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static bool initPCI(pHWARE ptr, const char *name);
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static void initCard(pHWARE ptr);
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static void initChan(pHWARE ptr);
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static CARD* card[10];
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#else
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typedef struct mapping_t {
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int cntr_num;
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int sync_num;
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int outp_num;
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} MAPPING;
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static MAPPING mapping[8] = {
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{ 0, 37, 36 },
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{ 1, 33, 32 },
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{ 2, 29, 28 },
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{ 3, 25, 24 },
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{ 4, 21, 20 },
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{ 5, 17, 16 },
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{ 6, 13, 12 },
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{ 7, 9, 8 }
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};
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#endif
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int hware_ctor(const char* device_name, pHWARE* ptr)
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{
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pHWARE hware = NULL;
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#ifdef REGISTER_LEVEL_PROGRAMMING
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CARD* pci = NULL;
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#endif
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int error = 0;
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bool flag = false;
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char text_string[] = DEFAULT_DEVICE;
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const char *name;
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const char *text;
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hware = (DEVICE_PRIVATE*) malloc(sizeof(DEVICE_PRIVATE));
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*ptr = hware;
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memset(hware, 0, sizeof(DEVICE_PRIVATE));
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name = device_name;
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text = text_string;
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while (name && *name)
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{
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if (isspace(*name))
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++name;
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else if (*name >= '0' && *name <= '9')
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{
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if (flag)
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{
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hware->channel_number = *name - '0';
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}
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else
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{
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hware->card_number = *name - '0';
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flag = true;
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}
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}
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else if (tolower(*name) != *text)
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{
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/* TODO error */
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printf("Device name error: %s (%d,%d)\n",
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device_name,
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hware->channel_number,
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hware->card_number);
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break;
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}
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++name;
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++text;
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}
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#ifdef REGISTER_LEVEL_PROGRAMMING
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if (card[hware->card_number] == NULL)
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{
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char local_name[40] = "PXI6::1::INSTR";
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FILE* fd = fopen("/proc/nirlpk/lsdaq", "r");
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if (fd)
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{
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bool found = false;
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int count = 0;
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char line[100];
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while (fgets(line, 100, fd))
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{
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if (strstr(line, DEVICE_ID_NUMBER))
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{
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++count;
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name = strstr(line, "PXI");
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if (name && count == hware->card_number)
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{
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found = true;
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strcpy(local_name, name);
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break;
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}
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}
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if (!found)
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{
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// TODO error
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}
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}
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fclose(fd);
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}
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card[hware->card_number] = (CARD*) malloc(sizeof(CARD));
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memset(card[hware->card_number], 0, sizeof(CARD));
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pci = card[hware->card_number];
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hware->card = pci;
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if(!initPCI(hware, local_name))
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{
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printf("Error accessing the PCI device \"%s\". Exiting.\n",
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local_name);
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error = 1;
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goto Error;
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}
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initCard(hware);
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}
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else
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{
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pci = card[hware->card_number];
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hware->card = pci;
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}
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// Mark the counter on this card as in-use
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if (pci->dev_mask & (1 << hware->channel_number))
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{
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// TODO error
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}
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pci->dev_mask |= 1 << hware->channel_number;
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initChan(hware);
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#else
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do {
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char local_name[40];
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hware->sync_line_number = mapping[hware->channel_number].sync_num;
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hware->output_line_number = mapping[hware->channel_number].outp_num;
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/*********************************************/
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// Create a DAQmx task
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/*********************************************/
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DAQmxErrChk (DAQmxCreateTask("",&hware->taskHandle));
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DAQmxErrChk (DAQmxCreateTask("",&hware->taskHandle_dout));
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/*********************************************/
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// Create a DAQmx device within the task
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/*********************************************/
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DAQmxErrChk (
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DAQmxCreateCICountEdgesChan(hware->taskHandle,
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device_name,
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"",
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DAQmx_Val_Rising,
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hware->count32,
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DAQmx_Val_CountUp));
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/*********************************************/
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// Create the digital output channel within the task
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/*********************************************/
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snprintf(local_name, sizeof(local_name),
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"dev%d/line%d",
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hware->card_number,
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hware->channel_number);
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DAQmxErrChk (
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DAQmxCreateDOChan(hware->taskHandle_dout,
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local_name,
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"",
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DAQmx_Val_ChanPerLine));
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/*********************************************/
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// Start the DAQmx task
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/*********************************************/
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DAQmxErrChk (DAQmxStartTask(hware->taskHandle));
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DAQmxErrChk (DAQmxStartTask(hware->taskHandle_dout));
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hware_outp(hware, 0);
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} while (0);
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#endif
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return 0;
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Error:
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free(hware);
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*ptr = NULL;
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return error;
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}
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int hware_read(pHWARE hware, unsigned long long* value)
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{
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int error = 0;
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uInt32 counterValue1;
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*value = hware->count64;
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#ifdef REGISTER_LEVEL_PROGRAMMING
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uInt32 counterValue2;
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CARD* pci = hware->card;
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//read counter value
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//Use this method to read the value of an armed counter
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//during non-buffered counting. Since the value of the counter may
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//change during the read, we make sure that the value is stable.
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switch (hware->channel_number)
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{
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case 0:
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counterValue1 = pci->tio_1->G0_Save_Registers.readRegister();
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counterValue2 = pci->tio_1->G0_Save_Registers.readRegister();
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if (counterValue1 != counterValue2)
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counterValue1 = pci->tio_1->G0_Save_Registers.readRegister();
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break;
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case 1:
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counterValue1 = pci->tio_1->G1_Save_Registers.readRegister();
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counterValue2 = pci->tio_1->G1_Save_Registers.readRegister();
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if (counterValue1 != counterValue2)
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counterValue1 = pci->tio_1->G1_Save_Registers.readRegister();
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break;
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case 2:
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counterValue1 = pci->tio_1->G2_Save_Registers.readRegister();
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counterValue2 = pci->tio_1->G2_Save_Registers.readRegister();
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if (counterValue1 != counterValue2)
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counterValue1 = pci->tio_1->G2_Save_Registers.readRegister();
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break;
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case 3:
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counterValue1 = pci->tio_1->G3_Save_Registers.readRegister();
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counterValue2 = pci->tio_1->G3_Save_Registers.readRegister();
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if (counterValue1 != counterValue2)
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counterValue1 = pci->tio_1->G3_Save_Registers.readRegister();
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break;
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case 4:
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counterValue1 = pci->tio_2->G0_Save_Registers.readRegister();
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counterValue2 = pci->tio_2->G0_Save_Registers.readRegister();
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if (counterValue1 != counterValue2)
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counterValue1 = pci->tio_2->G0_Save_Registers.readRegister();
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break;
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case 5:
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counterValue1 = pci->tio_2->G1_Save_Registers.readRegister();
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counterValue2 = pci->tio_2->G1_Save_Registers.readRegister();
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if (counterValue1 != counterValue2)
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counterValue1 = pci->tio_2->G1_Save_Registers.readRegister();
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break;
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case 6:
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counterValue1 = pci->tio_2->G2_Save_Registers.readRegister();
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counterValue2 = pci->tio_2->G2_Save_Registers.readRegister();
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if (counterValue1 != counterValue2)
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counterValue1 = pci->tio_2->G2_Save_Registers.readRegister();
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break;
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case 7:
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counterValue1 = pci->tio_2->G3_Save_Registers.readRegister();
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counterValue2 = pci->tio_2->G3_Save_Registers.readRegister();
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if (counterValue1 != counterValue2)
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counterValue1 = pci->tio_2->G3_Save_Registers.readRegister();
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break;
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}
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hware->count64 += counterValue1 - hware->count32;
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hware->count32 = counterValue1;
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*value = hware->count64;
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#else
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/*********************************************/
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// DAQmx Read Code
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/*********************************************/
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DAQmxErrChk (DAQmxReadCounterScalarU32(hware->taskHandle,
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1.0,
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&counterValue1,
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NULL));
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hware->count64 += counterValue1 - hware->count32;
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hware->count32 = counterValue1;
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*value = hware->count64;
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Error:
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#endif
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return error;
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} /* hware_read */
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/*
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* Select the source
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*/
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int hware_source(pHWARE hware, int value)
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{
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int error = 0;
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#ifdef REGISTER_LEVEL_PROGRAMMING
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CARD* pci = hware->card;
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int src = 1;
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if (value == 3)
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//set source to internal time base 3, the 80Mhz internal clock
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src = 30;
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else if (value == 2)
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//set source to internal time base 2, the l00Khz internal clock
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src = 18;
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else if (value == 1)
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//set source to internal time base 1, the 20Mhz internal clock
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src = 0;
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else
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//set source to external default source pin
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src = 1;
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switch (hware->channel_number)
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{
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case 0:
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pci->tio_1->G0_Input_Select_Register.writeG0_Source_Select(src);
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break;
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case 1:
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pci->tio_1->G1_Input_Select_Register.writeG1_Source_Select(src);
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break;
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case 2:
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pci->tio_1->G2_Input_Select_Register.writeG2_Source_Select(src);
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break;
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case 3:
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pci->tio_1->G3_Input_Select_Register.writeG3_Source_Select(src);
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break;
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case 4:
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pci->tio_2->G0_Input_Select_Register.writeG0_Source_Select(src);
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break;
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case 5:
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pci->tio_2->G1_Input_Select_Register.writeG1_Source_Select(src);
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break;
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case 6:
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pci->tio_2->G2_Input_Select_Register.writeG2_Source_Select(src);
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break;
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case 7:
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pci->tio_2->G3_Input_Select_Register.writeG3_Source_Select(src);
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break;
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}
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#else
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// TODO
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// DAQmxGetDevCIPhysicalChans
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// DAQmxSetCICountEdgesTerm
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//Error:
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#endif
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return error;
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}
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/*
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* Select the filter
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*/
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int hware_filter(pHWARE hware, int value)
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{
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int error = 0;
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#ifdef REGISTER_LEVEL_PROGRAMMING
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CARD* pci = hware->card;
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int src = 0;
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if (value > 0 && value < 7)
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src = value;
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switch (hware->channel_number)
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{
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case 0:
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pci->tio_1->IO_Pin_38_39_Configuration_Register.writeIO_Filter_39_Select(src);
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break;
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case 1:
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pci->tio_1->IO_Pin_34_35_Configuration_Register.writeIO_Filter_35_Select(src);
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break;
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case 2:
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pci->tio_1->IO_Pin_30_31_Configuration_Register.writeIO_Filter_31_Select(src);
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break;
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case 3:
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pci->tio_1->IO_Pin_26_27_Configuration_Register.writeIO_Filter_27_Select(src);
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break;
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case 4:
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pci->tio_2->IO_Pin_22_23_Configuration_Register.writeIO_Filter_23_Select(src);
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break;
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case 5:
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pci->tio_2->IO_Pin_18_19_Configuration_Register.writeIO_Filter_19_Select(src);
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break;
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case 6:
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pci->tio_2->IO_Pin_14_15_Configuration_Register.writeIO_Filter_15_Select(src);
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break;
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case 7:
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pci->tio_2->IO_Pin_10_11_Configuration_Register.writeIO_Filter_11_Select(src);
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break;
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}
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#else
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// TODO
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// DAQmxGetDevCIPhysicalChans
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// DAQmxSetCICountEdgesTerm
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//Error:
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#endif
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return error;
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}
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/*
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* Set the output line corresponding to the counter
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*/
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int hware_outp(pHWARE hware, int value)
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{
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int error = 0;
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#ifdef REGISTER_LEVEL_PROGRAMMING
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CARD* pci = hware->card;
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u16 data;
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if (value < 0)
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{
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// set the disabled line to input
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value = 0;
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pci->dio_mask &= ~(1 << hware->channel_number);
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pci->tio_1->DIO_Control_Register.writeDIO_Pins_Dir(pci->dio_mask);
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}
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else
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{
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pci->dio_mask |= 1 << hware->channel_number;
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pci->tio_1->DIO_Control_Register.writeDIO_Pins_Dir(pci->dio_mask);
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data = pci->tio_1->DIO_Output_Register.readDIO_Parallel_Data_Out();
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printf("data %04x", data);
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if (value > 0)
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data |= 1 << hware->channel_number;
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else
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data &= ~(1 << hware->channel_number);
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pci->tio_1->DIO_Output_Register.writeDIO_Parallel_Data_Out(data);
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printf(" => %04x", data);
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data = pci->tio_1->DIO_Output_Register.readDIO_Parallel_Data_Out();
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printf(" => %04x\n", data);
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}
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#else
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uInt8 data;
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if (value < 0)
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{
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// set the disabled line to logic low
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data = 0;
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DAQmxWriteDigitalLines(hware->taskHandle_dout,
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1,
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1,
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10.0,
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DAQmx_Val_GroupByChannel,
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&data,
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NULL,
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NULL);
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}
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else
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{
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if (value > 0)
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data = 1;
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else
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data = 0;
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DAQmxErrChk (
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DAQmxWriteDigitalScalarU32(hware->taskHandle_dout,
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1,
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10.0,
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data,
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NULL));
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}
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Error:
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#endif
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return error;
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}
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/*
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* Set up to read the counter synchronized to an external signal
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*/
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void hware_sync(pHWARE hware, bool external)
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{
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#if REGISTER_LEVEL_PROGRAMMING
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//CARD* pci = hware->card;
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// TODO RLP
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#else
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int error = 0;
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char device_name[40];
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if (hware->sync != external)
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{
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hware->sync = external;
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/*********************************************/
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// DAQmx Stop Code
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/*********************************************/
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DAQmxStopTask(hware->taskHandle);
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DAQmxClearTask(hware->taskHandle);
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/*********************************************/
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// Create a DAQmx task to hold the counter
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/*********************************************/
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DAQmxErrChk (DAQmxCreateTask("",&hware->taskHandle));
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|
|
/*********************************************/
|
|
// Create a DAQmx counter within the task
|
|
/*********************************************/
|
|
hware->count32 = 0;
|
|
snprintf(device_name, sizeof(device_name), "dev%d/ctr%d",
|
|
hware->card_number, hware->channel_number);
|
|
DAQmxErrChk (
|
|
DAQmxCreateCICountEdgesChan(hware->taskHandle,
|
|
device_name,
|
|
"",
|
|
DAQmx_Val_Rising,
|
|
hware->count32,
|
|
DAQmx_Val_CountUp));
|
|
|
|
if (external)
|
|
{
|
|
char str[40];
|
|
snprintf(str, sizeof(str), "dev%d/PFI%d",
|
|
hware->card_number, hware->sync_line_number);
|
|
DAQmxErrChk (
|
|
DAQmxCfgSampClkTiming(hware->taskHandle,
|
|
str,
|
|
10000,
|
|
DAQmx_Val_Rising,
|
|
DAQmx_Val_ContSamps,
|
|
10000));
|
|
}
|
|
/*********************************************/
|
|
// Start the DAQmx task
|
|
/*********************************************/
|
|
DAQmxErrChk (DAQmxStartTask(hware->taskHandle));
|
|
|
|
}
|
|
Error:
|
|
#endif
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Shut down the channel
|
|
*/
|
|
int hware_dtor(pHWARE* ptr)
|
|
{
|
|
if (ptr && *ptr)
|
|
{
|
|
pHWARE hware = *ptr;
|
|
#ifdef REGISTER_LEVEL_PROGRAMMING
|
|
CARD* pci = hware->card;
|
|
switch (hware->channel_number)
|
|
{
|
|
case 0:
|
|
pci->tio_1->G0_Command_Register.writeG0_Disarm(1);
|
|
break;
|
|
case 1:
|
|
pci->tio_1->G1_Command_Register.writeG1_Disarm(1);
|
|
break;
|
|
case 2:
|
|
pci->tio_1->G2_Command_Register.writeG2_Disarm(1);
|
|
break;
|
|
case 3:
|
|
pci->tio_1->G3_Command_Register.writeG3_Disarm(1);
|
|
break;
|
|
case 4:
|
|
pci->tio_2->G0_Command_Register.writeG0_Disarm(1);
|
|
break;
|
|
case 5:
|
|
pci->tio_2->G1_Command_Register.writeG1_Disarm(1);
|
|
break;
|
|
case 6:
|
|
pci->tio_2->G2_Command_Register.writeG2_Disarm(1);
|
|
break;
|
|
case 7:
|
|
pci->tio_2->G3_Command_Register.writeG3_Disarm(1);
|
|
break;
|
|
}
|
|
|
|
pci->dev_mask &= ~(1 << hware->channel_number);
|
|
if (pci->dev_mask == 0)
|
|
{
|
|
delete pci->tio_1;
|
|
delete pci->tio_2;
|
|
pci->bus->destroyAddressSpace(pci->Bar1);
|
|
pci->bus->destroyAddressSpace(pci->Bar2);
|
|
|
|
releaseBoard(pci->bus);
|
|
card[hware->card_number] = NULL;
|
|
free(pci);
|
|
}
|
|
#else
|
|
if (hware->taskHandle != 0)
|
|
{
|
|
/*********************************************/
|
|
// DAQmx Stop Code
|
|
/*********************************************/
|
|
DAQmxStopTask(hware->taskHandle);
|
|
DAQmxClearTask(hware->taskHandle);
|
|
hware->taskHandle = 0;
|
|
}
|
|
if (hware->taskHandle_dout != 0)
|
|
{
|
|
/*********************************************/
|
|
// DAQmx Stop Code
|
|
/*********************************************/
|
|
DAQmxStopTask(hware->taskHandle_dout);
|
|
DAQmxClearTask(hware->taskHandle_dout);
|
|
hware->taskHandle_dout = 0;
|
|
}
|
|
|
|
#endif
|
|
|
|
/* release the storage */
|
|
free(hware);
|
|
*ptr = NULL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
bool hware_failed(int error)
|
|
{
|
|
if (DAQmxFailed(error))
|
|
return true;
|
|
else
|
|
return false;
|
|
}
|
|
|
|
void hware_errmsg(char* buff, int len)
|
|
{
|
|
*buff = '\0';
|
|
DAQmxGetExtendedErrorInfo(buff, len);
|
|
}
|
|
|
|
#ifdef REGISTER_LEVEL_PROGRAMMING
|
|
//
|
|
//Tell the MITE to link the BAR1 address to the DAQ Board
|
|
//You must initialize the MITE before you write to the rest of the PCI board
|
|
void initMite(iBus *bus)
|
|
{
|
|
tAddressSpace Bar0;
|
|
u32 physicalBar1;
|
|
|
|
//Skip MITE initialization for PCMCIA boards
|
|
//(which do not have a MITE DMA controller)
|
|
if(!bus->get(kIsPciPxiBus,0)) return;
|
|
|
|
Bar0 = bus->createAddressSpace(kPCI_BAR0);
|
|
|
|
//Get the physical address of the DAQ board
|
|
physicalBar1 = bus->get(kBusAddressPhysical,kPCI_BAR1);
|
|
|
|
// ***** 6602/6608 specific MITE initialization *****
|
|
// Hit the IO Window Base/Size Register 1 (IOWBSR1) in the MITE. We set the
|
|
// address, enable the window and set the size of the window:
|
|
Bar0.write32(0xC4, (physicalBar1 & 0xffffff00L) | 0x8C);
|
|
|
|
// Write to the IO Window Control Register 1 (IOWCR1) to make the IO window
|
|
// go to RAM memory space instead of the config space
|
|
Bar0.write32(0xF4, 0);
|
|
|
|
// ***** End of 6602/6608 specific code *****
|
|
|
|
bus->destroyAddressSpace(Bar0);
|
|
}
|
|
|
|
bool initPCI(pHWARE hware, const char* name)
|
|
{
|
|
CARD* pci = hware->card;
|
|
pci->bus = acquireBoard((tChar*) name);
|
|
|
|
if(pci->bus == NULL)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
//Intitialise Mite Chip.
|
|
|
|
initMite(pci->bus);
|
|
return true;
|
|
}
|
|
|
|
void initCard(pHWARE hware)
|
|
{
|
|
CARD* pci = hware->card;
|
|
pci->Bar1 = pci->bus->createAddressSpace(kPCI_BAR1);
|
|
pci->Bar2 = pci->bus->createAddressSpace(kPCI_BAR1);
|
|
pci->tio_1 = new tTIO(pci->Bar1);
|
|
pci->tio_2 = new tTIO(pci->Bar2);
|
|
pci->tio_2->setAddressOffset(0x800);
|
|
//
|
|
// Set all counter outputs to 'input' so we don't accidentally double drive an IO pin
|
|
|
|
pci->tio_1->IO_Pin_8_9_Configuration_Register.writeIO_Pin_8_Select(0); //0='input'
|
|
pci->tio_1->IO_Pin_12_13_Configuration_Register.writeIO_Pin_12_Select(0); //0='input'
|
|
pci->tio_1->IO_Pin_16_17_Configuration_Register.writeIO_Pin_16_Select(0); //0='input'
|
|
pci->tio_1->IO_Pin_20_21_Configuration_Register.writeIO_Pin_20_Select(0); //0='input'
|
|
|
|
pci->tio_1->IO_Pin_24_25_Configuration_Register.writeIO_Pin_24_Select(0); //0='input'
|
|
pci->tio_1->IO_Pin_28_29_Configuration_Register.writeIO_Pin_28_Select(0); //0='input'
|
|
pci->tio_1->IO_Pin_32_33_Configuration_Register.writeIO_Pin_32_Select(0); //0='input'
|
|
pci->tio_1->IO_Pin_36_37_Configuration_Register.writeIO_Pin_36_Select(0); //0='input'
|
|
|
|
pci->tio_2->IO_Pin_8_9_Configuration_Register.writeIO_Pin_8_Select(0); //0='input'
|
|
pci->tio_2->IO_Pin_12_13_Configuration_Register.writeIO_Pin_12_Select(0); //0='input'
|
|
pci->tio_2->IO_Pin_16_17_Configuration_Register.writeIO_Pin_16_Select(0); //0='input'
|
|
pci->tio_2->IO_Pin_20_21_Configuration_Register.writeIO_Pin_20_Select(0); //0='input'
|
|
|
|
pci->tio_2->IO_Pin_24_25_Configuration_Register.writeIO_Pin_24_Select(0); //0='input'
|
|
pci->tio_2->IO_Pin_28_29_Configuration_Register.writeIO_Pin_28_Select(0); //0='input'
|
|
pci->tio_2->IO_Pin_32_33_Configuration_Register.writeIO_Pin_32_Select(0); //0='input'
|
|
pci->tio_2->IO_Pin_36_37_Configuration_Register.writeIO_Pin_36_Select(0); //0='input'
|
|
|
|
//Bind the first TIO to counters 0-3 on the IO connector, and
|
|
//bind the second TIO to counters 4-7
|
|
pci->tio_1->Clock_Configuration_Register.writeCntr_Swap(0);
|
|
pci->tio_2->Clock_Configuration_Register.writeCntr_Swap(1);
|
|
}
|
|
|
|
void initChan(pHWARE hware)
|
|
{
|
|
CARD* pci = hware->card;
|
|
/*
|
|
* Set up the channel object
|
|
*/
|
|
switch (hware->channel_number)
|
|
{
|
|
case 0:
|
|
//Disarm
|
|
pci->tio_1->G0_Command_Register.writeG0_Disarm(1);
|
|
//load initial value of zero
|
|
pci->tio_1->G0_Load_A_Registers.writeG0_Load_A(0x00000000);
|
|
pci->tio_1->G0_Command_Register.writeG0_Load(1);
|
|
//set source to external default source pin
|
|
pci->tio_1->G0_Input_Select_Register.writeG0_Source_Select(1);
|
|
//set gate to no gate
|
|
pci->tio_1->G0_Input_Select_Register.writeG0_Gate_Select(30);
|
|
pci->tio_1->G0_Mode_Register.writeG0_Gate_Polarity(1);
|
|
pci->tio_1->G0_Mode_Register.writeG0_Trigger_Mode_For_Edge_Gate(3);
|
|
//set counting direction to up
|
|
pci->tio_1->G0_Command_Register.writeG0_Up_Down(1);
|
|
//arm counter
|
|
pci->tio_1->G0_Command_Register.writeG0_Arm(1);
|
|
break;
|
|
case 1:
|
|
//Disarm
|
|
pci->tio_1->G1_Command_Register.writeG1_Disarm(1);
|
|
//load initial value of zero
|
|
pci->tio_1->G1_Load_A_Registers.writeG1_Load_A(0x00000000);
|
|
pci->tio_1->G1_Command_Register.writeG1_Load(1);
|
|
//set source to external default source pin
|
|
pci->tio_1->G1_Input_Select_Register.writeG1_Source_Select(1);
|
|
//set gate to no gate
|
|
pci->tio_1->G1_Input_Select_Register.writeG1_Gate_Select(30);
|
|
pci->tio_1->G1_Mode_Register.writeG1_Gate_Polarity(1);
|
|
pci->tio_1->G1_Mode_Register.writeG1_Trigger_Mode_For_Edge_Gate(3);
|
|
//set counting direction to up
|
|
pci->tio_1->G1_Command_Register.writeG1_Up_Down(1);
|
|
//arm counter
|
|
pci->tio_1->G1_Command_Register.writeG1_Arm(1);
|
|
break;
|
|
case 2:
|
|
//Disarm
|
|
pci->tio_1->G2_Command_Register.writeG2_Disarm(1);
|
|
//load initial value of zero
|
|
pci->tio_1->G2_Load_A_Registers.writeG2_Load_A(0x00000000);
|
|
pci->tio_1->G2_Command_Register.writeG2_Load(1);
|
|
//set source to external default source pin
|
|
pci->tio_1->G2_Input_Select_Register.writeG2_Source_Select(1);
|
|
//set gate to no gate
|
|
pci->tio_1->G2_Input_Select_Register.writeG2_Gate_Select(30);
|
|
pci->tio_1->G2_Mode_Register.writeG2_Gate_Polarity(1);
|
|
pci->tio_1->G2_Mode_Register.writeG2_Trigger_Mode_For_Edge_Gate(3);
|
|
//set counting direction to up
|
|
pci->tio_1->G2_Command_Register.writeG2_Up_Down(1);
|
|
//arm counter
|
|
pci->tio_1->G2_Command_Register.writeG2_Arm(1);
|
|
break;
|
|
case 3:
|
|
//Disarm
|
|
pci->tio_1->G3_Command_Register.writeG3_Disarm(1);
|
|
//load initial value of zero
|
|
pci->tio_1->G3_Load_A_Registers.writeG3_Load_A(0x00000000);
|
|
pci->tio_1->G3_Command_Register.writeG3_Load(1);
|
|
//set source to external default source pin
|
|
pci->tio_1->G3_Input_Select_Register.writeG3_Source_Select(1);
|
|
//set gate to no gate
|
|
pci->tio_1->G3_Input_Select_Register.writeG3_Gate_Select(30);
|
|
pci->tio_1->G3_Mode_Register.writeG3_Gate_Polarity(1);
|
|
pci->tio_1->G3_Mode_Register.writeG3_Trigger_Mode_For_Edge_Gate(3);
|
|
//set counting direction to up
|
|
pci->tio_1->G3_Command_Register.writeG3_Up_Down(1);
|
|
//arm counter
|
|
pci->tio_1->G3_Command_Register.writeG3_Arm(1);
|
|
break;
|
|
case 4:
|
|
//Disarm
|
|
pci->tio_2->G0_Command_Register.writeG0_Disarm(1);
|
|
//load initial value of zero
|
|
pci->tio_2->G0_Load_A_Registers.writeG0_Load_A(0x00000000);
|
|
pci->tio_2->G0_Command_Register.writeG0_Load(1);
|
|
//set source to external default source pin
|
|
pci->tio_2->G0_Input_Select_Register.writeG0_Source_Select(1);
|
|
//set gate to no gate
|
|
pci->tio_2->G0_Input_Select_Register.writeG0_Gate_Select(30);
|
|
pci->tio_2->G0_Mode_Register.writeG0_Gate_Polarity(1);
|
|
pci->tio_2->G0_Mode_Register.writeG0_Trigger_Mode_For_Edge_Gate(3);
|
|
//set counting direction to up
|
|
pci->tio_2->G0_Command_Register.writeG0_Up_Down(1);
|
|
//arm counter
|
|
pci->tio_2->G0_Command_Register.writeG0_Arm(1);
|
|
break;
|
|
case 5:
|
|
//Disarm
|
|
pci->tio_2->G1_Command_Register.writeG1_Disarm(1);
|
|
//load initial value of zero
|
|
pci->tio_2->G1_Load_A_Registers.writeG1_Load_A(0x00000000);
|
|
pci->tio_2->G1_Command_Register.writeG1_Load(1);
|
|
//set source to external default source pin
|
|
pci->tio_2->G1_Input_Select_Register.writeG1_Source_Select(1);
|
|
//set gate to no gate
|
|
pci->tio_2->G1_Input_Select_Register.writeG1_Gate_Select(30);
|
|
pci->tio_2->G1_Mode_Register.writeG1_Gate_Polarity(1);
|
|
pci->tio_2->G1_Mode_Register.writeG1_Trigger_Mode_For_Edge_Gate(3);
|
|
//set counting direction to up
|
|
pci->tio_2->G1_Command_Register.writeG1_Up_Down(1);
|
|
//arm counter
|
|
pci->tio_2->G1_Command_Register.writeG1_Arm(1);
|
|
break;
|
|
case 6:
|
|
//Disarm
|
|
pci->tio_2->G2_Command_Register.writeG2_Disarm(1);
|
|
//load initial value of zero
|
|
pci->tio_2->G2_Load_A_Registers.writeG2_Load_A(0x00000000);
|
|
pci->tio_2->G2_Command_Register.writeG2_Load(1);
|
|
//set source to external default source pin
|
|
pci->tio_2->G2_Input_Select_Register.writeG2_Source_Select(1);
|
|
//set gate to no gate
|
|
pci->tio_2->G2_Input_Select_Register.writeG2_Gate_Select(30);
|
|
pci->tio_2->G2_Mode_Register.writeG2_Gate_Polarity(1);
|
|
pci->tio_2->G2_Mode_Register.writeG2_Trigger_Mode_For_Edge_Gate(3);
|
|
//set counting direction to up
|
|
pci->tio_2->G2_Command_Register.writeG2_Up_Down(1);
|
|
//arm counter
|
|
pci->tio_2->G2_Command_Register.writeG2_Arm(1);
|
|
break;
|
|
case 7:
|
|
//Disarm
|
|
pci->tio_2->G3_Command_Register.writeG3_Disarm(1);
|
|
//load initial value of zero
|
|
pci->tio_2->G3_Load_A_Registers.writeG3_Load_A(0x00000000);
|
|
pci->tio_2->G3_Command_Register.writeG3_Load(1);
|
|
//set source to external default source pin
|
|
pci->tio_2->G3_Input_Select_Register.writeG3_Source_Select(1);
|
|
//set gate to no gate
|
|
pci->tio_2->G3_Input_Select_Register.writeG3_Gate_Select(30);
|
|
pci->tio_2->G3_Mode_Register.writeG3_Gate_Polarity(1);
|
|
pci->tio_2->G3_Mode_Register.writeG3_Trigger_Mode_For_Edge_Gate(3);
|
|
//set counting direction to up
|
|
pci->tio_2->G3_Command_Register.writeG3_Up_Down(1);
|
|
//arm counter
|
|
pci->tio_2->G3_Command_Register.writeG3_Arm(1);
|
|
break;
|
|
}
|
|
}
|
|
#else
|
|
#endif
|
|
#else /* SIMULATE_HARDWARE */
|
|
#include <sys/time.h>
|
|
typedef struct device_private_t
|
|
{
|
|
/** extended 64-bit counter value */
|
|
unsigned long long count64;
|
|
/* TODO time and count */
|
|
int source; /* count rate to be simulated */
|
|
struct timeval last_time;
|
|
} DEVICE_PRIVATE;
|
|
|
|
int hware_ctor(const char* device_name, pHWARE* ptr)
|
|
{
|
|
pHWARE hware = NULL;
|
|
|
|
hware = (DEVICE_PRIVATE*) malloc(sizeof(DEVICE_PRIVATE));
|
|
*ptr = hware;
|
|
memset(hware, 0, sizeof(DEVICE_PRIVATE));
|
|
|
|
/* TODO time and count */
|
|
hware->source = 1000; /* initial count rate */
|
|
gettimeofday(&hware->last_time, NULL);
|
|
#if 0 /* DEBUG */
|
|
printf("hware_ctor: %s at %p\n", device_name, *ptr);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int hware_read(pHWARE hware, unsigned long long* value)
|
|
{
|
|
struct timeval this_time;
|
|
double delta_time;
|
|
long long delta_count = 0;
|
|
/* TODO time and count */
|
|
gettimeofday(&this_time, NULL);
|
|
delta_time = (this_time.tv_sec + 1e-6 * this_time.tv_usec) -
|
|
(hware->last_time.tv_sec + 1e-6 * hware->last_time.tv_usec);
|
|
delta_count = (long long)(0.5 + delta_time * hware->source);
|
|
hware->count64 += delta_count;
|
|
hware->last_time = this_time;
|
|
*value = hware->count64;
|
|
return 0;
|
|
}
|
|
int hware_source(pHWARE hware, int value)
|
|
{
|
|
#if 0 /* DEBUG */
|
|
int old_source = hware->source;
|
|
#endif
|
|
switch (value)
|
|
{
|
|
case 0:
|
|
hware->source = 10000;
|
|
break;
|
|
case 1:
|
|
hware->source = 20000000;
|
|
break;
|
|
case 2:
|
|
hware->source = 100000;
|
|
break;
|
|
case 3:
|
|
hware->source = 80000000;
|
|
break;
|
|
default:
|
|
if (value < 1000)
|
|
hware->source = 1000;
|
|
else
|
|
hware->source = value;
|
|
break;
|
|
}
|
|
#if 0 /* DEBUG */
|
|
printf("hware_source: %d moves %d to %d at %p\n", value, old_source, hware->source, hware);
|
|
#endif
|
|
return 0;
|
|
}
|
|
int hware_filter(pHWARE hware, int value)
|
|
{
|
|
/* nothing to do */
|
|
return 0;
|
|
}
|
|
int hware_outp(pHWARE hware, int value)
|
|
{
|
|
/* nothing to do */
|
|
return 0;
|
|
}
|
|
void hware_sync(pHWARE hware, bool external)
|
|
{
|
|
/* nothing to do */
|
|
}
|
|
int hware_dtor(pHWARE* ptr)
|
|
{
|
|
if (ptr && *ptr)
|
|
{
|
|
/* release the storage */
|
|
free(*ptr);
|
|
*ptr = NULL;
|
|
}
|
|
return 0;
|
|
}
|
|
bool hware_failed(int error)
|
|
{
|
|
return false;
|
|
}
|
|
void hware_errmsg(char* buff, int len)
|
|
{
|
|
if (buff)
|
|
strncpy(buff, "Simulated error message", len);
|
|
}
|
|
#endif
|