diff --git a/site_ansto/instrument/TEST_SICS/fakeRFGen/SIM_RFGen.tcl b/site_ansto/instrument/TEST_SICS/fakeRFGen/SIM_RFGen.tcl
index b1a83c40..6f64ca1a 100644
--- a/site_ansto/instrument/TEST_SICS/fakeRFGen/SIM_RFGen.tcl
+++ b/site_ansto/instrument/TEST_SICS/fakeRFGen/SIM_RFGen.tcl
@@ -1,5 +1,5 @@
-# $Revision: 1.1.2.2 $
-# $Date: 2010-05-14 02:31:24 $
+# $Revision: 1.1.2.3 $
+# $Date: 2010-05-14 02:36:39 $
 # Author: Ferdi Franceschini (ffr@ansto.gov.au)
 # Last revision by: $Author: ffr $
 
@@ -30,7 +30,7 @@ proc readLine {channel} {
   global VOLTAGE
   global bSWITCHES
   global bOPSTATE
-  set TESTMODE "fail"
+  set TESTMODE "normal"
 
   set data [read $channel 1]
   binary scan $data c sigStart
@@ -126,4 +126,4 @@ proc startserver {args} {
   return;
 }
 
-startserver -port 65012
+startserver -port 65001